1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38#include <linux/pinctrl/consumer.h> 39 40#include <linux/can.h> 41#include <linux/can/dev.h> 42#include <linux/can/error.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_SWR BIT(15) 55#define CONTROL_TEST BIT(7) 56#define CONTROL_CCE BIT(6) 57#define CONTROL_DISABLE_AR BIT(5) 58#define CONTROL_ENABLE_AR (0 << 5) 59#define CONTROL_EIE BIT(3) 60#define CONTROL_SIE BIT(2) 61#define CONTROL_IE BIT(1) 62#define CONTROL_INIT BIT(0) 63 64#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 65 66/* test register */ 67#define TEST_RX BIT(7) 68#define TEST_TX1 BIT(6) 69#define TEST_TX2 BIT(5) 70#define TEST_LBACK BIT(4) 71#define TEST_SILENT BIT(3) 72#define TEST_BASIC BIT(2) 73 74/* status register */ 75#define STATUS_PDA BIT(10) 76#define STATUS_BOFF BIT(7) 77#define STATUS_EWARN BIT(6) 78#define STATUS_EPASS BIT(5) 79#define STATUS_RXOK BIT(4) 80#define STATUS_TXOK BIT(3) 81 82/* error counter register */ 83#define ERR_CNT_TEC_MASK 0xff 84#define ERR_CNT_TEC_SHIFT 0 85#define ERR_CNT_REC_SHIFT 8 86#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 87#define ERR_CNT_RP_SHIFT 15 88#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 89 90/* bit-timing register */ 91#define BTR_BRP_MASK 0x3f 92#define BTR_BRP_SHIFT 0 93#define BTR_SJW_SHIFT 6 94#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 95#define BTR_TSEG1_SHIFT 8 96#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 97#define BTR_TSEG2_SHIFT 12 98#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 99 100/* interrupt register */ 101#define INT_STS_PENDING 0x8000 102 103/* brp extension register */ 104#define BRP_EXT_BRPE_MASK 0x0f 105#define BRP_EXT_BRPE_SHIFT 0 106 107/* IFx command request */ 108#define IF_COMR_BUSY BIT(15) 109 110/* IFx command mask */ 111#define IF_COMM_WR BIT(7) 112#define IF_COMM_MASK BIT(6) 113#define IF_COMM_ARB BIT(5) 114#define IF_COMM_CONTROL BIT(4) 115#define IF_COMM_CLR_INT_PND BIT(3) 116#define IF_COMM_TXRQST BIT(2) 117#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 118#define IF_COMM_DATAA BIT(1) 119#define IF_COMM_DATAB BIT(0) 120 121/* TX buffer setup */ 122#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 123 IF_COMM_TXRQST | \ 124 IF_COMM_DATAA | IF_COMM_DATAB) 125 126/* For the low buffers we clear the interrupt bit, but keep newdat */ 127#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 128 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 129 IF_COMM_DATAA | IF_COMM_DATAB) 130 131/* For the high buffers we clear the interrupt bit and newdat */ 132#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 133 134/* Receive setup of message objects */ 135#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 136 137/* Invalidation of message objects */ 138#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 139 140/* IFx arbitration */ 141#define IF_ARB_MSGVAL BIT(31) 142#define IF_ARB_MSGXTD BIT(30) 143#define IF_ARB_TRANSMIT BIT(29) 144 145/* IFx message control */ 146#define IF_MCONT_NEWDAT BIT(15) 147#define IF_MCONT_MSGLST BIT(14) 148#define IF_MCONT_INTPND BIT(13) 149#define IF_MCONT_UMASK BIT(12) 150#define IF_MCONT_TXIE BIT(11) 151#define IF_MCONT_RXIE BIT(10) 152#define IF_MCONT_RMTEN BIT(9) 153#define IF_MCONT_TXRQST BIT(8) 154#define IF_MCONT_EOB BIT(7) 155#define IF_MCONT_DLC_MASK 0xf 156 157#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 158#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 159 160#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 161 162/* Use IF1 in NAPI path and IF2 in TX path */ 163#define IF_NAPI 0 164#define IF_TX 1 165 166/* minimum timeout for checking BUSY status */ 167#define MIN_TIMEOUT_VALUE 6 168 169/* Wait for ~1 sec for INIT bit */ 170#define INIT_WAIT_MS 1000 171 172/* c_can lec values */ 173enum c_can_lec_type { 174 LEC_NO_ERROR = 0, 175 LEC_STUFF_ERROR, 176 LEC_FORM_ERROR, 177 LEC_ACK_ERROR, 178 LEC_BIT1_ERROR, 179 LEC_BIT0_ERROR, 180 LEC_CRC_ERROR, 181 LEC_UNUSED, 182 LEC_MASK = LEC_UNUSED, 183}; 184 185/* c_can error types: 186 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 187 */ 188enum c_can_bus_error_types { 189 C_CAN_NO_ERROR = 0, 190 C_CAN_BUS_OFF, 191 C_CAN_ERROR_WARNING, 192 C_CAN_ERROR_PASSIVE, 193}; 194 195static const struct can_bittiming_const c_can_bittiming_const = { 196 .name = KBUILD_MODNAME, 197 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 198 .tseg1_max = 16, 199 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 200 .tseg2_max = 8, 201 .sjw_max = 4, 202 .brp_min = 1, 203 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 204 .brp_inc = 1, 205}; 206 207static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 208{ 209 if (priv->device) 210 pm_runtime_get_sync(priv->device); 211} 212 213static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 214{ 215 if (priv->device) 216 pm_runtime_put_sync(priv->device); 217} 218 219static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 220{ 221 if (priv->raminit) 222 priv->raminit(priv, enable); 223} 224 225static void c_can_irq_control(struct c_can_priv *priv, bool enable) 226{ 227 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 228 229 if (enable) 230 ctrl |= CONTROL_IRQMSK; 231 232 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 233} 234 235static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 236{ 237 struct c_can_priv *priv = netdev_priv(dev); 238 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 239 240 priv->write_reg32(priv, reg, (cmd << 16) | obj); 241 242 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 243 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 244 return; 245 udelay(1); 246 } 247 netdev_err(dev, "Updating object timed out\n"); 248} 249 250static inline void c_can_object_get(struct net_device *dev, int iface, 251 u32 obj, u32 cmd) 252{ 253 c_can_obj_update(dev, iface, cmd, obj); 254} 255 256static inline void c_can_object_put(struct net_device *dev, int iface, 257 u32 obj, u32 cmd) 258{ 259 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 260} 261 262/* Note: According to documentation clearing TXIE while MSGVAL is set 263 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O 264 * load significantly. 265 */ 266static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) 267{ 268 struct c_can_priv *priv = netdev_priv(dev); 269 270 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 271 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 272} 273 274static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 275{ 276 struct c_can_priv *priv = netdev_priv(dev); 277 278 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 279 c_can_inval_tx_object(dev, iface, obj); 280} 281 282static void c_can_setup_tx_object(struct net_device *dev, int iface, 283 struct can_frame *frame, int idx) 284{ 285 struct c_can_priv *priv = netdev_priv(dev); 286 u16 ctrl = IF_MCONT_TX | frame->len; 287 bool rtr = frame->can_id & CAN_RTR_FLAG; 288 u32 arb = IF_ARB_MSGVAL; 289 int i; 290 291 if (frame->can_id & CAN_EFF_FLAG) { 292 arb |= frame->can_id & CAN_EFF_MASK; 293 arb |= IF_ARB_MSGXTD; 294 } else { 295 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 296 } 297 298 if (!rtr) 299 arb |= IF_ARB_TRANSMIT; 300 301 /* If we change the DIR bit, we need to invalidate the buffer 302 * first, i.e. clear the MSGVAL flag in the arbiter. 303 */ 304 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { 305 u32 obj = idx + priv->msg_obj_tx_first; 306 307 c_can_inval_msg_object(dev, iface, obj); 308 change_bit(idx, &priv->tx_dir); 309 } 310 311 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 312 313 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 314 315 if (priv->type == BOSCH_D_CAN) { 316 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); 317 318 for (i = 0; i < frame->len; i += 4, dreg += 2) { 319 data = (u32)frame->data[i]; 320 data |= (u32)frame->data[i + 1] << 8; 321 data |= (u32)frame->data[i + 2] << 16; 322 data |= (u32)frame->data[i + 3] << 24; 323 priv->write_reg32(priv, dreg, data); 324 } 325 } else { 326 for (i = 0; i < frame->len; i += 2) { 327 priv->write_reg(priv, 328 C_CAN_IFACE(DATA1_REG, iface) + i / 2, 329 frame->data[i] | 330 (frame->data[i + 1] << 8)); 331 } 332 } 333} 334 335static int c_can_handle_lost_msg_obj(struct net_device *dev, 336 int iface, int objno, u32 ctrl) 337{ 338 struct net_device_stats *stats = &dev->stats; 339 struct c_can_priv *priv = netdev_priv(dev); 340 struct can_frame *frame; 341 struct sk_buff *skb; 342 343 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 344 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 345 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 346 347 stats->rx_errors++; 348 stats->rx_over_errors++; 349 350 /* create an error msg */ 351 skb = alloc_can_err_skb(dev, &frame); 352 if (unlikely(!skb)) 353 return 0; 354 355 frame->can_id |= CAN_ERR_CRTL; 356 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 357 358 netif_receive_skb(skb); 359 return 1; 360} 361 362static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 363{ 364 struct net_device_stats *stats = &dev->stats; 365 struct c_can_priv *priv = netdev_priv(dev); 366 struct can_frame *frame; 367 struct sk_buff *skb; 368 u32 arb, data; 369 370 skb = alloc_can_skb(dev, &frame); 371 if (!skb) { 372 stats->rx_dropped++; 373 return -ENOMEM; 374 } 375 376 frame->len = can_cc_dlc2len(ctrl & 0x0F); 377 378 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); 379 380 if (arb & IF_ARB_MSGXTD) 381 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 382 else 383 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 384 385 if (arb & IF_ARB_TRANSMIT) { 386 frame->can_id |= CAN_RTR_FLAG; 387 } else { 388 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 389 390 if (priv->type == BOSCH_D_CAN) { 391 for (i = 0; i < frame->len; i += 4, dreg += 2) { 392 data = priv->read_reg32(priv, dreg); 393 frame->data[i] = data; 394 frame->data[i + 1] = data >> 8; 395 frame->data[i + 2] = data >> 16; 396 frame->data[i + 3] = data >> 24; 397 } 398 } else { 399 for (i = 0; i < frame->len; i += 2, dreg++) { 400 data = priv->read_reg(priv, dreg); 401 frame->data[i] = data; 402 frame->data[i + 1] = data >> 8; 403 } 404 } 405 406 stats->rx_bytes += frame->len; 407 } 408 stats->rx_packets++; 409 410 netif_receive_skb(skb); 411 return 0; 412} 413 414static void c_can_setup_receive_object(struct net_device *dev, int iface, 415 u32 obj, u32 mask, u32 id, u32 mcont) 416{ 417 struct c_can_priv *priv = netdev_priv(dev); 418 419 mask |= BIT(29); 420 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 421 422 id |= IF_ARB_MSGVAL; 423 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); 424 425 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 426 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 427} 428 429static bool c_can_tx_busy(const struct c_can_priv *priv, 430 const struct c_can_tx_ring *tx_ring) 431{ 432 if (c_can_get_tx_free(priv, tx_ring) > 0) 433 return false; 434 435 netif_stop_queue(priv->dev); 436 437 /* Memory barrier before checking tx_free (head and tail) */ 438 smp_mb(); 439 440 if (c_can_get_tx_free(priv, tx_ring) == 0) { 441 netdev_dbg(priv->dev, 442 "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n", 443 tx_ring->head, tx_ring->tail, 444 tx_ring->head - tx_ring->tail); 445 return true; 446 } 447 448 netif_start_queue(priv->dev); 449 return false; 450} 451 452static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 453 struct net_device *dev) 454{ 455 struct can_frame *frame = (struct can_frame *)skb->data; 456 struct c_can_priv *priv = netdev_priv(dev); 457 struct c_can_tx_ring *tx_ring = &priv->tx; 458 u32 idx, obj, cmd = IF_COMM_TX; 459 460 if (can_dev_dropped_skb(dev, skb)) 461 return NETDEV_TX_OK; 462 463 if (c_can_tx_busy(priv, tx_ring)) 464 return NETDEV_TX_BUSY; 465 466 idx = c_can_get_tx_head(tx_ring); 467 tx_ring->head++; 468 if (c_can_get_tx_free(priv, tx_ring) == 0) 469 netif_stop_queue(dev); 470 471 if (idx < c_can_get_tx_tail(tx_ring)) 472 cmd &= ~IF_COMM_TXRQST; /* Cache the message */ 473 474 /* Store the message in the interface so we can call 475 * can_put_echo_skb(). We must do this before we enable 476 * transmit as we might race against do_tx(). 477 */ 478 c_can_setup_tx_object(dev, IF_TX, frame, idx); 479 can_put_echo_skb(skb, dev, idx, 0); 480 obj = idx + priv->msg_obj_tx_first; 481 c_can_object_put(dev, IF_TX, obj, cmd); 482 483 return NETDEV_TX_OK; 484} 485 486static int c_can_wait_for_ctrl_init(struct net_device *dev, 487 struct c_can_priv *priv, u32 init) 488{ 489 int retry = 0; 490 491 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 492 udelay(10); 493 if (retry++ > 1000) { 494 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 495 return -EIO; 496 } 497 } 498 return 0; 499} 500 501static int c_can_set_bittiming(struct net_device *dev) 502{ 503 unsigned int reg_btr, reg_brpe, ctrl_save; 504 u8 brp, brpe, sjw, tseg1, tseg2; 505 u32 ten_bit_brp; 506 struct c_can_priv *priv = netdev_priv(dev); 507 const struct can_bittiming *bt = &priv->can.bittiming; 508 int res; 509 510 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 511 ten_bit_brp = bt->brp - 1; 512 brp = ten_bit_brp & BTR_BRP_MASK; 513 brpe = ten_bit_brp >> 6; 514 515 sjw = bt->sjw - 1; 516 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 517 tseg2 = bt->phase_seg2 - 1; 518 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 519 (tseg2 << BTR_TSEG2_SHIFT); 520 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 521 522 netdev_info(dev, 523 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 524 525 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 526 ctrl_save &= ~CONTROL_INIT; 527 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 528 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 529 if (res) 530 return res; 531 532 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 533 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 534 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 535 536 return c_can_wait_for_ctrl_init(dev, priv, 0); 537} 538 539/* Configure C_CAN message objects for Tx and Rx purposes: 540 * C_CAN provides a total of 32 message objects that can be configured 541 * either for Tx or Rx purposes. Here the first 16 message objects are used as 542 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 543 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 544 * See user guide document for further details on configuring message 545 * objects. 546 */ 547static void c_can_configure_msg_objects(struct net_device *dev) 548{ 549 struct c_can_priv *priv = netdev_priv(dev); 550 int i; 551 552 /* first invalidate all message objects */ 553 for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++) 554 c_can_inval_msg_object(dev, IF_NAPI, i); 555 556 /* setup receive message objects */ 557 for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++) 558 c_can_setup_receive_object(dev, IF_NAPI, i, 0, 0, IF_MCONT_RCV); 559 560 c_can_setup_receive_object(dev, IF_NAPI, priv->msg_obj_rx_last, 0, 0, 561 IF_MCONT_RCV_EOB); 562} 563 564static int c_can_software_reset(struct net_device *dev) 565{ 566 struct c_can_priv *priv = netdev_priv(dev); 567 int retry = 0; 568 569 if (priv->type != BOSCH_D_CAN) 570 return 0; 571 572 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT); 573 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { 574 msleep(20); 575 if (retry++ > 100) { 576 netdev_err(dev, "CCTRL: software reset failed\n"); 577 return -EIO; 578 } 579 } 580 581 return 0; 582} 583 584/* Configure C_CAN chip: 585 * - enable/disable auto-retransmission 586 * - set operating mode 587 * - configure message objects 588 */ 589static int c_can_chip_config(struct net_device *dev) 590{ 591 struct c_can_priv *priv = netdev_priv(dev); 592 struct c_can_tx_ring *tx_ring = &priv->tx; 593 int err; 594 595 err = c_can_software_reset(dev); 596 if (err) 597 return err; 598 599 /* enable automatic retransmission */ 600 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 601 602 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 603 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 604 /* loopback + silent mode : useful for hot self-test */ 605 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 606 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 607 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 608 /* loopback mode : useful for self-test function */ 609 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 610 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 611 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 612 /* silent mode : bus-monitoring mode */ 613 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 614 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 615 } 616 617 /* configure message objects */ 618 c_can_configure_msg_objects(dev); 619 620 /* set a `lec` value so that we can check for updates later */ 621 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 622 623 /* Clear all internal status */ 624 tx_ring->head = 0; 625 tx_ring->tail = 0; 626 priv->tx_dir = 0; 627 628 /* set bittiming params */ 629 return c_can_set_bittiming(dev); 630} 631 632static int c_can_start(struct net_device *dev) 633{ 634 struct c_can_priv *priv = netdev_priv(dev); 635 int err; 636 struct pinctrl *p; 637 638 /* basic c_can configuration */ 639 err = c_can_chip_config(dev); 640 if (err) 641 return err; 642 643 /* Setup the command for new messages */ 644 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 645 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 646 647 priv->can.state = CAN_STATE_ERROR_ACTIVE; 648 649 /* Attempt to use "active" if available else use "default" */ 650 p = pinctrl_get_select(priv->device, "active"); 651 if (!IS_ERR(p)) 652 pinctrl_put(p); 653 else 654 pinctrl_pm_select_default_state(priv->device); 655 656 return 0; 657} 658 659static void c_can_stop(struct net_device *dev) 660{ 661 struct c_can_priv *priv = netdev_priv(dev); 662 663 c_can_irq_control(priv, false); 664 665 /* put ctrl to init on stop to end ongoing transmission */ 666 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); 667 668 /* deactivate pins */ 669 pinctrl_pm_select_sleep_state(dev->dev.parent); 670 priv->can.state = CAN_STATE_STOPPED; 671} 672 673static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 674{ 675 struct c_can_priv *priv = netdev_priv(dev); 676 int err; 677 678 switch (mode) { 679 case CAN_MODE_START: 680 err = c_can_start(dev); 681 if (err) 682 return err; 683 netif_wake_queue(dev); 684 c_can_irq_control(priv, true); 685 break; 686 default: 687 return -EOPNOTSUPP; 688 } 689 690 return 0; 691} 692 693static int __c_can_get_berr_counter(const struct net_device *dev, 694 struct can_berr_counter *bec) 695{ 696 unsigned int reg_err_counter; 697 struct c_can_priv *priv = netdev_priv(dev); 698 699 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 700 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 701 ERR_CNT_REC_SHIFT; 702 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 703 704 return 0; 705} 706 707static int c_can_get_berr_counter(const struct net_device *dev, 708 struct can_berr_counter *bec) 709{ 710 struct c_can_priv *priv = netdev_priv(dev); 711 int err; 712 713 c_can_pm_runtime_get_sync(priv); 714 err = __c_can_get_berr_counter(dev, bec); 715 c_can_pm_runtime_put_sync(priv); 716 717 return err; 718} 719 720static void c_can_do_tx(struct net_device *dev) 721{ 722 struct c_can_priv *priv = netdev_priv(dev); 723 struct c_can_tx_ring *tx_ring = &priv->tx; 724 struct net_device_stats *stats = &dev->stats; 725 u32 idx, obj, pkts = 0, bytes = 0, pend; 726 u8 tail; 727 728 if (priv->msg_obj_tx_last > 32) 729 pend = priv->read_reg32(priv, C_CAN_INTPND3_REG); 730 else 731 pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 732 733 while ((idx = ffs(pend))) { 734 idx--; 735 pend &= ~BIT(idx); 736 obj = idx + priv->msg_obj_tx_first; 737 738 /* We use IF_NAPI interface instead of IF_TX because we 739 * are called from c_can_poll(), which runs inside 740 * NAPI. We are not transmitting. 741 */ 742 c_can_inval_tx_object(dev, IF_NAPI, obj); 743 bytes += can_get_echo_skb(dev, idx, NULL); 744 pkts++; 745 } 746 747 if (!pkts) 748 return; 749 750 tx_ring->tail += pkts; 751 if (c_can_get_tx_free(priv, tx_ring)) { 752 /* Make sure that anybody stopping the queue after 753 * this sees the new tx_ring->tail. 754 */ 755 smp_mb(); 756 netif_wake_queue(priv->dev); 757 } 758 759 stats->tx_bytes += bytes; 760 stats->tx_packets += pkts; 761 762 tail = c_can_get_tx_tail(tx_ring); 763 if (priv->type == BOSCH_D_CAN && tail == 0) { 764 u8 head = c_can_get_tx_head(tx_ring); 765 766 /* Start transmission for all cached messages */ 767 for (idx = tail; idx < head; idx++) { 768 obj = idx + priv->msg_obj_tx_first; 769 c_can_object_put(dev, IF_NAPI, obj, IF_COMM_TXRQST); 770 } 771 } 772} 773 774/* If we have a gap in the pending bits, that means we either 775 * raced with the hardware or failed to readout all upper 776 * objects in the last run due to quota limit. 777 */ 778static u32 c_can_adjust_pending(u32 pend, u32 rx_mask) 779{ 780 u32 weight, lasts; 781 782 if (pend == rx_mask) 783 return pend; 784 785 /* If the last set bit is larger than the number of pending 786 * bits we have a gap. 787 */ 788 weight = hweight32(pend); 789 lasts = fls(pend); 790 791 /* If the bits are linear, nothing to do */ 792 if (lasts == weight) 793 return pend; 794 795 /* Find the first set bit after the gap. We walk backwards 796 * from the last set bit. 797 */ 798 for (lasts--; pend & BIT(lasts - 1); lasts--) 799 ; 800 801 return pend & ~GENMASK(lasts - 1, 0); 802} 803 804static inline void c_can_rx_object_get(struct net_device *dev, 805 struct c_can_priv *priv, u32 obj) 806{ 807 c_can_object_get(dev, IF_NAPI, obj, priv->comm_rcv_high); 808} 809 810static inline void c_can_rx_finalize(struct net_device *dev, 811 struct c_can_priv *priv, u32 obj) 812{ 813 if (priv->type != BOSCH_D_CAN) 814 c_can_object_get(dev, IF_NAPI, obj, IF_COMM_CLR_NEWDAT); 815} 816 817static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 818 u32 pend, int quota) 819{ 820 u32 pkts = 0, ctrl, obj; 821 822 while ((obj = ffs(pend)) && quota > 0) { 823 pend &= ~BIT(obj - 1); 824 825 c_can_rx_object_get(dev, priv, obj); 826 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_NAPI)); 827 828 if (ctrl & IF_MCONT_MSGLST) { 829 int n; 830 831 n = c_can_handle_lost_msg_obj(dev, IF_NAPI, obj, ctrl); 832 833 pkts += n; 834 quota -= n; 835 continue; 836 } 837 838 /* This really should not happen, but this covers some 839 * odd HW behaviour. Do not remove that unless you 840 * want to brick your machine. 841 */ 842 if (!(ctrl & IF_MCONT_NEWDAT)) 843 continue; 844 845 /* read the data from the message object */ 846 c_can_read_msg_object(dev, IF_NAPI, ctrl); 847 848 c_can_rx_finalize(dev, priv, obj); 849 850 pkts++; 851 quota--; 852 } 853 854 return pkts; 855} 856 857static inline u32 c_can_get_pending(struct c_can_priv *priv) 858{ 859 u32 pend; 860 861 if (priv->msg_obj_rx_last > 16) 862 pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG); 863 else 864 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 865 866 return pend; 867} 868 869/* theory of operation: 870 * 871 * c_can core saves a received CAN message into the first free message 872 * object it finds free (starting with the lowest). Bits NEWDAT and 873 * INTPND are set for this message object indicating that a new message 874 * has arrived. 875 * 876 * We clear the newdat bit right away. 877 * 878 * This can result in packet reordering when the readout is slow. 879 */ 880static int c_can_do_rx_poll(struct net_device *dev, int quota) 881{ 882 struct c_can_priv *priv = netdev_priv(dev); 883 u32 pkts = 0, pend = 0, toread, n; 884 885 while (quota > 0) { 886 if (!pend) { 887 pend = c_can_get_pending(priv); 888 if (!pend) 889 break; 890 /* If the pending field has a gap, handle the 891 * bits above the gap first. 892 */ 893 toread = c_can_adjust_pending(pend, 894 priv->msg_obj_rx_mask); 895 } else { 896 toread = pend; 897 } 898 /* Remove the bits from pend */ 899 pend &= ~toread; 900 /* Read the objects */ 901 n = c_can_read_objects(dev, priv, toread, quota); 902 pkts += n; 903 quota -= n; 904 } 905 906 return pkts; 907} 908 909static int c_can_handle_state_change(struct net_device *dev, 910 enum c_can_bus_error_types error_type) 911{ 912 unsigned int reg_err_counter; 913 unsigned int rx_err_passive; 914 struct c_can_priv *priv = netdev_priv(dev); 915 struct can_frame *cf; 916 struct sk_buff *skb; 917 struct can_berr_counter bec; 918 919 switch (error_type) { 920 case C_CAN_NO_ERROR: 921 priv->can.state = CAN_STATE_ERROR_ACTIVE; 922 break; 923 case C_CAN_ERROR_WARNING: 924 /* error warning state */ 925 priv->can.can_stats.error_warning++; 926 priv->can.state = CAN_STATE_ERROR_WARNING; 927 break; 928 case C_CAN_ERROR_PASSIVE: 929 /* error passive state */ 930 priv->can.can_stats.error_passive++; 931 priv->can.state = CAN_STATE_ERROR_PASSIVE; 932 break; 933 case C_CAN_BUS_OFF: 934 /* bus-off state */ 935 priv->can.state = CAN_STATE_BUS_OFF; 936 priv->can.can_stats.bus_off++; 937 break; 938 default: 939 break; 940 } 941 942 /* propagate the error condition to the CAN stack */ 943 skb = alloc_can_err_skb(dev, &cf); 944 if (unlikely(!skb)) 945 return 0; 946 947 __c_can_get_berr_counter(dev, &bec); 948 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 949 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 950 ERR_CNT_RP_SHIFT; 951 952 switch (error_type) { 953 case C_CAN_NO_ERROR: 954 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 955 cf->data[1] = CAN_ERR_CRTL_ACTIVE; 956 cf->data[6] = bec.txerr; 957 cf->data[7] = bec.rxerr; 958 break; 959 case C_CAN_ERROR_WARNING: 960 /* error warning state */ 961 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 962 cf->data[1] = (bec.txerr > bec.rxerr) ? 963 CAN_ERR_CRTL_TX_WARNING : 964 CAN_ERR_CRTL_RX_WARNING; 965 cf->data[6] = bec.txerr; 966 cf->data[7] = bec.rxerr; 967 968 break; 969 case C_CAN_ERROR_PASSIVE: 970 /* error passive state */ 971 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 972 if (rx_err_passive) 973 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 974 if (bec.txerr > 127) 975 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 976 977 cf->data[6] = bec.txerr; 978 cf->data[7] = bec.rxerr; 979 break; 980 case C_CAN_BUS_OFF: 981 /* bus-off state */ 982 cf->can_id |= CAN_ERR_BUSOFF; 983 can_bus_off(dev); 984 break; 985 default: 986 break; 987 } 988 989 netif_receive_skb(skb); 990 991 return 1; 992} 993 994static int c_can_handle_bus_err(struct net_device *dev, 995 enum c_can_lec_type lec_type) 996{ 997 struct c_can_priv *priv = netdev_priv(dev); 998 struct net_device_stats *stats = &dev->stats; 999 struct can_frame *cf; 1000 struct sk_buff *skb; 1001 1002 /* early exit if no lec update or no error. 1003 * no lec update means that no CAN bus event has been detected 1004 * since CPU wrote 0x7 value to status reg. 1005 */ 1006 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 1007 return 0; 1008 1009 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1010 return 0; 1011 1012 /* common for all type of bus errors */ 1013 priv->can.can_stats.bus_error++; 1014 stats->rx_errors++; 1015 1016 /* propagate the error condition to the CAN stack */ 1017 skb = alloc_can_err_skb(dev, &cf); 1018 if (unlikely(!skb)) 1019 return 0; 1020 1021 /* check for 'last error code' which tells us the 1022 * type of the last error to occur on the CAN bus 1023 */ 1024 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1025 1026 switch (lec_type) { 1027 case LEC_STUFF_ERROR: 1028 netdev_dbg(dev, "stuff error\n"); 1029 cf->data[2] |= CAN_ERR_PROT_STUFF; 1030 break; 1031 case LEC_FORM_ERROR: 1032 netdev_dbg(dev, "form error\n"); 1033 cf->data[2] |= CAN_ERR_PROT_FORM; 1034 break; 1035 case LEC_ACK_ERROR: 1036 netdev_dbg(dev, "ack error\n"); 1037 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 1038 break; 1039 case LEC_BIT1_ERROR: 1040 netdev_dbg(dev, "bit1 error\n"); 1041 cf->data[2] |= CAN_ERR_PROT_BIT1; 1042 break; 1043 case LEC_BIT0_ERROR: 1044 netdev_dbg(dev, "bit0 error\n"); 1045 cf->data[2] |= CAN_ERR_PROT_BIT0; 1046 break; 1047 case LEC_CRC_ERROR: 1048 netdev_dbg(dev, "CRC error\n"); 1049 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 netif_receive_skb(skb); 1056 return 1; 1057} 1058 1059static int c_can_poll(struct napi_struct *napi, int quota) 1060{ 1061 struct net_device *dev = napi->dev; 1062 struct c_can_priv *priv = netdev_priv(dev); 1063 u16 curr, last = priv->last_status; 1064 int work_done = 0; 1065 1066 /* Only read the status register if a status interrupt was pending */ 1067 if (atomic_xchg(&priv->sie_pending, 0)) { 1068 priv->last_status = priv->read_reg(priv, C_CAN_STS_REG); 1069 curr = priv->last_status; 1070 /* Ack status on C_CAN. D_CAN is self clearing */ 1071 if (priv->type != BOSCH_D_CAN) 1072 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1073 } else { 1074 /* no change detected ... */ 1075 curr = last; 1076 } 1077 1078 /* handle state changes */ 1079 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1080 netdev_dbg(dev, "entered error warning state\n"); 1081 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1082 } 1083 1084 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1085 netdev_dbg(dev, "entered error passive state\n"); 1086 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1087 } 1088 1089 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1090 netdev_dbg(dev, "entered bus off state\n"); 1091 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1092 goto end; 1093 } 1094 1095 /* handle bus recovery events */ 1096 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1097 netdev_dbg(dev, "left bus off state\n"); 1098 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1099 } 1100 1101 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1102 netdev_dbg(dev, "left error passive state\n"); 1103 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1104 } 1105 1106 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) { 1107 netdev_dbg(dev, "left error warning state\n"); 1108 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR); 1109 } 1110 1111 /* handle lec errors on the bus */ 1112 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1113 1114 /* Handle Tx/Rx events. We do this unconditionally */ 1115 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1116 c_can_do_tx(dev); 1117 1118end: 1119 if (work_done < quota) { 1120 napi_complete_done(napi, work_done); 1121 /* enable all IRQs if we are not in bus off state */ 1122 if (priv->can.state != CAN_STATE_BUS_OFF) 1123 c_can_irq_control(priv, true); 1124 } 1125 1126 return work_done; 1127} 1128 1129static irqreturn_t c_can_isr(int irq, void *dev_id) 1130{ 1131 struct net_device *dev = (struct net_device *)dev_id; 1132 struct c_can_priv *priv = netdev_priv(dev); 1133 int reg_int; 1134 1135 reg_int = priv->read_reg(priv, C_CAN_INT_REG); 1136 if (!reg_int) 1137 return IRQ_NONE; 1138 1139 /* save for later use */ 1140 if (reg_int & INT_STS_PENDING) 1141 atomic_set(&priv->sie_pending, 1); 1142 1143 /* disable all interrupts and schedule the NAPI */ 1144 c_can_irq_control(priv, false); 1145 napi_schedule(&priv->napi); 1146 1147 return IRQ_HANDLED; 1148} 1149 1150static int c_can_open(struct net_device *dev) 1151{ 1152 int err; 1153 struct c_can_priv *priv = netdev_priv(dev); 1154 1155 c_can_pm_runtime_get_sync(priv); 1156 c_can_reset_ram(priv, true); 1157 1158 /* open the can device */ 1159 err = open_candev(dev); 1160 if (err) { 1161 netdev_err(dev, "failed to open can device\n"); 1162 goto exit_open_fail; 1163 } 1164 1165 /* register interrupt handler */ 1166 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1167 dev); 1168 if (err < 0) { 1169 netdev_err(dev, "failed to request interrupt\n"); 1170 goto exit_irq_fail; 1171 } 1172 1173 /* start the c_can controller */ 1174 err = c_can_start(dev); 1175 if (err) 1176 goto exit_start_fail; 1177 1178 napi_enable(&priv->napi); 1179 /* enable status change, error and module interrupts */ 1180 c_can_irq_control(priv, true); 1181 netif_start_queue(dev); 1182 1183 return 0; 1184 1185exit_start_fail: 1186 free_irq(dev->irq, dev); 1187exit_irq_fail: 1188 close_candev(dev); 1189exit_open_fail: 1190 c_can_reset_ram(priv, false); 1191 c_can_pm_runtime_put_sync(priv); 1192 return err; 1193} 1194 1195static int c_can_close(struct net_device *dev) 1196{ 1197 struct c_can_priv *priv = netdev_priv(dev); 1198 1199 netif_stop_queue(dev); 1200 napi_disable(&priv->napi); 1201 c_can_stop(dev); 1202 free_irq(dev->irq, dev); 1203 close_candev(dev); 1204 1205 c_can_reset_ram(priv, false); 1206 c_can_pm_runtime_put_sync(priv); 1207 1208 return 0; 1209} 1210 1211struct net_device *alloc_c_can_dev(int msg_obj_num) 1212{ 1213 struct net_device *dev; 1214 struct c_can_priv *priv; 1215 int msg_obj_tx_num = msg_obj_num / 2; 1216 1217 dev = alloc_candev(sizeof(*priv), msg_obj_tx_num); 1218 if (!dev) 1219 return NULL; 1220 1221 priv = netdev_priv(dev); 1222 priv->msg_obj_num = msg_obj_num; 1223 priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num; 1224 priv->msg_obj_rx_first = 1; 1225 priv->msg_obj_rx_last = 1226 priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1; 1227 priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0); 1228 1229 priv->msg_obj_tx_num = msg_obj_tx_num; 1230 priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1; 1231 priv->msg_obj_tx_last = 1232 priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1; 1233 1234 priv->tx.head = 0; 1235 priv->tx.tail = 0; 1236 priv->tx.obj_num = msg_obj_tx_num; 1237 1238 netif_napi_add_weight(dev, &priv->napi, c_can_poll, 1239 priv->msg_obj_rx_num); 1240 1241 priv->dev = dev; 1242 priv->can.bittiming_const = &c_can_bittiming_const; 1243 priv->can.do_set_mode = c_can_set_mode; 1244 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1245 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1246 CAN_CTRLMODE_LISTENONLY | 1247 CAN_CTRLMODE_BERR_REPORTING; 1248 1249 return dev; 1250} 1251EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1252 1253#ifdef CONFIG_PM 1254int c_can_power_down(struct net_device *dev) 1255{ 1256 u32 val; 1257 unsigned long time_out; 1258 struct c_can_priv *priv = netdev_priv(dev); 1259 1260 if (!(dev->flags & IFF_UP)) 1261 return 0; 1262 1263 WARN_ON(priv->type != BOSCH_D_CAN); 1264 1265 /* set PDR value so the device goes to power down mode */ 1266 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1267 val |= CONTROL_EX_PDR; 1268 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1269 1270 /* Wait for the PDA bit to get set */ 1271 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1272 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1273 time_after(time_out, jiffies)) 1274 cpu_relax(); 1275 1276 if (time_after(jiffies, time_out)) 1277 return -ETIMEDOUT; 1278 1279 c_can_stop(dev); 1280 1281 c_can_reset_ram(priv, false); 1282 c_can_pm_runtime_put_sync(priv); 1283 1284 return 0; 1285} 1286EXPORT_SYMBOL_GPL(c_can_power_down); 1287 1288int c_can_power_up(struct net_device *dev) 1289{ 1290 u32 val; 1291 unsigned long time_out; 1292 struct c_can_priv *priv = netdev_priv(dev); 1293 int ret; 1294 1295 if (!(dev->flags & IFF_UP)) 1296 return 0; 1297 1298 WARN_ON(priv->type != BOSCH_D_CAN); 1299 1300 c_can_pm_runtime_get_sync(priv); 1301 c_can_reset_ram(priv, true); 1302 1303 /* Clear PDR and INIT bits */ 1304 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1305 val &= ~CONTROL_EX_PDR; 1306 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1307 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1308 val &= ~CONTROL_INIT; 1309 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1310 1311 /* Wait for the PDA bit to get clear */ 1312 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1313 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1314 time_after(time_out, jiffies)) 1315 cpu_relax(); 1316 1317 if (time_after(jiffies, time_out)) { 1318 ret = -ETIMEDOUT; 1319 goto err_out; 1320 } 1321 1322 ret = c_can_start(dev); 1323 if (ret) 1324 goto err_out; 1325 1326 c_can_irq_control(priv, true); 1327 1328 return 0; 1329 1330err_out: 1331 c_can_reset_ram(priv, false); 1332 c_can_pm_runtime_put_sync(priv); 1333 1334 return ret; 1335} 1336EXPORT_SYMBOL_GPL(c_can_power_up); 1337#endif 1338 1339void free_c_can_dev(struct net_device *dev) 1340{ 1341 struct c_can_priv *priv = netdev_priv(dev); 1342 1343 netif_napi_del(&priv->napi); 1344 free_candev(dev); 1345} 1346EXPORT_SYMBOL_GPL(free_c_can_dev); 1347 1348static const struct net_device_ops c_can_netdev_ops = { 1349 .ndo_open = c_can_open, 1350 .ndo_stop = c_can_close, 1351 .ndo_start_xmit = c_can_start_xmit, 1352 .ndo_change_mtu = can_change_mtu, 1353}; 1354 1355int register_c_can_dev(struct net_device *dev) 1356{ 1357 /* Deactivate pins to prevent DRA7 DCAN IP from being 1358 * stuck in transition when module is disabled. 1359 * Pins are activated in c_can_start() and deactivated 1360 * in c_can_stop() 1361 */ 1362 pinctrl_pm_select_sleep_state(dev->dev.parent); 1363 1364 dev->flags |= IFF_ECHO; /* we support local echo */ 1365 dev->netdev_ops = &c_can_netdev_ops; 1366 dev->ethtool_ops = &c_can_ethtool_ops; 1367 1368 return register_candev(dev); 1369} 1370EXPORT_SYMBOL_GPL(register_c_can_dev); 1371 1372void unregister_c_can_dev(struct net_device *dev) 1373{ 1374 unregister_candev(dev); 1375} 1376EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1377 1378MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1379MODULE_LICENSE("GPL v2"); 1380MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1381