1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Marvell MMC/SD/SDIO driver 4 * 5 * Authors: Maen Suleiman, Nicolas Pitre 6 * Copyright (C) 2008-2009 Marvell Ltd. 7 */ 8 9#include <linux/module.h> 10#include <linux/init.h> 11#include <linux/io.h> 12#include <linux/platform_device.h> 13#include <linux/mbus.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/dma-mapping.h> 17#include <linux/scatterlist.h> 18#include <linux/irq.h> 19#include <linux/clk.h> 20#include <linux/of_irq.h> 21#include <linux/mmc/host.h> 22#include <linux/mmc/slot-gpio.h> 23 24#include <linux/sizes.h> 25#include <asm/unaligned.h> 26 27#include "mvsdio.h" 28 29#define DRIVER_NAME "mvsdio" 30 31static int maxfreq; 32static int nodma; 33 34struct mvsd_host { 35 void __iomem *base; 36 struct mmc_request *mrq; 37 spinlock_t lock; 38 unsigned int xfer_mode; 39 unsigned int intr_en; 40 unsigned int ctrl; 41 bool use_pio; 42 struct sg_mapping_iter sg_miter; 43 unsigned int pio_size; 44 unsigned int sg_frags; 45 unsigned int ns_per_clk; 46 unsigned int clock; 47 unsigned int base_clock; 48 struct timer_list timer; 49 struct mmc_host *mmc; 50 struct device *dev; 51 struct clk *clk; 52}; 53 54#define mvsd_write(offs, val) writel(val, iobase + (offs)) 55#define mvsd_read(offs) readl(iobase + (offs)) 56 57static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) 58{ 59 void __iomem *iobase = host->base; 60 unsigned int tmout; 61 int tmout_index; 62 63 /* 64 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE 65 * register is sometimes not set before a while when some 66 * "unusual" data block sizes are used (such as with the SWITCH 67 * command), even despite the fact that the XFER_DONE interrupt 68 * was raised. And if another data transfer starts before 69 * this bit comes to good sense (which eventually happens by 70 * itself) then the new transfer simply fails with a timeout. 71 */ 72 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { 73 unsigned long t = jiffies + HZ; 74 unsigned int hw_state, count = 0; 75 do { 76 hw_state = mvsd_read(MVSD_HW_STATE); 77 if (time_after(jiffies, t)) { 78 dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); 79 break; 80 } 81 count++; 82 } while (!(hw_state & (1 << 13))); 83 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " 84 "(hw=0x%04x, count=%d, jiffies=%ld)\n", 85 hw_state, count, jiffies - (t - HZ)); 86 } 87 88 /* If timeout=0 then maximum timeout index is used. */ 89 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); 90 tmout += data->timeout_clks; 91 tmout_index = fls(tmout - 1) - 12; 92 if (tmout_index < 0) 93 tmout_index = 0; 94 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) 95 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; 96 97 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", 98 (data->flags & MMC_DATA_READ) ? "read" : "write", 99 (u32)sg_virt(data->sg), data->blocks, data->blksz, 100 tmout, tmout_index); 101 102 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; 103 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); 104 mvsd_write(MVSD_HOST_CTRL, host->ctrl); 105 mvsd_write(MVSD_BLK_COUNT, data->blocks); 106 mvsd_write(MVSD_BLK_SIZE, data->blksz); 107 108 if (nodma || (data->blksz | data->sg->offset) & 3 || 109 ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) { 110 /* 111 * We cannot do DMA on a buffer which offset or size 112 * is not aligned on a 4-byte boundary. 113 * 114 * It also appears the host to card DMA can corrupt 115 * data when the buffer is not aligned on a 64 byte 116 * boundary. 117 */ 118 unsigned int miter_flags = SG_MITER_ATOMIC; /* Used from IRQ */ 119 120 if (data->flags & MMC_DATA_READ) 121 miter_flags |= SG_MITER_TO_SG; 122 else 123 miter_flags |= SG_MITER_FROM_SG; 124 125 host->pio_size = data->blocks * data->blksz; 126 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, miter_flags); 127 if (!nodma) 128 dev_dbg(host->dev, "fallback to PIO for data\n"); 129 host->use_pio = true; 130 return 1; 131 } else { 132 dma_addr_t phys_addr; 133 134 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), 135 data->sg, data->sg_len, 136 mmc_get_dma_dir(data)); 137 phys_addr = sg_dma_address(data->sg); 138 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); 139 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); 140 host->use_pio = false; 141 return 0; 142 } 143} 144 145static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) 146{ 147 struct mvsd_host *host = mmc_priv(mmc); 148 void __iomem *iobase = host->base; 149 struct mmc_command *cmd = mrq->cmd; 150 u32 cmdreg = 0, xfer = 0, intr = 0; 151 unsigned long flags; 152 unsigned int timeout; 153 154 BUG_ON(host->mrq != NULL); 155 host->mrq = mrq; 156 157 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", 158 cmd->opcode, mvsd_read(MVSD_HW_STATE)); 159 160 cmdreg = MVSD_CMD_INDEX(cmd->opcode); 161 162 if (cmd->flags & MMC_RSP_BUSY) 163 cmdreg |= MVSD_CMD_RSP_48BUSY; 164 else if (cmd->flags & MMC_RSP_136) 165 cmdreg |= MVSD_CMD_RSP_136; 166 else if (cmd->flags & MMC_RSP_PRESENT) 167 cmdreg |= MVSD_CMD_RSP_48; 168 else 169 cmdreg |= MVSD_CMD_RSP_NONE; 170 171 if (cmd->flags & MMC_RSP_CRC) 172 cmdreg |= MVSD_CMD_CHECK_CMDCRC; 173 174 if (cmd->flags & MMC_RSP_OPCODE) 175 cmdreg |= MVSD_CMD_INDX_CHECK; 176 177 if (cmd->flags & MMC_RSP_PRESENT) { 178 cmdreg |= MVSD_UNEXPECTED_RESP; 179 intr |= MVSD_NOR_UNEXP_RSP; 180 } 181 182 if (mrq->data) { 183 struct mmc_data *data = mrq->data; 184 int pio; 185 186 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; 187 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; 188 if (data->flags & MMC_DATA_READ) 189 xfer |= MVSD_XFER_MODE_TO_HOST; 190 191 pio = mvsd_setup_data(host, data); 192 if (pio) { 193 xfer |= MVSD_XFER_MODE_PIO; 194 /* PIO section of mvsd_irq has comments on those bits */ 195 if (data->flags & MMC_DATA_WRITE) 196 intr |= MVSD_NOR_TX_AVAIL; 197 else if (host->pio_size > 32) 198 intr |= MVSD_NOR_RX_FIFO_8W; 199 else 200 intr |= MVSD_NOR_RX_READY; 201 } 202 203 if (data->stop) { 204 struct mmc_command *stop = data->stop; 205 u32 cmd12reg = 0; 206 207 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); 208 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); 209 210 if (stop->flags & MMC_RSP_BUSY) 211 cmd12reg |= MVSD_AUTOCMD12_BUSY; 212 if (stop->flags & MMC_RSP_OPCODE) 213 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; 214 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); 215 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); 216 217 xfer |= MVSD_XFER_MODE_AUTO_CMD12; 218 intr |= MVSD_NOR_AUTOCMD12_DONE; 219 } else { 220 intr |= MVSD_NOR_XFER_DONE; 221 } 222 } else { 223 intr |= MVSD_NOR_CMD_DONE; 224 } 225 226 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); 227 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); 228 229 spin_lock_irqsave(&host->lock, flags); 230 231 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; 232 host->xfer_mode |= xfer; 233 mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 234 235 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); 236 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 237 mvsd_write(MVSD_CMD, cmdreg); 238 239 host->intr_en &= MVSD_NOR_CARD_INT; 240 host->intr_en |= intr | MVSD_NOR_ERROR; 241 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 242 mvsd_write(MVSD_ERR_INTR_EN, 0xffff); 243 244 timeout = cmd->busy_timeout ? cmd->busy_timeout : 5000; 245 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout)); 246 247 spin_unlock_irqrestore(&host->lock, flags); 248} 249 250static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, 251 u32 err_status) 252{ 253 void __iomem *iobase = host->base; 254 255 if (cmd->flags & MMC_RSP_136) { 256 unsigned int response[8], i; 257 for (i = 0; i < 8; i++) 258 response[i] = mvsd_read(MVSD_RSP(i)); 259 cmd->resp[0] = ((response[0] & 0x03ff) << 22) | 260 ((response[1] & 0xffff) << 6) | 261 ((response[2] & 0xfc00) >> 10); 262 cmd->resp[1] = ((response[2] & 0x03ff) << 22) | 263 ((response[3] & 0xffff) << 6) | 264 ((response[4] & 0xfc00) >> 10); 265 cmd->resp[2] = ((response[4] & 0x03ff) << 22) | 266 ((response[5] & 0xffff) << 6) | 267 ((response[6] & 0xfc00) >> 10); 268 cmd->resp[3] = ((response[6] & 0x03ff) << 22) | 269 ((response[7] & 0x3fff) << 8); 270 } else if (cmd->flags & MMC_RSP_PRESENT) { 271 unsigned int response[3], i; 272 for (i = 0; i < 3; i++) 273 response[i] = mvsd_read(MVSD_RSP(i)); 274 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | 275 ((response[1] & 0xffff) << (14 - 8)) | 276 ((response[0] & 0x03ff) << (30 - 8)); 277 cmd->resp[1] = ((response[0] & 0xfc00) >> 10); 278 cmd->resp[2] = 0; 279 cmd->resp[3] = 0; 280 } 281 282 if (err_status & MVSD_ERR_CMD_TIMEOUT) { 283 cmd->error = -ETIMEDOUT; 284 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | 285 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { 286 cmd->error = -EILSEQ; 287 } 288 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | 289 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | 290 MVSD_ERR_CMD_STARTBIT); 291 292 return err_status; 293} 294 295static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, 296 u32 err_status) 297{ 298 void __iomem *iobase = host->base; 299 300 if (host->use_pio) { 301 sg_miter_stop(&host->sg_miter); 302 host->pio_size = 0; 303 } else { 304 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, 305 mmc_get_dma_dir(data)); 306 } 307 308 if (err_status & MVSD_ERR_DATA_TIMEOUT) 309 data->error = -ETIMEDOUT; 310 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) 311 data->error = -EILSEQ; 312 else if (err_status & MVSD_ERR_XFER_SIZE) 313 data->error = -EBADE; 314 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | 315 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); 316 317 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", 318 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); 319 data->bytes_xfered = 320 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; 321 /* We can't be sure about the last block when errors are detected */ 322 if (data->bytes_xfered && data->error) 323 data->bytes_xfered -= data->blksz; 324 325 /* Handle Auto cmd 12 response */ 326 if (data->stop) { 327 unsigned int response[3], i; 328 for (i = 0; i < 3; i++) 329 response[i] = mvsd_read(MVSD_AUTO_RSP(i)); 330 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | 331 ((response[1] & 0xffff) << (14 - 8)) | 332 ((response[0] & 0x03ff) << (30 - 8)); 333 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); 334 data->stop->resp[2] = 0; 335 data->stop->resp[3] = 0; 336 337 if (err_status & MVSD_ERR_AUTOCMD12) { 338 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); 339 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); 340 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) 341 data->stop->error = -ENOEXEC; 342 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) 343 data->stop->error = -ETIMEDOUT; 344 else if (err_cmd12) 345 data->stop->error = -EILSEQ; 346 err_status &= ~MVSD_ERR_AUTOCMD12; 347 } 348 } 349 350 return err_status; 351} 352 353static irqreturn_t mvsd_irq(int irq, void *dev) 354{ 355 struct mvsd_host *host = dev; 356 struct sg_mapping_iter *sgm = &host->sg_miter; 357 void __iomem *iobase = host->base; 358 u32 intr_status, intr_done_mask; 359 int irq_handled = 0; 360 u16 *p; 361 int s; 362 363 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 364 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", 365 intr_status, mvsd_read(MVSD_NOR_INTR_EN), 366 mvsd_read(MVSD_HW_STATE)); 367 368 /* 369 * It looks like, SDIO IP can issue one late, spurious irq 370 * although all irqs should be disabled. To work around this, 371 * bail out early, if we didn't expect any irqs to occur. 372 */ 373 if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) { 374 dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n", 375 mvsd_read(MVSD_NOR_INTR_STATUS), 376 mvsd_read(MVSD_NOR_INTR_EN), 377 mvsd_read(MVSD_ERR_INTR_STATUS), 378 mvsd_read(MVSD_ERR_INTR_EN)); 379 return IRQ_HANDLED; 380 } 381 382 spin_lock(&host->lock); 383 384 /* PIO handling, if needed. Messy business... */ 385 if (host->use_pio) { 386 /* 387 * As we set sgm->consumed this always gives a valid buffer 388 * position. 389 */ 390 if (!sg_miter_next(sgm)) { 391 /* This should not happen */ 392 dev_err(host->dev, "ran out of scatter segments\n"); 393 spin_unlock(&host->lock); 394 host->intr_en &= 395 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W | 396 MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); 397 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 398 return IRQ_HANDLED; 399 } 400 p = sgm->addr; 401 s = sgm->length; 402 if (s > host->pio_size) 403 s = host->pio_size; 404 } 405 406 if (host->use_pio && 407 (intr_status & host->intr_en & 408 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { 409 410 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { 411 readsw(iobase + MVSD_FIFO, p, 16); 412 p += 16; 413 s -= 32; 414 sgm->consumed += 32; 415 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 416 } 417 /* 418 * Normally we'd use < 32 here, but the RX_FIFO_8W bit 419 * doesn't appear to assert when there is exactly 32 bytes 420 * (8 words) left to fetch in a transfer. 421 */ 422 if (s <= 32) { 423 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { 424 put_unaligned(mvsd_read(MVSD_FIFO), p++); 425 put_unaligned(mvsd_read(MVSD_FIFO), p++); 426 s -= 4; 427 sgm->consumed += 4; 428 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 429 } 430 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { 431 u16 val[2] = {0, 0}; 432 val[0] = mvsd_read(MVSD_FIFO); 433 val[1] = mvsd_read(MVSD_FIFO); 434 memcpy(p, ((void *)&val) + 4 - s, s); 435 sgm->consumed += s; 436 s = 0; 437 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 438 } 439 /* PIO transfer done */ 440 host->pio_size -= sgm->consumed; 441 if (host->pio_size == 0) { 442 host->intr_en &= 443 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); 444 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 445 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { 446 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; 447 host->intr_en |= MVSD_NOR_RX_READY; 448 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 449 } 450 } 451 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", 452 s, intr_status, mvsd_read(MVSD_HW_STATE)); 453 irq_handled = 1; 454 } else if (host->use_pio && 455 (intr_status & host->intr_en & 456 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { 457 /* 458 * The TX_FIFO_8W bit is unreliable. When set, bursting 459 * 16 halfwords all at once in the FIFO drops data. Actually 460 * TX_AVAIL does go off after only one word is pushed even if 461 * TX_FIFO_8W remains set. 462 */ 463 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { 464 mvsd_write(MVSD_FIFO, get_unaligned(p++)); 465 mvsd_write(MVSD_FIFO, get_unaligned(p++)); 466 s -= 4; 467 sgm->consumed += 4; 468 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 469 } 470 if (s < 4) { 471 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { 472 u16 val[2] = {0, 0}; 473 memcpy(((void *)&val) + 4 - s, p, s); 474 mvsd_write(MVSD_FIFO, val[0]); 475 mvsd_write(MVSD_FIFO, val[1]); 476 sgm->consumed += s; 477 s = 0; 478 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 479 } 480 /* PIO transfer done */ 481 host->pio_size -= sgm->consumed; 482 if (host->pio_size == 0) { 483 host->intr_en &= 484 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); 485 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 486 } 487 } 488 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", 489 s, intr_status, mvsd_read(MVSD_HW_STATE)); 490 irq_handled = 1; 491 } 492 493 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); 494 495 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | 496 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; 497 if (intr_status & host->intr_en & ~intr_done_mask) { 498 struct mmc_request *mrq = host->mrq; 499 struct mmc_command *cmd = mrq->cmd; 500 u32 err_status = 0; 501 502 del_timer(&host->timer); 503 host->mrq = NULL; 504 505 host->intr_en &= MVSD_NOR_CARD_INT; 506 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 507 mvsd_write(MVSD_ERR_INTR_EN, 0); 508 509 spin_unlock(&host->lock); 510 511 if (intr_status & MVSD_NOR_UNEXP_RSP) { 512 cmd->error = -EPROTO; 513 } else if (intr_status & MVSD_NOR_ERROR) { 514 err_status = mvsd_read(MVSD_ERR_INTR_STATUS); 515 dev_dbg(host->dev, "err 0x%04x\n", err_status); 516 } 517 518 err_status = mvsd_finish_cmd(host, cmd, err_status); 519 if (mrq->data) 520 err_status = mvsd_finish_data(host, mrq->data, err_status); 521 if (err_status) { 522 dev_err(host->dev, "unhandled error status %#04x\n", 523 err_status); 524 cmd->error = -ENOMSG; 525 } 526 527 mmc_request_done(host->mmc, mrq); 528 irq_handled = 1; 529 } else 530 spin_unlock(&host->lock); 531 532 if (intr_status & MVSD_NOR_CARD_INT) { 533 mmc_signal_sdio_irq(host->mmc); 534 irq_handled = 1; 535 } 536 537 if (irq_handled) 538 return IRQ_HANDLED; 539 540 dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n", 541 intr_status, host->intr_en, host->pio_size); 542 return IRQ_NONE; 543} 544 545static void mvsd_timeout_timer(struct timer_list *t) 546{ 547 struct mvsd_host *host = from_timer(host, t, timer); 548 void __iomem *iobase = host->base; 549 struct mmc_request *mrq; 550 unsigned long flags; 551 552 spin_lock_irqsave(&host->lock, flags); 553 mrq = host->mrq; 554 if (mrq) { 555 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n"); 556 dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n", 557 mvsd_read(MVSD_HW_STATE), 558 mvsd_read(MVSD_NOR_INTR_STATUS), 559 mvsd_read(MVSD_NOR_INTR_EN)); 560 561 host->mrq = NULL; 562 563 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 564 565 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; 566 mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 567 568 host->intr_en &= MVSD_NOR_CARD_INT; 569 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 570 mvsd_write(MVSD_ERR_INTR_EN, 0); 571 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 572 573 mrq->cmd->error = -ETIMEDOUT; 574 mvsd_finish_cmd(host, mrq->cmd, 0); 575 if (mrq->data) { 576 mrq->data->error = -ETIMEDOUT; 577 mvsd_finish_data(host, mrq->data, 0); 578 } 579 } 580 spin_unlock_irqrestore(&host->lock, flags); 581 582 if (mrq) 583 mmc_request_done(host->mmc, mrq); 584} 585 586static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) 587{ 588 struct mvsd_host *host = mmc_priv(mmc); 589 void __iomem *iobase = host->base; 590 unsigned long flags; 591 592 spin_lock_irqsave(&host->lock, flags); 593 if (enable) { 594 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; 595 host->intr_en |= MVSD_NOR_CARD_INT; 596 } else { 597 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; 598 host->intr_en &= ~MVSD_NOR_CARD_INT; 599 } 600 mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 601 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 602 spin_unlock_irqrestore(&host->lock, flags); 603} 604 605static void mvsd_power_up(struct mvsd_host *host) 606{ 607 void __iomem *iobase = host->base; 608 dev_dbg(host->dev, "power up\n"); 609 mvsd_write(MVSD_NOR_INTR_EN, 0); 610 mvsd_write(MVSD_ERR_INTR_EN, 0); 611 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 612 mvsd_write(MVSD_XFER_MODE, 0); 613 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); 614 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); 615 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); 616 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 617} 618 619static void mvsd_power_down(struct mvsd_host *host) 620{ 621 void __iomem *iobase = host->base; 622 dev_dbg(host->dev, "power down\n"); 623 mvsd_write(MVSD_NOR_INTR_EN, 0); 624 mvsd_write(MVSD_ERR_INTR_EN, 0); 625 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 626 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); 627 mvsd_write(MVSD_NOR_STATUS_EN, 0); 628 mvsd_write(MVSD_ERR_STATUS_EN, 0); 629 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); 630 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 631} 632 633static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 634{ 635 struct mvsd_host *host = mmc_priv(mmc); 636 void __iomem *iobase = host->base; 637 u32 ctrl_reg = 0; 638 639 if (ios->power_mode == MMC_POWER_UP) 640 mvsd_power_up(host); 641 642 if (ios->clock == 0) { 643 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); 644 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); 645 host->clock = 0; 646 dev_dbg(host->dev, "clock off\n"); 647 } else if (ios->clock != host->clock) { 648 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; 649 if (m > MVSD_BASE_DIV_MAX) 650 m = MVSD_BASE_DIV_MAX; 651 mvsd_write(MVSD_CLK_DIV, m); 652 host->clock = ios->clock; 653 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); 654 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", 655 ios->clock, host->base_clock / (m+1), m); 656 } 657 658 /* default transfer mode */ 659 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; 660 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; 661 662 /* default to maximum timeout */ 663 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; 664 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; 665 666 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) 667 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; 668 669 if (ios->bus_width == MMC_BUS_WIDTH_4) 670 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; 671 672 /* 673 * The HI_SPEED_EN bit is causing trouble with many (but not all) 674 * high speed SD, SDHC and SDIO cards. Not enabling that bit 675 * makes all cards work. So let's just ignore that bit for now 676 * and revisit this issue if problems for not enabling this bit 677 * are ever reported. 678 */ 679#if 0 680 if (ios->timing == MMC_TIMING_MMC_HS || 681 ios->timing == MMC_TIMING_SD_HS) 682 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; 683#endif 684 685 host->ctrl = ctrl_reg; 686 mvsd_write(MVSD_HOST_CTRL, ctrl_reg); 687 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, 688 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? 689 "push-pull" : "open-drain", 690 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? 691 "4bit-width" : "1bit-width", 692 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? 693 "high-speed" : ""); 694 695 if (ios->power_mode == MMC_POWER_OFF) 696 mvsd_power_down(host); 697} 698 699static const struct mmc_host_ops mvsd_ops = { 700 .request = mvsd_request, 701 .get_ro = mmc_gpio_get_ro, 702 .set_ios = mvsd_set_ios, 703 .enable_sdio_irq = mvsd_enable_sdio_irq, 704}; 705 706static void 707mv_conf_mbus_windows(struct mvsd_host *host, 708 const struct mbus_dram_target_info *dram) 709{ 710 void __iomem *iobase = host->base; 711 int i; 712 713 for (i = 0; i < 4; i++) { 714 writel(0, iobase + MVSD_WINDOW_CTRL(i)); 715 writel(0, iobase + MVSD_WINDOW_BASE(i)); 716 } 717 718 for (i = 0; i < dram->num_cs; i++) { 719 const struct mbus_dram_window *cs = dram->cs + i; 720 writel(((cs->size - 1) & 0xffff0000) | 721 (cs->mbus_attr << 8) | 722 (dram->mbus_dram_target_id << 4) | 1, 723 iobase + MVSD_WINDOW_CTRL(i)); 724 writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); 725 } 726} 727 728static int mvsd_probe(struct platform_device *pdev) 729{ 730 struct device_node *np = pdev->dev.of_node; 731 struct mmc_host *mmc = NULL; 732 struct mvsd_host *host = NULL; 733 const struct mbus_dram_target_info *dram; 734 int ret, irq; 735 736 if (!np) { 737 dev_err(&pdev->dev, "no DT node\n"); 738 return -ENODEV; 739 } 740 irq = platform_get_irq(pdev, 0); 741 if (irq < 0) 742 return irq; 743 744 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); 745 if (!mmc) { 746 ret = -ENOMEM; 747 goto out; 748 } 749 750 host = mmc_priv(mmc); 751 host->mmc = mmc; 752 host->dev = &pdev->dev; 753 754 /* 755 * Some non-DT platforms do not pass a clock, and the clock 756 * frequency is passed through platform_data. On DT platforms, 757 * a clock must always be passed, even if there is no gatable 758 * clock associated to the SDIO interface (it can simply be a 759 * fixed rate clock). 760 */ 761 host->clk = devm_clk_get(&pdev->dev, NULL); 762 if (IS_ERR(host->clk)) { 763 dev_err(&pdev->dev, "no clock associated\n"); 764 ret = -EINVAL; 765 goto out; 766 } 767 clk_prepare_enable(host->clk); 768 769 mmc->ops = &mvsd_ops; 770 771 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 772 773 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); 774 mmc->f_max = MVSD_CLOCKRATE_MAX; 775 776 mmc->max_blk_size = 2048; 777 mmc->max_blk_count = 65535; 778 779 mmc->max_segs = 1; 780 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 781 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 782 783 host->base_clock = clk_get_rate(host->clk) / 2; 784 ret = mmc_of_parse(mmc); 785 if (ret < 0) 786 goto out; 787 if (maxfreq) 788 mmc->f_max = maxfreq; 789 790 spin_lock_init(&host->lock); 791 792 host->base = devm_platform_ioremap_resource(pdev, 0); 793 if (IS_ERR(host->base)) { 794 ret = PTR_ERR(host->base); 795 goto out; 796 } 797 798 /* (Re-)program MBUS remapping windows if we are asked to. */ 799 dram = mv_mbus_dram_info(); 800 if (dram) 801 mv_conf_mbus_windows(host, dram); 802 803 mvsd_power_down(host); 804 805 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host); 806 if (ret) { 807 dev_err(&pdev->dev, "cannot assign irq %d\n", irq); 808 goto out; 809 } 810 811 timer_setup(&host->timer, mvsd_timeout_timer, 0); 812 platform_set_drvdata(pdev, mmc); 813 ret = mmc_add_host(mmc); 814 if (ret) 815 goto out; 816 817 if (!(mmc->caps & MMC_CAP_NEEDS_POLL)) 818 dev_dbg(&pdev->dev, "using GPIO for card detection\n"); 819 else 820 dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n"); 821 822 return 0; 823 824out: 825 if (mmc) { 826 if (!IS_ERR(host->clk)) 827 clk_disable_unprepare(host->clk); 828 mmc_free_host(mmc); 829 } 830 831 return ret; 832} 833 834static void mvsd_remove(struct platform_device *pdev) 835{ 836 struct mmc_host *mmc = platform_get_drvdata(pdev); 837 838 struct mvsd_host *host = mmc_priv(mmc); 839 840 mmc_remove_host(mmc); 841 del_timer_sync(&host->timer); 842 mvsd_power_down(host); 843 844 if (!IS_ERR(host->clk)) 845 clk_disable_unprepare(host->clk); 846 mmc_free_host(mmc); 847} 848 849static const struct of_device_id mvsdio_dt_ids[] = { 850 { .compatible = "marvell,orion-sdio" }, 851 { /* sentinel */ } 852}; 853MODULE_DEVICE_TABLE(of, mvsdio_dt_ids); 854 855static struct platform_driver mvsd_driver = { 856 .probe = mvsd_probe, 857 .remove_new = mvsd_remove, 858 .driver = { 859 .name = DRIVER_NAME, 860 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 861 .of_match_table = mvsdio_dt_ids, 862 }, 863}; 864 865module_platform_driver(mvsd_driver); 866 867/* maximum card clock frequency (default 50MHz) */ 868module_param(maxfreq, int, 0); 869 870/* force PIO transfers all the time */ 871module_param(nodma, int, 0); 872 873MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); 874MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); 875MODULE_LICENSE("GPL"); 876MODULE_ALIAS("platform:mvsdio"); 877