1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * SPI core driver for the Ocelot chip family.
4 *
5 * This driver will handle everything necessary to allow for communication over
6 * SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
7 * are to prepare the chip's SPI interface for a specific bus speed, and a host
8 * processor's endianness. This will create and distribute regmaps for any
9 * children.
10 *
11 * Copyright 2021-2022 Innovative Advantage Inc.
12 *
13 * Author: Colin Foster <colin.foster@in-advantage.com>
14 */
15
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/errno.h>
19#include <linux/export.h>
20#include <linux/ioport.h>
21#include <linux/mod_devicetable.h>
22#include <linux/module.h>
23#include <linux/regmap.h>
24#include <linux/spi/spi.h>
25#include <linux/types.h>
26#include <linux/units.h>
27
28#include "ocelot.h"
29
30#define REG_DEV_CPUORG_IF_CTRL		0x0000
31#define REG_DEV_CPUORG_IF_CFGSTAT	0x0004
32
33#define CFGSTAT_IF_NUM_VCORE		(0 << 24)
34#define CFGSTAT_IF_NUM_VRAP		(1 << 24)
35#define CFGSTAT_IF_NUM_SI		(2 << 24)
36#define CFGSTAT_IF_NUM_MIIM		(3 << 24)
37
38#define VSC7512_DEVCPU_ORG_RES_START	0x71000000
39#define VSC7512_DEVCPU_ORG_RES_SIZE	0x38
40
41#define VSC7512_CHIP_REGS_RES_START	0x71070000
42#define VSC7512_CHIP_REGS_RES_SIZE	0x14
43
44static const struct resource vsc7512_dev_cpuorg_resource =
45	DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
46			     VSC7512_DEVCPU_ORG_RES_SIZE,
47			     "devcpu_org");
48
49static const struct resource vsc7512_gcb_resource =
50	DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
51			     VSC7512_CHIP_REGS_RES_SIZE,
52			     "devcpu_gcb_chip_regs");
53
54static int ocelot_spi_initialize(struct device *dev)
55{
56	struct ocelot_ddata *ddata = dev_get_drvdata(dev);
57	u32 val, check;
58	int err;
59
60	val = OCELOT_SPI_BYTE_ORDER;
61
62	/*
63	 * The SPI address must be big-endian, but we want the payload to match
64	 * our CPU. These are two bits (0 and 1) but they're repeated such that
65	 * the write from any configuration will be valid. The four
66	 * configurations are:
67	 *
68	 * 0b00: little-endian, MSB first
69	 * |            111111   | 22221111 | 33222222 |
70	 * | 76543210 | 54321098 | 32109876 | 10987654 |
71	 *
72	 * 0b01: big-endian, MSB first
73	 * | 33222222 | 22221111 | 111111   |          |
74	 * | 10987654 | 32109876 | 54321098 | 76543210 |
75	 *
76	 * 0b10: little-endian, LSB first
77	 * |              111111 | 11112222 | 22222233 |
78	 * | 01234567 | 89012345 | 67890123 | 45678901 |
79	 *
80	 * 0b11: big-endian, LSB first
81	 * | 22222233 | 11112222 |   111111 |          |
82	 * | 45678901 | 67890123 | 89012345 | 01234567 |
83	 */
84	err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
85	if (err)
86		return err;
87
88	/*
89	 * Apply the number of padding bytes between a read request and the data
90	 * payload. Some registers have access times of up to 1us, so if the
91	 * first payload bit is shifted out too quickly, the read will fail.
92	 */
93	val = ddata->spi_padding_bytes;
94	err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
95	if (err)
96		return err;
97
98	/*
99	 * After we write the interface configuration, read it back here. This
100	 * will verify several different things. The first is that the number of
101	 * padding bytes actually got written correctly. These are found in bits
102	 * 0:3.
103	 *
104	 * The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
105	 * and will be set if the register access is too fast. This would be in
106	 * the condition that the number of padding bytes is insufficient for
107	 * the SPI bus frequency.
108	 *
109	 * The last check is for bits 31:24, which define the interface by which
110	 * the registers are being accessed. Since we're accessing them via the
111	 * serial interface, it must return IF_NUM_SI.
112	 */
113	check = val | CFGSTAT_IF_NUM_SI;
114
115	err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
116	if (err)
117		return err;
118
119	if (check != val)
120		return -ENODEV;
121
122	return 0;
123}
124
125static const struct regmap_config ocelot_spi_regmap_config = {
126	.reg_bits = 24,
127	.reg_stride = 4,
128	.reg_shift = REGMAP_DOWNSHIFT(2),
129	.val_bits = 32,
130
131	.write_flag_mask = 0x80,
132
133	.use_single_read = true,
134	.use_single_write = true,
135	.can_multi_write = false,
136
137	.reg_format_endian = REGMAP_ENDIAN_BIG,
138	.val_format_endian = REGMAP_ENDIAN_NATIVE,
139};
140
141static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
142				      void *val, size_t val_size)
143{
144	struct spi_transfer xfers[3] = {0};
145	struct device *dev = context;
146	struct ocelot_ddata *ddata;
147	struct spi_device *spi;
148	struct spi_message msg;
149	unsigned int index = 0;
150
151	ddata = dev_get_drvdata(dev);
152	spi = to_spi_device(dev);
153
154	xfers[index].tx_buf = reg;
155	xfers[index].len = reg_size;
156	index++;
157
158	if (ddata->spi_padding_bytes) {
159		xfers[index].len = ddata->spi_padding_bytes;
160		xfers[index].tx_buf = ddata->dummy_buf;
161		xfers[index].dummy_data = 1;
162		index++;
163	}
164
165	xfers[index].rx_buf = val;
166	xfers[index].len = val_size;
167	index++;
168
169	spi_message_init_with_transfers(&msg, xfers, index);
170
171	return spi_sync(spi, &msg);
172}
173
174static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
175{
176	struct device *dev = context;
177	struct spi_device *spi = to_spi_device(dev);
178
179	return spi_write(spi, data, count);
180}
181
182static const struct regmap_bus ocelot_spi_regmap_bus = {
183	.write = ocelot_spi_regmap_bus_write,
184	.read = ocelot_spi_regmap_bus_read,
185};
186
187struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
188{
189	struct regmap_config regmap_config;
190
191	memcpy(&regmap_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
192
193	regmap_config.name = res->name;
194	regmap_config.max_register = resource_size(res) - 1;
195	regmap_config.reg_base = res->start;
196
197	return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, &regmap_config);
198}
199EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);
200
201static int ocelot_spi_probe(struct spi_device *spi)
202{
203	struct device *dev = &spi->dev;
204	struct ocelot_ddata *ddata;
205	struct regmap *r;
206	int err;
207
208	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
209	if (!ddata)
210		return -ENOMEM;
211
212	spi_set_drvdata(spi, ddata);
213
214	if (spi->max_speed_hz <= 500000) {
215		ddata->spi_padding_bytes = 0;
216	} else {
217		/*
218		 * Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
219		 * Register access time is 1us, so we need to configure and send
220		 * out enough padding bytes between the read request and data
221		 * transmission that lasts at least 1 microsecond.
222		 */
223		ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
224
225		ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
226		if (!ddata->dummy_buf)
227			return -ENOMEM;
228	}
229
230	spi->bits_per_word = 8;
231
232	err = spi_setup(spi);
233	if (err)
234		return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
235
236	r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
237	if (IS_ERR(r))
238		return PTR_ERR(r);
239
240	ddata->cpuorg_regmap = r;
241
242	r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
243	if (IS_ERR(r))
244		return PTR_ERR(r);
245
246	ddata->gcb_regmap = r;
247
248	/*
249	 * The chip must be set up for SPI before it gets initialized and reset.
250	 * This must be done before calling init, and after a chip reset is
251	 * performed.
252	 */
253	err = ocelot_spi_initialize(dev);
254	if (err)
255		return dev_err_probe(dev, err, "Error initializing SPI bus\n");
256
257	err = ocelot_chip_reset(dev);
258	if (err)
259		return dev_err_probe(dev, err, "Error resetting device\n");
260
261	/*
262	 * A chip reset will clear the SPI configuration, so it needs to be done
263	 * again before we can access any registers.
264	 */
265	err = ocelot_spi_initialize(dev);
266	if (err)
267		return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
268
269	err = ocelot_core_init(dev);
270	if (err)
271		return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
272
273	return 0;
274}
275
276static const struct spi_device_id ocelot_spi_ids[] = {
277	{ "vsc7512", 0 },
278	{ }
279};
280MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);
281
282static const struct of_device_id ocelot_spi_of_match[] = {
283	{ .compatible = "mscc,vsc7512" },
284	{ }
285};
286MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
287
288static struct spi_driver ocelot_spi_driver = {
289	.driver = {
290		.name = "ocelot-soc",
291		.of_match_table = ocelot_spi_of_match,
292	},
293	.id_table = ocelot_spi_ids,
294	.probe = ocelot_spi_probe,
295};
296module_spi_driver(ocelot_spi_driver);
297
298MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
299MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
300MODULE_LICENSE("Dual MIT/GPL");
301MODULE_IMPORT_NS(MFD_OCELOT);
302