1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Hantro VPU codec driver 4 * 5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 6 */ 7 8#include <asm/unaligned.h> 9#include <linux/bitfield.h> 10#include <media/v4l2-mem2mem.h> 11#include "hantro.h" 12#include "hantro_hw.h" 13 14#define VDPU_SWREG(nr) ((nr) * 4) 15 16#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63) 17#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64) 18#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61) 19#define VDPU_REG_REFER0_BASE VDPU_SWREG(131) 20#define VDPU_REG_REFER2_BASE VDPU_SWREG(134) 21#define VDPU_REG_REFER3_BASE VDPU_SWREG(135) 22#define VDPU_REG_REFER1_BASE VDPU_SWREG(148) 23#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) 24 25#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) 26#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) 27#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) 28#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) 29 30#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) 31#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) 32 33#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) 34#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) 35#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) 36 37#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0)) 38 39#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0) 40#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0) 41#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0) 42#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) 43#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) 44#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) 45 46#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0) 47#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16)) 48#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8)) 49#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0)) 50 51#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) 52#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0) 53#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0) 54#define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0) 55#define VDPU_REG_PIC_INTER_E(v) ((v) ? BIT(14) : 0) 56#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0) 57#define VDPU_REG_FWD_INTERLACE_E(v) ((v) ? BIT(12) : 0) 58#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0) 59#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0) 60#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0) 61 62#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23)) 63#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11)) 64#define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) 65#define VDPU_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0) 66 67#define VDPU_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26)) 68#define VDPU_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0) 69#define VDPU_REG_CON_MV_E(v) ((v) ? BIT(4) : 0) 70#define VDPU_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2)) 71#define VDPU_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0) 72#define VDPU_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0) 73 74#define VDPU_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0) 75#define VDPU_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15)) 76#define VDPU_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11)) 77#define VDPU_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7)) 78#define VDPU_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3)) 79#define VDPU_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0) 80#define VDPU_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0) 81 82static void 83rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, 84 struct hantro_ctx *ctx) 85{ 86 struct v4l2_ctrl_mpeg2_quantisation *q; 87 88 q = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_MPEG2_QUANTISATION); 89 hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, q); 90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); 91} 92 93static void 94rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, 95 struct hantro_ctx *ctx, 96 struct vb2_buffer *src_buf, 97 struct vb2_buffer *dst_buf, 98 const struct v4l2_ctrl_mpeg2_sequence *seq, 99 const struct v4l2_ctrl_mpeg2_picture *pic) 100{ 101 dma_addr_t forward_addr = 0, backward_addr = 0; 102 dma_addr_t current_addr, addr; 103 104 switch (pic->picture_coding_type) { 105 case V4L2_MPEG2_PIC_CODING_TYPE_B: 106 backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts); 107 fallthrough; 108 case V4L2_MPEG2_PIC_CODING_TYPE_P: 109 forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts); 110 } 111 112 /* Source bitstream buffer */ 113 addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); 114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); 115 116 /* Destination frame buffer */ 117 addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0); 118 current_addr = addr; 119 120 if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) 121 addr += ALIGN(ctx->dst_fmt.width, 16); 122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); 123 124 if (!forward_addr) 125 forward_addr = current_addr; 126 if (!backward_addr) 127 backward_addr = current_addr; 128 129 /* Set forward ref frame (top/bottom field) */ 130 if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME || 131 pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B || 132 (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD && 133 pic->flags & V4L2_MPEG2_PIC_TOP_FIELD) || 134 (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD && 135 !(pic->flags & V4L2_MPEG2_PIC_TOP_FIELD))) { 136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); 137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); 138 } else if (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) { 139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); 140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); 141 } else if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) { 142 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE); 143 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); 144 } 145 146 /* Set backward ref frame (top/bottom field) */ 147 vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE); 148 vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE); 149} 150 151int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx) 152{ 153 struct hantro_dev *vpu = ctx->dev; 154 struct vb2_v4l2_buffer *src_buf, *dst_buf; 155 const struct v4l2_ctrl_mpeg2_sequence *seq; 156 const struct v4l2_ctrl_mpeg2_picture *pic; 157 u32 reg; 158 159 src_buf = hantro_get_src_buf(ctx); 160 dst_buf = hantro_get_dst_buf(ctx); 161 162 hantro_start_prepare_run(ctx); 163 164 seq = hantro_get_ctrl(ctx, 165 V4L2_CID_STATELESS_MPEG2_SEQUENCE); 166 pic = hantro_get_ctrl(ctx, 167 V4L2_CID_STATELESS_MPEG2_PICTURE); 168 169 reg = VDPU_REG_DEC_ADV_PRE_DIS(0) | 170 VDPU_REG_DEC_SCMD_DIS(0) | 171 VDPU_REG_FILTERING_DIS(1) | 172 VDPU_REG_DEC_LATENCY(0); 173 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); 174 175 reg = VDPU_REG_INIT_QP(1) | 176 VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); 177 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); 178 179 reg = VDPU_REG_APF_THRESHOLD(8) | 180 VDPU_REG_STARTMB_X(0) | 181 VDPU_REG_STARTMB_Y(0); 182 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); 183 184 reg = VDPU_REG_DEC_MODE(5); 185 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); 186 187 reg = VDPU_REG_DEC_STRENDIAN_E(1) | 188 VDPU_REG_DEC_STRSWAP32_E(1) | 189 VDPU_REG_DEC_OUTSWAP32_E(1) | 190 VDPU_REG_DEC_INSWAP32_E(1) | 191 VDPU_REG_DEC_OUT_ENDIAN(1) | 192 VDPU_REG_DEC_IN_ENDIAN(1); 193 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); 194 195 reg = VDPU_REG_DEC_DATA_DISC_E(0) | 196 VDPU_REG_DEC_MAX_BURST(16) | 197 VDPU_REG_DEC_AXI_WR_ID(0) | 198 VDPU_REG_DEC_AXI_RD_ID(0); 199 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); 200 201 reg = VDPU_REG_RLC_MODE_E(0) | 202 VDPU_REG_PIC_INTERLACE_E(!(seq->flags & V4L2_MPEG2_SEQ_FLAG_PROGRESSIVE)) | 203 VDPU_REG_PIC_FIELDMODE_E(pic->picture_structure != V4L2_MPEG2_PIC_FRAME) | 204 VDPU_REG_PIC_B_E(pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B) | 205 VDPU_REG_PIC_INTER_E(pic->picture_coding_type != V4L2_MPEG2_PIC_CODING_TYPE_I) | 206 VDPU_REG_PIC_TOPFIELD_E(pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) | 207 VDPU_REG_FWD_INTERLACE_E(0) | 208 VDPU_REG_WRITE_MVS_E(0) | 209 VDPU_REG_DEC_TIMEOUT_E(1) | 210 VDPU_REG_DEC_CLK_GATE_E(1); 211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); 212 213 reg = VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) | 214 VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) | 215 VDPU_REG_ALT_SCAN_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) | 216 VDPU_REG_TOPFIELDFIRST_E(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST); 217 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120)); 218 219 reg = VDPU_REG_STRM_START_BIT(0) | 220 VDPU_REG_QSCALE_TYPE(pic->flags & V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE) | 221 VDPU_REG_CON_MV_E(pic->flags & V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV) | 222 VDPU_REG_INTRA_DC_PREC(pic->intra_dc_precision) | 223 VDPU_REG_INTRA_VLC_TAB(pic->flags & V4L2_MPEG2_PIC_FLAG_INTRA_VLC) | 224 VDPU_REG_FRAME_PRED_DCT(pic->flags & V4L2_MPEG2_PIC_FLAG_FRAME_PRED_DCT); 225 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122)); 226 227 reg = VDPU_REG_ALT_SCAN_FLAG_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) | 228 VDPU_REG_FCODE_FWD_HOR(pic->f_code[0][0]) | 229 VDPU_REG_FCODE_FWD_VER(pic->f_code[0][1]) | 230 VDPU_REG_FCODE_BWD_HOR(pic->f_code[1][0]) | 231 VDPU_REG_FCODE_BWD_VER(pic->f_code[1][1]) | 232 VDPU_REG_MV_ACCURACY_FWD(1) | 233 VDPU_REG_MV_ACCURACY_BWD(1); 234 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136)); 235 236 rockchip_vpu2_mpeg2_dec_set_quantisation(vpu, ctx); 237 238 rockchip_vpu2_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf, 239 &dst_buf->vb2_buf, seq, pic); 240 241 /* Kick the watchdog and start decoding */ 242 hantro_end_prepare_run(ctx); 243 244 reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1); 245 vdpu_write(vpu, reg, VDPU_SWREG(57)); 246 247 return 0; 248} 249