1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Hantro VPU codec driver 4 * 5 * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz <andrzej.p@collabora.com> 6 */ 7 8#include "hantro_hw.h" 9#include "hantro_g2_regs.h" 10 11#define G2_ALIGN 16 12 13void hantro_g2_check_idle(struct hantro_dev *vpu) 14{ 15 int i; 16 17 for (i = 0; i < 3; i++) { 18 u32 status; 19 20 /* Make sure the VPU is idle */ 21 status = vdpu_read(vpu, G2_REG_INTERRUPT); 22 if (status & G2_REG_INTERRUPT_DEC_E) { 23 dev_warn(vpu->dev, "device still running, aborting"); 24 status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; 25 vdpu_write(vpu, status, G2_REG_INTERRUPT); 26 } 27 } 28} 29 30irqreturn_t hantro_g2_irq(int irq, void *dev_id) 31{ 32 struct hantro_dev *vpu = dev_id; 33 enum vb2_buffer_state state; 34 u32 status; 35 36 status = vdpu_read(vpu, G2_REG_INTERRUPT); 37 state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? 38 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; 39 40 vdpu_write(vpu, 0, G2_REG_INTERRUPT); 41 vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); 42 43 hantro_irq_done(vpu, state); 44 45 return IRQ_HANDLED; 46} 47 48size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx) 49{ 50 return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8; 51} 52 53size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx) 54{ 55 size_t cr_offset = hantro_g2_chroma_offset(ctx); 56 57 return ALIGN((cr_offset * 3) / 2, G2_ALIGN); 58} 59