1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Hantro VP8 codec driver 4 * 5 * Copyright (C) 2019 Rockchip Electronics Co., Ltd. 6 * ZhiChao Yu <zhichao.yu@rock-chips.com> 7 * 8 * Copyright (C) 2019 Google, Inc. 9 * Tomasz Figa <tfiga@chromium.org> 10 */ 11 12#include <media/v4l2-mem2mem.h> 13 14#include "hantro_hw.h" 15#include "hantro.h" 16#include "hantro_g1_regs.h" 17 18/* DCT partition base address regs */ 19static const struct hantro_reg vp8_dec_dct_base[8] = { 20 { G1_REG_ADDR_STR, 0, 0xffffffff }, 21 { G1_REG_ADDR_REF(8), 0, 0xffffffff }, 22 { G1_REG_ADDR_REF(9), 0, 0xffffffff }, 23 { G1_REG_ADDR_REF(10), 0, 0xffffffff }, 24 { G1_REG_ADDR_REF(11), 0, 0xffffffff }, 25 { G1_REG_ADDR_REF(12), 0, 0xffffffff }, 26 { G1_REG_ADDR_REF(14), 0, 0xffffffff }, 27 { G1_REG_ADDR_REF(15), 0, 0xffffffff }, 28}; 29 30/* Loop filter level regs */ 31static const struct hantro_reg vp8_dec_lf_level[4] = { 32 { G1_REG_REF_PIC(2), 18, 0x3f }, 33 { G1_REG_REF_PIC(2), 12, 0x3f }, 34 { G1_REG_REF_PIC(2), 6, 0x3f }, 35 { G1_REG_REF_PIC(2), 0, 0x3f }, 36}; 37 38/* Macroblock loop filter level adjustment regs */ 39static const struct hantro_reg vp8_dec_mb_adj[4] = { 40 { G1_REG_REF_PIC(0), 21, 0x7f }, 41 { G1_REG_REF_PIC(0), 14, 0x7f }, 42 { G1_REG_REF_PIC(0), 7, 0x7f }, 43 { G1_REG_REF_PIC(0), 0, 0x7f }, 44}; 45 46/* Reference frame adjustment regs */ 47static const struct hantro_reg vp8_dec_ref_adj[4] = { 48 { G1_REG_REF_PIC(1), 21, 0x7f }, 49 { G1_REG_REF_PIC(1), 14, 0x7f }, 50 { G1_REG_REF_PIC(1), 7, 0x7f }, 51 { G1_REG_REF_PIC(1), 0, 0x7f }, 52}; 53 54/* Quantizer */ 55static const struct hantro_reg vp8_dec_quant[4] = { 56 { G1_REG_REF_PIC(3), 11, 0x7ff }, 57 { G1_REG_REF_PIC(3), 0, 0x7ff }, 58 { G1_REG_BD_REF_PIC(4), 11, 0x7ff }, 59 { G1_REG_BD_REF_PIC(4), 0, 0x7ff }, 60}; 61 62/* Quantizer delta regs */ 63static const struct hantro_reg vp8_dec_quant_delta[5] = { 64 { G1_REG_REF_PIC(3), 27, 0x1f }, 65 { G1_REG_REF_PIC(3), 22, 0x1f }, 66 { G1_REG_BD_REF_PIC(4), 27, 0x1f }, 67 { G1_REG_BD_REF_PIC(4), 22, 0x1f }, 68 { G1_REG_BD_P_REF_PIC, 27, 0x1f }, 69}; 70 71/* DCT partition start bits regs */ 72static const struct hantro_reg vp8_dec_dct_start_bits[8] = { 73 { G1_REG_DEC_CTRL2, 26, 0x3f }, { G1_REG_DEC_CTRL4, 26, 0x3f }, 74 { G1_REG_DEC_CTRL4, 20, 0x3f }, { G1_REG_DEC_CTRL7, 24, 0x3f }, 75 { G1_REG_DEC_CTRL7, 18, 0x3f }, { G1_REG_DEC_CTRL7, 12, 0x3f }, 76 { G1_REG_DEC_CTRL7, 6, 0x3f }, { G1_REG_DEC_CTRL7, 0, 0x3f }, 77}; 78 79/* Precision filter tap regs */ 80static const struct hantro_reg vp8_dec_pred_bc_tap[8][4] = { 81 { 82 { G1_REG_PRED_FLT, 22, 0x3ff }, 83 { G1_REG_PRED_FLT, 12, 0x3ff }, 84 { G1_REG_PRED_FLT, 2, 0x3ff }, 85 { G1_REG_REF_PIC(4), 22, 0x3ff }, 86 }, 87 { 88 { G1_REG_REF_PIC(4), 12, 0x3ff }, 89 { G1_REG_REF_PIC(4), 2, 0x3ff }, 90 { G1_REG_REF_PIC(5), 22, 0x3ff }, 91 { G1_REG_REF_PIC(5), 12, 0x3ff }, 92 }, 93 { 94 { G1_REG_REF_PIC(5), 2, 0x3ff }, 95 { G1_REG_REF_PIC(6), 22, 0x3ff }, 96 { G1_REG_REF_PIC(6), 12, 0x3ff }, 97 { G1_REG_REF_PIC(6), 2, 0x3ff }, 98 }, 99 { 100 { G1_REG_REF_PIC(7), 22, 0x3ff }, 101 { G1_REG_REF_PIC(7), 12, 0x3ff }, 102 { G1_REG_REF_PIC(7), 2, 0x3ff }, 103 { G1_REG_LT_REF, 22, 0x3ff }, 104 }, 105 { 106 { G1_REG_LT_REF, 12, 0x3ff }, 107 { G1_REG_LT_REF, 2, 0x3ff }, 108 { G1_REG_VALID_REF, 22, 0x3ff }, 109 { G1_REG_VALID_REF, 12, 0x3ff }, 110 }, 111 { 112 { G1_REG_VALID_REF, 2, 0x3ff }, 113 { G1_REG_BD_REF_PIC(0), 22, 0x3ff }, 114 { G1_REG_BD_REF_PIC(0), 12, 0x3ff }, 115 { G1_REG_BD_REF_PIC(0), 2, 0x3ff }, 116 }, 117 { 118 { G1_REG_BD_REF_PIC(1), 22, 0x3ff }, 119 { G1_REG_BD_REF_PIC(1), 12, 0x3ff }, 120 { G1_REG_BD_REF_PIC(1), 2, 0x3ff }, 121 { G1_REG_BD_REF_PIC(2), 22, 0x3ff }, 122 }, 123 { 124 { G1_REG_BD_REF_PIC(2), 12, 0x3ff }, 125 { G1_REG_BD_REF_PIC(2), 2, 0x3ff }, 126 { G1_REG_BD_REF_PIC(3), 22, 0x3ff }, 127 { G1_REG_BD_REF_PIC(3), 12, 0x3ff }, 128 }, 129}; 130 131/* 132 * Set loop filters 133 */ 134static void cfg_lf(struct hantro_ctx *ctx, 135 const struct v4l2_ctrl_vp8_frame *hdr) 136{ 137 const struct v4l2_vp8_segment *seg = &hdr->segment; 138 const struct v4l2_vp8_loop_filter *lf = &hdr->lf; 139 struct hantro_dev *vpu = ctx->dev; 140 unsigned int i; 141 u32 reg; 142 143 if (!(seg->flags & V4L2_VP8_SEGMENT_FLAG_ENABLED)) { 144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); 145 } else if (seg->flags & V4L2_VP8_SEGMENT_FLAG_DELTA_VALUE_MODE) { 146 for (i = 0; i < 4; i++) { 147 u32 lf_level = clamp(lf->level + seg->lf_update[i], 148 0, 63); 149 150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); 151 } 152 } else { 153 for (i = 0; i < 4; i++) 154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], 155 seg->lf_update[i]); 156 } 157 158 reg = G1_REG_REF_PIC_FILT_SHARPNESS(lf->sharpness_level); 159 if (lf->flags & V4L2_VP8_LF_FILTER_TYPE_SIMPLE) 160 reg |= G1_REG_REF_PIC_FILT_TYPE_E; 161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); 162 163 if (lf->flags & V4L2_VP8_LF_ADJ_ENABLE) { 164 for (i = 0; i < 4; i++) { 165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], 166 lf->mb_mode_delta[i]); 167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], 168 lf->ref_frm_delta[i]); 169 } 170 } 171} 172 173/* 174 * Set quantization parameters 175 */ 176static void cfg_qp(struct hantro_ctx *ctx, 177 const struct v4l2_ctrl_vp8_frame *hdr) 178{ 179 const struct v4l2_vp8_quantization *q = &hdr->quant; 180 const struct v4l2_vp8_segment *seg = &hdr->segment; 181 struct hantro_dev *vpu = ctx->dev; 182 unsigned int i; 183 184 if (!(seg->flags & V4L2_VP8_SEGMENT_FLAG_ENABLED)) { 185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); 186 } else if (seg->flags & V4L2_VP8_SEGMENT_FLAG_DELTA_VALUE_MODE) { 187 for (i = 0; i < 4; i++) { 188 u32 quant = clamp(q->y_ac_qi + seg->quant_update[i], 189 0, 127); 190 191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); 192 } 193 } else { 194 for (i = 0; i < 4; i++) 195 hantro_reg_write(vpu, &vp8_dec_quant[i], 196 seg->quant_update[i]); 197 } 198 199 hantro_reg_write(vpu, &vp8_dec_quant_delta[0], q->y_dc_delta); 200 hantro_reg_write(vpu, &vp8_dec_quant_delta[1], q->y2_dc_delta); 201 hantro_reg_write(vpu, &vp8_dec_quant_delta[2], q->y2_ac_delta); 202 hantro_reg_write(vpu, &vp8_dec_quant_delta[3], q->uv_dc_delta); 203 hantro_reg_write(vpu, &vp8_dec_quant_delta[4], q->uv_ac_delta); 204} 205 206/* 207 * set control partition and DCT partition regs 208 * 209 * VP8 frame stream data layout: 210 * 211 * first_part_size parttion_sizes[0] 212 * ^ ^ 213 * src_dma | | 214 * ^ +--------+------+ +-----+-----+ 215 * | | control part | | | 216 * +--------+----------------+------------------+-----------+-----+-----------+ 217 * | tag 3B | extra 7B | hdr | mb_data | DCT sz | DCT part0 | ... | DCT partn | 218 * +--------+-----------------------------------+-----------+-----+-----------+ 219 * | | | | 220 * v +----+---+ v 221 * mb_start | src_dma_end 222 * v 223 * DCT size part 224 * (num_dct-1)*3B 225 * Note: 226 * 1. only key-frames have extra 7-bytes 227 * 2. all offsets are base on src_dma 228 * 3. number of DCT parts is 1, 2, 4 or 8 229 * 4. the addresses set to the VPU must be 64-bits aligned 230 */ 231static void cfg_parts(struct hantro_ctx *ctx, 232 const struct v4l2_ctrl_vp8_frame *hdr) 233{ 234 struct hantro_dev *vpu = ctx->dev; 235 struct vb2_v4l2_buffer *vb2_src; 236 u32 first_part_offset = V4L2_VP8_FRAME_IS_KEY_FRAME(hdr) ? 10 : 3; 237 u32 mb_size, mb_offset_bytes, mb_offset_bits, mb_start_bits; 238 u32 dct_size_part_size, dct_part_offset; 239 struct hantro_reg reg; 240 dma_addr_t src_dma; 241 u32 dct_part_total_len = 0; 242 u32 count = 0; 243 unsigned int i; 244 245 vb2_src = hantro_get_src_buf(ctx); 246 src_dma = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); 247 248 /* 249 * Calculate control partition mb data info 250 * @first_part_header_bits: bits offset of mb data from first 251 * part start pos 252 * @mb_offset_bits: bits offset of mb data from src_dma 253 * base addr 254 * @mb_offset_byte: bytes offset of mb data from src_dma 255 * base addr 256 * @mb_start_bits: bits offset of mb data from mb data 257 * 64bits alignment addr 258 */ 259 mb_offset_bits = first_part_offset * 8 + 260 hdr->first_part_header_bits + 8; 261 mb_offset_bytes = mb_offset_bits / 8; 262 mb_start_bits = mb_offset_bits - 263 (mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) * 8; 264 mb_size = hdr->first_part_size - 265 (mb_offset_bytes - first_part_offset) + 266 (mb_offset_bytes & DEC_8190_ALIGN_MASK); 267 268 /* Macroblock data aligned base addr */ 269 vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) 270 + src_dma, G1_REG_ADDR_REF(13)); 271 272 /* Macroblock data start bits */ 273 reg.base = G1_REG_DEC_CTRL2; 274 reg.mask = 0x3f; 275 reg.shift = 18; 276 hantro_reg_write(vpu, ®, mb_start_bits); 277 278 /* Macroblock aligned data length */ 279 reg.base = G1_REG_DEC_CTRL6; 280 reg.mask = 0x3fffff; 281 reg.shift = 0; 282 hantro_reg_write(vpu, ®, mb_size + 1); 283 284 /* 285 * Calculate DCT partition info 286 * @dct_size_part_size: Containing sizes of DCT part, every DCT part 287 * has 3 bytes to store its size, except the last 288 * DCT part 289 * @dct_part_offset: bytes offset of DCT parts from src_dma base addr 290 * @dct_part_total_len: total size of all DCT parts 291 */ 292 dct_size_part_size = (hdr->num_dct_parts - 1) * 3; 293 dct_part_offset = first_part_offset + hdr->first_part_size; 294 for (i = 0; i < hdr->num_dct_parts; i++) 295 dct_part_total_len += hdr->dct_part_sizes[i]; 296 dct_part_total_len += dct_size_part_size; 297 dct_part_total_len += (dct_part_offset & DEC_8190_ALIGN_MASK); 298 299 /* Number of DCT partitions */ 300 reg.base = G1_REG_DEC_CTRL6; 301 reg.mask = 0xf; 302 reg.shift = 24; 303 hantro_reg_write(vpu, ®, hdr->num_dct_parts - 1); 304 305 /* DCT partition length */ 306 vdpu_write_relaxed(vpu, 307 G1_REG_DEC_CTRL3_STREAM_LEN(dct_part_total_len), 308 G1_REG_DEC_CTRL3); 309 310 /* DCT partitions base address */ 311 for (i = 0; i < hdr->num_dct_parts; i++) { 312 u32 byte_offset = dct_part_offset + dct_size_part_size + count; 313 u32 base_addr = byte_offset + src_dma; 314 315 hantro_reg_write(vpu, &vp8_dec_dct_base[i], 316 base_addr & (~DEC_8190_ALIGN_MASK)); 317 318 hantro_reg_write(vpu, &vp8_dec_dct_start_bits[i], 319 (byte_offset & DEC_8190_ALIGN_MASK) * 8); 320 321 count += hdr->dct_part_sizes[i]; 322 } 323} 324 325/* 326 * prediction filter taps 327 * normal 6-tap filters 328 */ 329static void cfg_tap(struct hantro_ctx *ctx, 330 const struct v4l2_ctrl_vp8_frame *hdr) 331{ 332 struct hantro_dev *vpu = ctx->dev; 333 struct hantro_reg reg; 334 u32 val = 0; 335 int i, j; 336 337 reg.base = G1_REG_BD_REF_PIC(3); 338 reg.mask = 0xf; 339 340 if ((hdr->version & 0x03) != 0) 341 return; /* Tap filter not used. */ 342 343 for (i = 0; i < 8; i++) { 344 val = (hantro_vp8_dec_mc_filter[i][0] << 2) | 345 hantro_vp8_dec_mc_filter[i][5]; 346 347 for (j = 0; j < 4; j++) 348 hantro_reg_write(vpu, &vp8_dec_pred_bc_tap[i][j], 349 hantro_vp8_dec_mc_filter[i][j + 1]); 350 351 switch (i) { 352 case 2: 353 reg.shift = 8; 354 break; 355 case 4: 356 reg.shift = 4; 357 break; 358 case 6: 359 reg.shift = 0; 360 break; 361 default: 362 continue; 363 } 364 365 hantro_reg_write(vpu, ®, val); 366 } 367} 368 369static void cfg_ref(struct hantro_ctx *ctx, 370 const struct v4l2_ctrl_vp8_frame *hdr, 371 struct vb2_v4l2_buffer *vb2_dst) 372{ 373 struct hantro_dev *vpu = ctx->dev; 374 dma_addr_t ref; 375 376 377 ref = hantro_get_ref(ctx, hdr->last_frame_ts); 378 if (!ref) { 379 vpu_debug(0, "failed to find last frame ts=%llu\n", 380 hdr->last_frame_ts); 381 ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); 382 } 383 vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0)); 384 385 ref = hantro_get_ref(ctx, hdr->golden_frame_ts); 386 if (!ref && hdr->golden_frame_ts) 387 vpu_debug(0, "failed to find golden frame ts=%llu\n", 388 hdr->golden_frame_ts); 389 if (!ref) 390 ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); 391 if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) 392 ref |= G1_REG_ADDR_REF_TOPC_E; 393 vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4)); 394 395 ref = hantro_get_ref(ctx, hdr->alt_frame_ts); 396 if (!ref && hdr->alt_frame_ts) 397 vpu_debug(0, "failed to find alt frame ts=%llu\n", 398 hdr->alt_frame_ts); 399 if (!ref) 400 ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); 401 if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) 402 ref |= G1_REG_ADDR_REF_TOPC_E; 403 vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(5)); 404} 405 406static void cfg_buffers(struct hantro_ctx *ctx, 407 const struct v4l2_ctrl_vp8_frame *hdr, 408 struct vb2_v4l2_buffer *vb2_dst) 409{ 410 const struct v4l2_vp8_segment *seg = &hdr->segment; 411 struct hantro_dev *vpu = ctx->dev; 412 dma_addr_t dst_dma; 413 u32 reg; 414 415 /* Set probability table buffer address */ 416 vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, 417 G1_REG_ADDR_QTABLE); 418 419 /* Set segment map address */ 420 reg = G1_REG_FWD_PIC1_SEGMENT_BASE(ctx->vp8_dec.segment_map.dma); 421 if (seg->flags & V4L2_VP8_SEGMENT_FLAG_ENABLED) { 422 reg |= G1_REG_FWD_PIC1_SEGMENT_E; 423 if (seg->flags & V4L2_VP8_SEGMENT_FLAG_UPDATE_MAP) 424 reg |= G1_REG_FWD_PIC1_SEGMENT_UPD_E; 425 } 426 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0)); 427 428 dst_dma = hantro_get_dec_buf_addr(ctx, &vb2_dst->vb2_buf); 429 vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST); 430} 431 432int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) 433{ 434 const struct v4l2_ctrl_vp8_frame *hdr; 435 struct hantro_dev *vpu = ctx->dev; 436 struct vb2_v4l2_buffer *vb2_dst; 437 size_t height = ctx->dst_fmt.height; 438 size_t width = ctx->dst_fmt.width; 439 u32 mb_width, mb_height; 440 u32 reg; 441 442 hantro_start_prepare_run(ctx); 443 444 hdr = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_VP8_FRAME); 445 if (WARN_ON(!hdr)) 446 return -EINVAL; 447 448 /* Reset segment_map buffer in keyframe */ 449 if (V4L2_VP8_FRAME_IS_KEY_FRAME(hdr) && ctx->vp8_dec.segment_map.cpu) 450 memset(ctx->vp8_dec.segment_map.cpu, 0, 451 ctx->vp8_dec.segment_map.size); 452 453 hantro_vp8_prob_update(ctx, hdr); 454 455 reg = G1_REG_CONFIG_DEC_TIMEOUT_E | 456 G1_REG_CONFIG_DEC_STRENDIAN_E | 457 G1_REG_CONFIG_DEC_INSWAP32_E | 458 G1_REG_CONFIG_DEC_STRSWAP32_E | 459 G1_REG_CONFIG_DEC_OUTSWAP32_E | 460 G1_REG_CONFIG_DEC_CLK_GATE_E | 461 G1_REG_CONFIG_DEC_IN_ENDIAN | 462 G1_REG_CONFIG_DEC_OUT_ENDIAN | 463 G1_REG_CONFIG_DEC_MAX_BURST(16); 464 vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG); 465 466 reg = G1_REG_DEC_CTRL0_DEC_MODE(10) | 467 G1_REG_DEC_CTRL0_DEC_AXI_AUTO; 468 if (!V4L2_VP8_FRAME_IS_KEY_FRAME(hdr)) 469 reg |= G1_REG_DEC_CTRL0_PIC_INTER_E; 470 if (!(hdr->flags & V4L2_VP8_FRAME_FLAG_MB_NO_SKIP_COEFF)) 471 reg |= G1_REG_DEC_CTRL0_SKIP_MODE; 472 if (hdr->lf.level == 0) 473 reg |= G1_REG_DEC_CTRL0_FILTERING_DIS; 474 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); 475 476 /* Frame dimensions */ 477 mb_width = MB_WIDTH(width); 478 mb_height = MB_HEIGHT(height); 479 reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(mb_width) | 480 G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(mb_height) | 481 G1_REG_DEC_CTRL1_PIC_MB_W_EXT(mb_width >> 9) | 482 G1_REG_DEC_CTRL1_PIC_MB_H_EXT(mb_height >> 8); 483 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); 484 485 /* Boolean decoder */ 486 reg = G1_REG_DEC_CTRL2_BOOLEAN_RANGE(hdr->coder_state.range) 487 | G1_REG_DEC_CTRL2_BOOLEAN_VALUE(hdr->coder_state.value); 488 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); 489 490 reg = 0; 491 if (hdr->version != 3) 492 reg |= G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT; 493 if (hdr->version & 0x3) 494 reg |= G1_REG_DEC_CTRL4_BILIN_MC_E; 495 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); 496 497 cfg_lf(ctx, hdr); 498 cfg_qp(ctx, hdr); 499 cfg_parts(ctx, hdr); 500 cfg_tap(ctx, hdr); 501 502 vb2_dst = hantro_get_dst_buf(ctx); 503 cfg_ref(ctx, hdr, vb2_dst); 504 cfg_buffers(ctx, hdr, vb2_dst); 505 506 hantro_end_prepare_run(ctx); 507 508 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); 509 510 return 0; 511} 512