1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Hantro VPU codec driver
4 *
5 * Copyright 2018 Google LLC.
6 *	Tomasz Figa <tfiga@chromium.org>
7 */
8
9#ifndef HANTRO_G1_REGS_H_
10#define HANTRO_G1_REGS_H_
11
12#define G1_SWREG(nr)                 ((nr) * 4)
13
14/* Decoder registers. */
15#define G1_REG_INTERRUPT				0x004
16#define     G1_REG_INTERRUPT_DEC_PIC_INF		BIT(24)
17#define     G1_REG_INTERRUPT_DEC_TIMEOUT		BIT(18)
18#define     G1_REG_INTERRUPT_DEC_SLICE_INT		BIT(17)
19#define     G1_REG_INTERRUPT_DEC_ERROR_INT		BIT(16)
20#define     G1_REG_INTERRUPT_DEC_ASO_INT		BIT(15)
21#define     G1_REG_INTERRUPT_DEC_BUFFER_INT		BIT(14)
22#define     G1_REG_INTERRUPT_DEC_BUS_INT		BIT(13)
23#define     G1_REG_INTERRUPT_DEC_RDY_INT		BIT(12)
24#define     G1_REG_INTERRUPT_DEC_IRQ			BIT(8)
25#define     G1_REG_INTERRUPT_DEC_IRQ_DIS		BIT(4)
26#define     G1_REG_INTERRUPT_DEC_E			BIT(0)
27#define G1_REG_CONFIG					0x008
28#define     G1_REG_CONFIG_DEC_AXI_RD_ID(x)		(((x) & 0xff) << 24)
29#define     G1_REG_CONFIG_DEC_TIMEOUT_E			BIT(23)
30#define     G1_REG_CONFIG_DEC_STRSWAP32_E		BIT(22)
31#define     G1_REG_CONFIG_DEC_STRENDIAN_E		BIT(21)
32#define     G1_REG_CONFIG_DEC_INSWAP32_E		BIT(20)
33#define     G1_REG_CONFIG_DEC_OUTSWAP32_E		BIT(19)
34#define     G1_REG_CONFIG_DEC_DATA_DISC_E		BIT(18)
35#define     G1_REG_CONFIG_TILED_MODE_MSB		BIT(17)
36#define     G1_REG_CONFIG_DEC_OUT_TILED_E		BIT(17)
37#define     G1_REG_CONFIG_DEC_LATENCY(x)		(((x) & 0x3f) << 11)
38#define     G1_REG_CONFIG_DEC_CLK_GATE_E		BIT(10)
39#define     G1_REG_CONFIG_DEC_IN_ENDIAN			BIT(9)
40#define     G1_REG_CONFIG_DEC_OUT_ENDIAN		BIT(8)
41#define     G1_REG_CONFIG_PRIORITY_MODE(x)		(((x) & 0x7) << 5)
42#define     G1_REG_CONFIG_TILED_MODE_LSB		BIT(7)
43#define     G1_REG_CONFIG_DEC_ADV_PRE_DIS		BIT(6)
44#define     G1_REG_CONFIG_DEC_SCMD_DIS			BIT(5)
45#define     G1_REG_CONFIG_DEC_MAX_BURST(x)		(((x) & 0x1f) << 0)
46#define G1_REG_DEC_CTRL0				0x00c
47#define     G1_REG_DEC_CTRL0_DEC_MODE(x)		(((x) & 0xf) << 28)
48#define     G1_REG_DEC_CTRL0_RLC_MODE_E			BIT(27)
49#define     G1_REG_DEC_CTRL0_SKIP_MODE			BIT(26)
50#define     G1_REG_DEC_CTRL0_DIVX3_E			BIT(25)
51#define     G1_REG_DEC_CTRL0_PJPEG_E			BIT(24)
52#define     G1_REG_DEC_CTRL0_PIC_INTERLACE_E		BIT(23)
53#define     G1_REG_DEC_CTRL0_PIC_FIELDMODE_E		BIT(22)
54#define     G1_REG_DEC_CTRL0_PIC_B_E			BIT(21)
55#define     G1_REG_DEC_CTRL0_PIC_INTER_E		BIT(20)
56#define     G1_REG_DEC_CTRL0_PIC_TOPFIELD_E		BIT(19)
57#define     G1_REG_DEC_CTRL0_FWD_INTERLACE_E		BIT(18)
58#define     G1_REG_DEC_CTRL0_SORENSON_E			BIT(17)
59#define     G1_REG_DEC_CTRL0_REF_TOPFIELD_E		BIT(16)
60#define     G1_REG_DEC_CTRL0_DEC_OUT_DIS		BIT(15)
61#define     G1_REG_DEC_CTRL0_FILTERING_DIS		BIT(14)
62#define     G1_REG_DEC_CTRL0_WEBP_E			BIT(13)
63#define     G1_REG_DEC_CTRL0_MVC_E			BIT(13)
64#define     G1_REG_DEC_CTRL0_PIC_FIXED_QUANT		BIT(13)
65#define     G1_REG_DEC_CTRL0_WRITE_MVS_E		BIT(12)
66#define     G1_REG_DEC_CTRL0_REFTOPFIRST_E		BIT(11)
67#define     G1_REG_DEC_CTRL0_SEQ_MBAFF_E		BIT(10)
68#define     G1_REG_DEC_CTRL0_PICORD_COUNT_E		BIT(9)
69#define     G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E		BIT(8)
70#define     G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x)		(((x) & 0xff) << 0)
71/* Setting AXI ID to 0xff to get auto generated ID to avoid possible conflicts */
72#define     G1_REG_DEC_CTRL0_DEC_AXI_AUTO		G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0xff)
73#define G1_REG_DEC_CTRL1				0x010
74#define     G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x)		(((x) & 0x1ff) << 23)
75#define     G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x)		(((x) & 0xf) << 19)
76#define     G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x)		(((x) & 0xff) << 11)
77#define     G1_REG_DEC_CTRL1_MB_HEIGHT_OFF(x)		(((x) & 0xf) << 7)
78#define     G1_REG_DEC_CTRL1_ALT_SCAN_E			BIT(6)
79#define     G1_REG_DEC_CTRL1_TOPFIELDFIRST_E		BIT(5)
80#define     G1_REG_DEC_CTRL1_REF_FRAMES(x)		(((x) & 0x1f) << 0)
81#define     G1_REG_DEC_CTRL1_PIC_MB_W_EXT(x)		(((x) & 0x7) << 3)
82#define     G1_REG_DEC_CTRL1_PIC_MB_H_EXT(x)		(((x) & 0x7) << 0)
83#define     G1_REG_DEC_CTRL1_PIC_REFER_FLAG		BIT(0)
84#define G1_REG_DEC_CTRL2				0x014
85#define     G1_REG_DEC_CTRL2_STRM_START_BIT(x)		(((x) & 0x3f) << 26)
86#define     G1_REG_DEC_CTRL2_SYNC_MARKER_E		BIT(25)
87#define     G1_REG_DEC_CTRL2_TYPE1_QUANT_E		BIT(24)
88#define     G1_REG_DEC_CTRL2_CH_QP_OFFSET(x)		(((x) & 0x1f) << 19)
89#define     G1_REG_DEC_CTRL2_CH_QP_OFFSET2(x)		(((x) & 0x1f) << 14)
90#define     G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E		BIT(0)
91#define     G1_REG_DEC_CTRL2_INTRADC_VLC_THR(x)		(((x) & 0x7) << 16)
92#define     G1_REG_DEC_CTRL2_VOP_TIME_INCR(x)		(((x) & 0xffff) << 0)
93#define     G1_REG_DEC_CTRL2_DQ_PROFILE			BIT(24)
94#define     G1_REG_DEC_CTRL2_DQBI_LEVEL			BIT(23)
95#define     G1_REG_DEC_CTRL2_RANGE_RED_FRM_E		BIT(22)
96#define     G1_REG_DEC_CTRL2_FAST_UVMC_E		BIT(20)
97#define     G1_REG_DEC_CTRL2_TRANSDCTAB			BIT(17)
98#define     G1_REG_DEC_CTRL2_TRANSACFRM(x)		(((x) & 0x3) << 15)
99#define     G1_REG_DEC_CTRL2_TRANSACFRM2(x)		(((x) & 0x3) << 13)
100#define     G1_REG_DEC_CTRL2_MB_MODE_TAB(x)		(((x) & 0x7) << 10)
101#define     G1_REG_DEC_CTRL2_MVTAB(x)			(((x) & 0x7) << 7)
102#define     G1_REG_DEC_CTRL2_CBPTAB(x)			(((x) & 0x7) << 4)
103#define     G1_REG_DEC_CTRL2_2MV_BLK_PAT_TAB(x)		(((x) & 0x3) << 2)
104#define     G1_REG_DEC_CTRL2_4MV_BLK_PAT_TAB(x)		(((x) & 0x3) << 0)
105#define     G1_REG_DEC_CTRL2_QSCALE_TYPE		BIT(24)
106#define     G1_REG_DEC_CTRL2_CON_MV_E			BIT(4)
107#define     G1_REG_DEC_CTRL2_INTRA_DC_PREC(x)		(((x) & 0x3) << 2)
108#define     G1_REG_DEC_CTRL2_INTRA_VLC_TAB		BIT(1)
109#define     G1_REG_DEC_CTRL2_FRAME_PRED_DCT		BIT(0)
110#define     G1_REG_DEC_CTRL2_JPEG_QTABLES(x)		(((x) & 0x3) << 11)
111#define     G1_REG_DEC_CTRL2_JPEG_MODE(x)		(((x) & 0x7) << 8)
112#define     G1_REG_DEC_CTRL2_JPEG_FILRIGHT_E		BIT(7)
113#define     G1_REG_DEC_CTRL2_JPEG_STREAM_ALL		BIT(6)
114#define     G1_REG_DEC_CTRL2_CR_AC_VLCTABLE		BIT(5)
115#define     G1_REG_DEC_CTRL2_CB_AC_VLCTABLE		BIT(4)
116#define     G1_REG_DEC_CTRL2_CR_DC_VLCTABLE		BIT(3)
117#define     G1_REG_DEC_CTRL2_CB_DC_VLCTABLE		BIT(2)
118#define     G1_REG_DEC_CTRL2_CR_DC_VLCTABLE3		BIT(1)
119#define     G1_REG_DEC_CTRL2_CB_DC_VLCTABLE3		BIT(0)
120#define     G1_REG_DEC_CTRL2_STRM1_START_BIT(x)		(((x) & 0x3f) << 18)
121#define     G1_REG_DEC_CTRL2_HUFFMAN_E			BIT(17)
122#define     G1_REG_DEC_CTRL2_MULTISTREAM_E		BIT(16)
123#define     G1_REG_DEC_CTRL2_BOOLEAN_VALUE(x)		(((x) & 0xff) << 8)
124#define     G1_REG_DEC_CTRL2_BOOLEAN_RANGE(x)		(((x) & 0xff) << 0)
125#define     G1_REG_DEC_CTRL2_ALPHA_OFFSET(x)		(((x) & 0x1f) << 5)
126#define     G1_REG_DEC_CTRL2_BETA_OFFSET(x)		(((x) & 0x1f) << 0)
127#define G1_REG_DEC_CTRL3				0x018
128#define     G1_REG_DEC_CTRL3_START_CODE_E		BIT(31)
129#define     G1_REG_DEC_CTRL3_INIT_QP(x)			(((x) & 0x3f) << 25)
130#define     G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E		BIT(24)
131#define     G1_REG_DEC_CTRL3_STREAM_LEN_EXT(x)		(((x) & 0xff) << 24)
132#define     G1_REG_DEC_CTRL3_STREAM_LEN(x)		(((x) & 0xffffff) << 0)
133#define G1_REG_DEC_CTRL4				0x01c
134#define     G1_REG_DEC_CTRL4_CABAC_E			BIT(31)
135#define     G1_REG_DEC_CTRL4_BLACKWHITE_E		BIT(30)
136#define     G1_REG_DEC_CTRL4_DIR_8X8_INFER_E		BIT(29)
137#define     G1_REG_DEC_CTRL4_WEIGHT_PRED_E		BIT(28)
138#define     G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x)		(((x) & 0x3) << 26)
139#define     G1_REG_DEC_CTRL4_AVS_H264_H_EXT		BIT(25)
140#define     G1_REG_DEC_CTRL4_FRAMENUM_LEN(x)		(((x) & 0x1f) << 16)
141#define     G1_REG_DEC_CTRL4_FRAMENUM(x)		(((x) & 0xffff) << 0)
142#define     G1_REG_DEC_CTRL4_BITPLANE0_E		BIT(31)
143#define     G1_REG_DEC_CTRL4_BITPLANE1_E		BIT(30)
144#define     G1_REG_DEC_CTRL4_BITPLANE2_E		BIT(29)
145#define     G1_REG_DEC_CTRL4_ALT_PQUANT(x)		(((x) & 0x1f) << 24)
146#define     G1_REG_DEC_CTRL4_DQ_EDGES(x)		(((x) & 0xf) << 20)
147#define     G1_REG_DEC_CTRL4_TTMBF			BIT(19)
148#define     G1_REG_DEC_CTRL4_PQINDEX(x)			(((x) & 0x1f) << 14)
149#define     G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT		BIT(13)
150#define     G1_REG_DEC_CTRL4_BILIN_MC_E			BIT(12)
151#define     G1_REG_DEC_CTRL4_UNIQP_E			BIT(11)
152#define     G1_REG_DEC_CTRL4_HALFQP_E			BIT(10)
153#define     G1_REG_DEC_CTRL4_TTFRM(x)			(((x) & 0x3) << 8)
154#define     G1_REG_DEC_CTRL4_2ND_BYTE_EMUL_E		BIT(7)
155#define     G1_REG_DEC_CTRL4_DQUANT_E			BIT(6)
156#define     G1_REG_DEC_CTRL4_VC1_ADV_E			BIT(5)
157#define     G1_REG_DEC_CTRL4_PJPEG_FILDOWN_E		BIT(26)
158#define     G1_REG_DEC_CTRL4_PJPEG_WDIV8		BIT(25)
159#define     G1_REG_DEC_CTRL4_PJPEG_HDIV8		BIT(24)
160#define     G1_REG_DEC_CTRL4_PJPEG_AH(x)		(((x) & 0xf) << 20)
161#define     G1_REG_DEC_CTRL4_PJPEG_AL(x)		(((x) & 0xf) << 16)
162#define     G1_REG_DEC_CTRL4_PJPEG_SS(x)		(((x) & 0xff) << 8)
163#define     G1_REG_DEC_CTRL4_PJPEG_SE(x)		(((x) & 0xff) << 0)
164#define     G1_REG_DEC_CTRL4_DCT1_START_BIT(x)		(((x) & 0x3f) << 26)
165#define     G1_REG_DEC_CTRL4_DCT2_START_BIT(x)		(((x) & 0x3f) << 20)
166#define     G1_REG_DEC_CTRL4_CH_MV_RES			BIT(13)
167#define     G1_REG_DEC_CTRL4_INIT_DC_MATCH0(x)		(((x) & 0x7) << 9)
168#define     G1_REG_DEC_CTRL4_INIT_DC_MATCH1(x)		(((x) & 0x7) << 6)
169#define     G1_REG_DEC_CTRL4_VP7_VERSION		BIT(5)
170#define G1_REG_DEC_CTRL5				0x020
171#define     G1_REG_DEC_CTRL5_CONST_INTRA_E		BIT(31)
172#define     G1_REG_DEC_CTRL5_FILT_CTRL_PRES		BIT(30)
173#define     G1_REG_DEC_CTRL5_RDPIC_CNT_PRES		BIT(29)
174#define     G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E		BIT(28)
175#define     G1_REG_DEC_CTRL5_REFPIC_MK_LEN(x)		(((x) & 0x7ff) << 17)
176#define     G1_REG_DEC_CTRL5_IDR_PIC_E			BIT(16)
177#define     G1_REG_DEC_CTRL5_IDR_PIC_ID(x)		(((x) & 0xffff) << 0)
178#define     G1_REG_DEC_CTRL5_MV_SCALEFACTOR(x)		(((x) & 0xff) << 24)
179#define     G1_REG_DEC_CTRL5_REF_DIST_FWD(x)		(((x) & 0x1f) << 19)
180#define     G1_REG_DEC_CTRL5_REF_DIST_BWD(x)		(((x) & 0x1f) << 14)
181#define     G1_REG_DEC_CTRL5_LOOP_FILT_LIMIT(x)		(((x) & 0xf) << 14)
182#define     G1_REG_DEC_CTRL5_VARIANCE_TEST_E		BIT(13)
183#define     G1_REG_DEC_CTRL5_MV_THRESHOLD(x)		(((x) & 0x7) << 10)
184#define     G1_REG_DEC_CTRL5_VAR_THRESHOLD(x)		(((x) & 0x3ff) << 0)
185#define     G1_REG_DEC_CTRL5_DIVX_IDCT_E		BIT(8)
186#define     G1_REG_DEC_CTRL5_DIVX3_SLICE_SIZE(x)	(((x) & 0xff) << 0)
187#define     G1_REG_DEC_CTRL5_PJPEG_REST_FREQ(x)		(((x) & 0xffff) << 0)
188#define     G1_REG_DEC_CTRL5_RV_PROFILE(x)		(((x) & 0x3) << 30)
189#define     G1_REG_DEC_CTRL5_RV_OSV_QUANT(x)		(((x) & 0x3) << 28)
190#define     G1_REG_DEC_CTRL5_RV_FWD_SCALE(x)		(((x) & 0x3fff) << 14)
191#define     G1_REG_DEC_CTRL5_RV_BWD_SCALE(x)		(((x) & 0x3fff) << 0)
192#define     G1_REG_DEC_CTRL5_INIT_DC_COMP0(x)		(((x) & 0xffff) << 16)
193#define     G1_REG_DEC_CTRL5_INIT_DC_COMP1(x)		(((x) & 0xffff) << 0)
194#define G1_REG_DEC_CTRL6				0x024
195#define     G1_REG_DEC_CTRL6_PPS_ID(x)			(((x) & 0xff) << 24)
196#define     G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(x)		(((x) & 0x1f) << 19)
197#define     G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(x)		(((x) & 0x1f) << 14)
198#define     G1_REG_DEC_CTRL6_POC_LENGTH(x)		(((x) & 0xff) << 0)
199#define     G1_REG_DEC_CTRL6_ICOMP0_E			BIT(24)
200#define     G1_REG_DEC_CTRL6_ISCALE0(x)			(((x) & 0xff) << 16)
201#define     G1_REG_DEC_CTRL6_ISHIFT0(x)			(((x) & 0xffff) << 0)
202#define     G1_REG_DEC_CTRL6_STREAM1_LEN(x)		(((x) & 0xffffff) << 0)
203#define     G1_REG_DEC_CTRL6_PIC_SLICE_AM(x)		(((x) & 0x1fff) << 0)
204#define     G1_REG_DEC_CTRL6_COEFFS_PART_AM(x)		(((x) & 0xf) << 24)
205#define G1_REG_FWD_PIC(i)				(0x028 + ((i) * 0x4))
206#define     G1_REG_FWD_PIC_PINIT_RLIST_F5(x)		(((x) & 0x1f) << 25)
207#define     G1_REG_FWD_PIC_PINIT_RLIST_F4(x)		(((x) & 0x1f) << 20)
208#define     G1_REG_FWD_PIC_PINIT_RLIST_F3(x)		(((x) & 0x1f) << 15)
209#define     G1_REG_FWD_PIC_PINIT_RLIST_F2(x)		(((x) & 0x1f) << 10)
210#define     G1_REG_FWD_PIC_PINIT_RLIST_F1(x)		(((x) & 0x1f) << 5)
211#define     G1_REG_FWD_PIC_PINIT_RLIST_F0(x)		(((x) & 0x1f) << 0)
212#define     G1_REG_FWD_PIC1_ICOMP1_E			BIT(24)
213#define     G1_REG_FWD_PIC1_ISCALE1(x)			(((x) & 0xff) << 16)
214#define     G1_REG_FWD_PIC1_ISHIFT1(x)			(((x) & 0xffff) << 0)
215#define     G1_REG_FWD_PIC1_SEGMENT_BASE(x)		((x) << 0)
216#define     G1_REG_FWD_PIC1_SEGMENT_UPD_E		BIT(1)
217#define     G1_REG_FWD_PIC1_SEGMENT_E			BIT(0)
218#define G1_REG_DEC_CTRL7				0x02c
219#define     G1_REG_DEC_CTRL7_PINIT_RLIST_F15(x)		(((x) & 0x1f) << 25)
220#define     G1_REG_DEC_CTRL7_PINIT_RLIST_F14(x)		(((x) & 0x1f) << 20)
221#define     G1_REG_DEC_CTRL7_PINIT_RLIST_F13(x)		(((x) & 0x1f) << 15)
222#define     G1_REG_DEC_CTRL7_PINIT_RLIST_F12(x)		(((x) & 0x1f) << 10)
223#define     G1_REG_DEC_CTRL7_PINIT_RLIST_F11(x)		(((x) & 0x1f) << 5)
224#define     G1_REG_DEC_CTRL7_PINIT_RLIST_F10(x)		(((x) & 0x1f) << 0)
225#define     G1_REG_DEC_CTRL7_ICOMP2_E			BIT(24)
226#define     G1_REG_DEC_CTRL7_ISCALE2(x)			(((x) & 0xff) << 16)
227#define     G1_REG_DEC_CTRL7_ISHIFT2(x)			(((x) & 0xffff) << 0)
228#define     G1_REG_DEC_CTRL7_DCT3_START_BIT(x)		(((x) & 0x3f) << 24)
229#define     G1_REG_DEC_CTRL7_DCT4_START_BIT(x)		(((x) & 0x3f) << 18)
230#define     G1_REG_DEC_CTRL7_DCT5_START_BIT(x)		(((x) & 0x3f) << 12)
231#define     G1_REG_DEC_CTRL7_DCT6_START_BIT(x)		(((x) & 0x3f) << 6)
232#define     G1_REG_DEC_CTRL7_DCT7_START_BIT(x)		(((x) & 0x3f) << 0)
233#define G1_REG_ADDR_STR					0x030
234#define G1_REG_ADDR_DST					0x034
235#define G1_REG_ADDR_REF(i)				(0x038 + ((i) * 0x4))
236#define     G1_REG_ADDR_REF_FIELD_E			BIT(1)
237#define     G1_REG_ADDR_REF_TOPC_E			BIT(0)
238#define G1_REG_REF_PIC(i)				(0x078 + ((i) * 0x4))
239#define     G1_REG_REF_PIC_FILT_TYPE_E			BIT(31)
240#define     G1_REG_REF_PIC_FILT_SHARPNESS(x)		(((x) & 0x7) << 28)
241#define     G1_REG_REF_PIC_MB_ADJ_0(x)			(((x) & 0x7f) << 21)
242#define     G1_REG_REF_PIC_MB_ADJ_1(x)			(((x) & 0x7f) << 14)
243#define     G1_REG_REF_PIC_MB_ADJ_2(x)			(((x) & 0x7f) << 7)
244#define     G1_REG_REF_PIC_MB_ADJ_3(x)			(((x) & 0x7f) << 0)
245#define     G1_REG_REF_PIC_REFER1_NBR(x)		(((x) & 0xffff) << 16)
246#define     G1_REG_REF_PIC_REFER0_NBR(x)		(((x) & 0xffff) << 0)
247#define     G1_REG_REF_PIC_LF_LEVEL_0(x)		(((x) & 0x3f) << 18)
248#define     G1_REG_REF_PIC_LF_LEVEL_1(x)		(((x) & 0x3f) << 12)
249#define     G1_REG_REF_PIC_LF_LEVEL_2(x)		(((x) & 0x3f) << 6)
250#define     G1_REG_REF_PIC_LF_LEVEL_3(x)		(((x) & 0x3f) << 0)
251#define     G1_REG_REF_PIC_QUANT_DELTA_0(x)		(((x) & 0x1f) << 27)
252#define     G1_REG_REF_PIC_QUANT_DELTA_1(x)		(((x) & 0x1f) << 22)
253#define     G1_REG_REF_PIC_QUANT_0(x)			(((x) & 0x7ff) << 11)
254#define     G1_REG_REF_PIC_QUANT_1(x)			(((x) & 0x7ff) << 0)
255#define G1_REG_LT_REF					0x098
256#define G1_REG_VALID_REF				0x09c
257#define G1_REG_ADDR_QTABLE				0x0a0
258#define G1_REG_ADDR_DIR_MV				0x0a4
259#define G1_REG_BD_REF_PIC(i)				(0x0a8 + ((i) * 0x4))
260#define     G1_REG_BD_REF_PIC_BINIT_RLIST_B2(x)		(((x) & 0x1f) << 25)
261#define     G1_REG_BD_REF_PIC_BINIT_RLIST_F2(x)		(((x) & 0x1f) << 20)
262#define     G1_REG_BD_REF_PIC_BINIT_RLIST_B1(x)		(((x) & 0x1f) << 15)
263#define     G1_REG_BD_REF_PIC_BINIT_RLIST_F1(x)		(((x) & 0x1f) << 10)
264#define     G1_REG_BD_REF_PIC_BINIT_RLIST_B0(x)		(((x) & 0x1f) << 5)
265#define     G1_REG_BD_REF_PIC_BINIT_RLIST_F0(x)		(((x) & 0x1f) << 0)
266#define     G1_REG_BD_REF_PIC_PRED_TAP_2_M1(x)		(((x) & 0x3) << 10)
267#define     G1_REG_BD_REF_PIC_PRED_TAP_2_4(x)		(((x) & 0x3) << 8)
268#define     G1_REG_BD_REF_PIC_PRED_TAP_4_M1(x)		(((x) & 0x3) << 6)
269#define     G1_REG_BD_REF_PIC_PRED_TAP_4_4(x)		(((x) & 0x3) << 4)
270#define     G1_REG_BD_REF_PIC_PRED_TAP_6_M1(x)		(((x) & 0x3) << 2)
271#define     G1_REG_BD_REF_PIC_PRED_TAP_6_4(x)		(((x) & 0x3) << 0)
272#define     G1_REG_BD_REF_PIC_QUANT_DELTA_2(x)		(((x) & 0x1f) << 27)
273#define     G1_REG_BD_REF_PIC_QUANT_DELTA_3(x)		(((x) & 0x1f) << 22)
274#define     G1_REG_BD_REF_PIC_QUANT_2(x)		(((x) & 0x7ff) << 11)
275#define     G1_REG_BD_REF_PIC_QUANT_3(x)		(((x) & 0x7ff) << 0)
276#define G1_REG_BD_P_REF_PIC				0x0bc
277#define     G1_REG_BD_P_REF_PIC_QUANT_DELTA_4(x)	(((x) & 0x1f) << 27)
278#define     G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x)	(((x) & 0x1f) << 25)
279#define     G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x)	(((x) & 0x1f) << 20)
280#define     G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x)	(((x) & 0x1f) << 15)
281#define     G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x)	(((x) & 0x1f) << 10)
282#define     G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(x)	(((x) & 0x1f) << 5)
283#define     G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(x)	(((x) & 0x1f) << 0)
284#define G1_REG_ERR_CONC					0x0c0
285#define     G1_REG_ERR_CONC_STARTMB_X(x)		(((x) & 0x1ff) << 23)
286#define     G1_REG_ERR_CONC_STARTMB_Y(x)		(((x) & 0xff) << 15)
287#define G1_REG_PRED_FLT					0x0c4
288#define     G1_REG_PRED_FLT_PRED_BC_TAP_0_0(x)		(((x) & 0x3ff) << 22)
289#define     G1_REG_PRED_FLT_PRED_BC_TAP_0_1(x)		(((x) & 0x3ff) << 12)
290#define     G1_REG_PRED_FLT_PRED_BC_TAP_0_2(x)		(((x) & 0x3ff) << 2)
291#define G1_REG_REF_BUF_CTRL				0x0cc
292#define     G1_REG_REF_BUF_CTRL_REFBU_E			BIT(31)
293#define     G1_REG_REF_BUF_CTRL_REFBU_THR(x)		(((x) & 0xfff) << 19)
294#define     G1_REG_REF_BUF_CTRL_REFBU_PICID(x)		(((x) & 0x1f) << 14)
295#define     G1_REG_REF_BUF_CTRL_REFBU_EVAL_E		BIT(13)
296#define     G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E		BIT(12)
297#define     G1_REG_REF_BUF_CTRL_REFBU_Y_OFFSET(x)	(((x) & 0x1ff) << 0)
298#define G1_REG_REF_BUF_CTRL2				0x0dc
299#define     G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E		BIT(31)
300#define     G1_REG_REF_BUF_CTRL2_REFBU2_THR(x)		(((x) & 0xfff) << 19)
301#define     G1_REG_REF_BUF_CTRL2_REFBU2_PICID(x)	(((x) & 0x1f) << 14)
302#define     G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(x)	(((x) & 0x3fff) << 0)
303#define G1_REG_SOFT_RESET				0x194
304
305/* Post-processor registers. */
306#define G1_REG_PP_INTERRUPT		G1_SWREG(60)
307#define    G1_REG_PP_READY_IRQ		BIT(12)
308#define    G1_REG_PP_IRQ		BIT(8)
309#define    G1_REG_PP_IRQ_DIS		BIT(4)
310#define    G1_REG_PP_PIPELINE_EN	BIT(1)
311#define    G1_REG_PP_EXTERNAL_TRIGGER	BIT(0)
312#define G1_REG_PP_DEV_CONFIG		G1_SWREG(61)
313#define     G1_REG_PP_AXI_RD_ID(v)	(((v) << 24) & GENMASK(31, 24))
314#define     G1_REG_PP_AXI_WR_ID(v)	(((v) << 16) & GENMASK(23, 16))
315#define     G1_REG_PP_INSWAP32_E(v)	((v) ? BIT(10) : 0)
316#define     G1_REG_PP_DATA_DISC_E(v)	((v) ? BIT(9) : 0)
317#define     G1_REG_PP_CLK_GATE_E(v)	((v) ? BIT(8) : 0)
318#define     G1_REG_PP_IN_ENDIAN(v)	((v) ? BIT(7) : 0)
319#define     G1_REG_PP_OUT_ENDIAN(v)	((v) ? BIT(6) : 0)
320#define     G1_REG_PP_OUTSWAP32_E(v)	((v) ? BIT(5) : 0)
321#define     G1_REG_PP_MAX_BURST(v)	(((v) << 0) & GENMASK(4, 0))
322#define G1_REG_PP_IN_LUMA_BASE		G1_SWREG(63)
323#define G1_REG_PP_IN_CB_BASE		G1_SWREG(64)
324#define G1_REG_PP_IN_CR_BASE		G1_SWREG(65)
325#define G1_REG_PP_OUT_LUMA_BASE		G1_SWREG(66)
326#define G1_REG_PP_OUT_CHROMA_BASE	G1_SWREG(67)
327#define G1_REG_PP_CONTRAST_ADJUST	G1_SWREG(68)
328#define G1_REG_PP_COLOR_CONVERSION	G1_SWREG(69)
329#define G1_REG_PP_COLOR_CONVERSION0	G1_SWREG(70)
330#define G1_REG_PP_COLOR_CONVERSION1	G1_SWREG(71)
331#define G1_REG_PP_INPUT_SIZE		G1_SWREG(72)
332#define    G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9))
333#define    G1_REG_PP_INPUT_SIZE_WIDTH(v)  (((v) << 0) & GENMASK(8, 0))
334#define G1_REG_PP_SCALING0		G1_SWREG(79)
335#define     G1_REG_PP_PADD_R(v)	(((v) << 23) & GENMASK(27, 23))
336#define     G1_REG_PP_PADD_G(v)	(((v) << 18) & GENMASK(22, 18))
337#define     G1_REG_PP_RANGEMAP_Y(v) ((v) ? BIT(31) : 0)
338#define     G1_REG_PP_RANGEMAP_C(v) ((v) ? BIT(30) : 0)
339#define     G1_REG_PP_YCBCR_RANGE(v) ((v) ? BIT(29) : 0)
340#define     G1_REG_PP_RGB_16(v) ((v) ? BIT(28) : 0)
341#define G1_REG_PP_SCALING1		G1_SWREG(80)
342#define     G1_REG_PP_PADD_B(v)	(((v) << 18) & GENMASK(22, 18))
343#define G1_REG_PP_MASK_R		G1_SWREG(82)
344#define G1_REG_PP_MASK_G		G1_SWREG(83)
345#define G1_REG_PP_MASK_B		G1_SWREG(84)
346#define G1_REG_PP_CONTROL		G1_SWREG(85)
347#define     G1_REG_PP_CONTROL_IN_FMT(v)	(((v) << 29) & GENMASK(31, 29))
348#define     G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26))
349#define     G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15))
350#define     G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))
351#define G1_REG_PP_MASK1_ORIG_WIDTH	G1_SWREG(88)
352#define     G1_REG_PP_ORIG_WIDTH(v)	(((v) << 23) & GENMASK(31, 23))
353#define G1_REG_PP_DISPLAY_WIDTH		G1_SWREG(92)
354#define G1_REG_PP_FUSE			G1_SWREG(99)
355
356#endif /* HANTRO_G1_REGS_H_ */
357