1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Hantro VPU codec driver 4 * 5 * Copyright 2018 Google LLC. 6 * Tomasz Figa <tfiga@chromium.org> 7 * 8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. 9 * Copyright (C) 2011 Samsung Electronics Co., Ltd. 10 */ 11 12#ifndef HANTRO_H_ 13#define HANTRO_H_ 14 15#include <linux/platform_device.h> 16#include <linux/videodev2.h> 17#include <linux/wait.h> 18#include <linux/clk.h> 19#include <linux/reset.h> 20 21#include <media/v4l2-ctrls.h> 22#include <media/v4l2-device.h> 23#include <media/v4l2-ioctl.h> 24#include <media/v4l2-mem2mem.h> 25#include <media/videobuf2-core.h> 26#include <media/videobuf2-dma-contig.h> 27 28#include "hantro_hw.h" 29 30struct hantro_ctx; 31struct hantro_codec_ops; 32struct hantro_postproc_ops; 33 34#define HANTRO_JPEG_ENCODER BIT(0) 35#define HANTRO_ENCODERS 0x0000ffff 36#define HANTRO_MPEG2_DECODER BIT(16) 37#define HANTRO_VP8_DECODER BIT(17) 38#define HANTRO_H264_DECODER BIT(18) 39#define HANTRO_HEVC_DECODER BIT(19) 40#define HANTRO_VP9_DECODER BIT(20) 41#define HANTRO_AV1_DECODER BIT(21) 42#define HANTRO_DECODERS 0xffff0000 43 44/** 45 * struct hantro_irq - irq handler and name 46 * 47 * @name: irq name for device tree lookup 48 * @handler: interrupt handler 49 */ 50struct hantro_irq { 51 const char *name; 52 irqreturn_t (*handler)(int irq, void *priv); 53}; 54 55/** 56 * struct hantro_variant - information about VPU hardware variant 57 * 58 * @enc_offset: Offset from VPU base to encoder registers. 59 * @dec_offset: Offset from VPU base to decoder registers. 60 * @enc_fmts: Encoder formats. 61 * @num_enc_fmts: Number of encoder formats. 62 * @dec_fmts: Decoder formats. 63 * @num_dec_fmts: Number of decoder formats. 64 * @postproc_fmts: Post-processor formats. 65 * @num_postproc_fmts: Number of post-processor formats. 66 * @postproc_ops: Post-processor ops. 67 * @codec: Supported codecs 68 * @codec_ops: Codec ops. 69 * @init: Initialize hardware, optional. 70 * @runtime_resume: reenable hardware after power gating, optional. 71 * @irqs: array of irq names and interrupt handlers 72 * @num_irqs: number of irqs in the array 73 * @clk_names: array of clock names 74 * @num_clocks: number of clocks in the array 75 * @reg_names: array of register range names 76 * @num_regs: number of register range names in the array 77 * @double_buffer: core needs double buffering 78 * @legacy_regs: core uses legacy register set 79 * @late_postproc: postproc must be set up at the end of the job 80 */ 81struct hantro_variant { 82 unsigned int enc_offset; 83 unsigned int dec_offset; 84 const struct hantro_fmt *enc_fmts; 85 unsigned int num_enc_fmts; 86 const struct hantro_fmt *dec_fmts; 87 unsigned int num_dec_fmts; 88 const struct hantro_fmt *postproc_fmts; 89 unsigned int num_postproc_fmts; 90 const struct hantro_postproc_ops *postproc_ops; 91 unsigned int codec; 92 const struct hantro_codec_ops *codec_ops; 93 int (*init)(struct hantro_dev *vpu); 94 int (*runtime_resume)(struct hantro_dev *vpu); 95 const struct hantro_irq *irqs; 96 int num_irqs; 97 const char * const *clk_names; 98 int num_clocks; 99 const char * const *reg_names; 100 int num_regs; 101 unsigned int double_buffer : 1; 102 unsigned int legacy_regs : 1; 103 unsigned int late_postproc : 1; 104}; 105 106/** 107 * enum hantro_codec_mode - codec operating mode. 108 * @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats. 109 * @HANTRO_MODE_JPEG_ENC: JPEG encoder. 110 * @HANTRO_MODE_H264_DEC: H264 decoder. 111 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder. 112 * @HANTRO_MODE_VP8_DEC: VP8 decoder. 113 * @HANTRO_MODE_HEVC_DEC: HEVC decoder. 114 * @HANTRO_MODE_VP9_DEC: VP9 decoder. 115 * @HANTRO_MODE_AV1_DEC: AV1 decoder 116 */ 117enum hantro_codec_mode { 118 HANTRO_MODE_NONE = -1, 119 HANTRO_MODE_JPEG_ENC, 120 HANTRO_MODE_H264_DEC, 121 HANTRO_MODE_MPEG2_DEC, 122 HANTRO_MODE_VP8_DEC, 123 HANTRO_MODE_HEVC_DEC, 124 HANTRO_MODE_VP9_DEC, 125 HANTRO_MODE_AV1_DEC, 126}; 127 128/* 129 * struct hantro_ctrl - helper type to declare supported controls 130 * @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.) 131 * @cfg: control configuration 132 */ 133struct hantro_ctrl { 134 unsigned int codec; 135 struct v4l2_ctrl_config cfg; 136}; 137 138/* 139 * struct hantro_func - Hantro VPU functionality 140 * 141 * @id: processing functionality ID (can be 142 * %MEDIA_ENT_F_PROC_VIDEO_ENCODER or 143 * %MEDIA_ENT_F_PROC_VIDEO_DECODER) 144 * @vdev: &struct video_device that exposes the encoder or 145 * decoder functionality 146 * @source_pad: &struct media_pad with the source pad. 147 * @sink: &struct media_entity pointer with the sink entity 148 * @sink_pad: &struct media_pad with the sink pad. 149 * @proc: &struct media_entity pointer with the M2M device itself. 150 * @proc_pads: &struct media_pad with the @proc pads. 151 * @intf_devnode: &struct media_intf devnode pointer with the interface 152 * with controls the M2M device. 153 * 154 * Contains everything needed to attach the video device to the media device. 155 */ 156struct hantro_func { 157 unsigned int id; 158 struct video_device vdev; 159 struct media_pad source_pad; 160 struct media_entity sink; 161 struct media_pad sink_pad; 162 struct media_entity proc; 163 struct media_pad proc_pads[2]; 164 struct media_intf_devnode *intf_devnode; 165}; 166 167static inline struct hantro_func * 168hantro_vdev_to_func(struct video_device *vdev) 169{ 170 return container_of(vdev, struct hantro_func, vdev); 171} 172 173/** 174 * struct hantro_dev - driver data 175 * @v4l2_dev: V4L2 device to register video devices for. 176 * @m2m_dev: mem2mem device associated to this device. 177 * @mdev: media device associated to this device. 178 * @encoder: encoder functionality. 179 * @decoder: decoder functionality. 180 * @pdev: Pointer to VPU platform device. 181 * @dev: Pointer to device for convenient logging using 182 * dev_ macros. 183 * @clocks: Array of clock handles. 184 * @resets: Array of reset handles. 185 * @reg_bases: Mapped addresses of VPU registers. 186 * @enc_base: Mapped address of VPU encoder register for convenience. 187 * @dec_base: Mapped address of VPU decoder register for convenience. 188 * @ctrl_base: Mapped address of VPU control block. 189 * @vpu_mutex: Mutex to synchronize V4L2 calls. 190 * @irqlock: Spinlock to synchronize access to data structures 191 * shared with interrupt handlers. 192 * @variant: Hardware variant-specific parameters. 193 * @watchdog_work: Delayed work for hardware timeout handling. 194 */ 195struct hantro_dev { 196 struct v4l2_device v4l2_dev; 197 struct v4l2_m2m_dev *m2m_dev; 198 struct media_device mdev; 199 struct hantro_func *encoder; 200 struct hantro_func *decoder; 201 struct platform_device *pdev; 202 struct device *dev; 203 struct clk_bulk_data *clocks; 204 struct reset_control *resets; 205 void __iomem **reg_bases; 206 void __iomem *enc_base; 207 void __iomem *dec_base; 208 void __iomem *ctrl_base; 209 210 struct mutex vpu_mutex; /* video_device lock */ 211 spinlock_t irqlock; 212 const struct hantro_variant *variant; 213 struct delayed_work watchdog_work; 214}; 215 216/** 217 * struct hantro_ctx - Context (instance) private data. 218 * 219 * @dev: VPU driver data to which the context belongs. 220 * @fh: V4L2 file handler. 221 * @is_encoder: Decoder or encoder context? 222 * 223 * @sequence_cap: Sequence counter for capture queue 224 * @sequence_out: Sequence counter for output queue 225 * 226 * @vpu_src_fmt: Descriptor of active source format. 227 * @src_fmt: V4L2 pixel format of active source format. 228 * @vpu_dst_fmt: Descriptor of active destination format. 229 * @dst_fmt: V4L2 pixel format of active destination format. 230 * 231 * @ctrl_handler: Control handler used to register controls. 232 * @jpeg_quality: User-specified JPEG compression quality. 233 * @bit_depth: Bit depth of current frame 234 * @need_postproc: Set to true if the bitstream features require to 235 * use the post-processor. 236 * 237 * @codec_ops: Set of operations related to codec mode. 238 * @postproc: Post-processing context. 239 * @h264_dec: H.264-decoding context. 240 * @mpeg2_dec: MPEG-2-decoding context. 241 * @vp8_dec: VP8-decoding context. 242 * @hevc_dec: HEVC-decoding context. 243 * @vp9_dec: VP9-decoding context. 244 * @av1_dec: AV1-decoding context. 245 */ 246struct hantro_ctx { 247 struct hantro_dev *dev; 248 struct v4l2_fh fh; 249 bool is_encoder; 250 251 u32 sequence_cap; 252 u32 sequence_out; 253 254 const struct hantro_fmt *vpu_src_fmt; 255 struct v4l2_pix_format_mplane src_fmt; 256 const struct hantro_fmt *vpu_dst_fmt; 257 struct v4l2_pix_format_mplane dst_fmt; 258 259 struct v4l2_ctrl_handler ctrl_handler; 260 int jpeg_quality; 261 int bit_depth; 262 263 const struct hantro_codec_ops *codec_ops; 264 struct hantro_postproc_ctx postproc; 265 bool need_postproc; 266 267 /* Specific for particular codec modes. */ 268 union { 269 struct hantro_h264_dec_hw_ctx h264_dec; 270 struct hantro_mpeg2_dec_hw_ctx mpeg2_dec; 271 struct hantro_vp8_dec_hw_ctx vp8_dec; 272 struct hantro_hevc_dec_hw_ctx hevc_dec; 273 struct hantro_vp9_dec_hw_ctx vp9_dec; 274 struct hantro_av1_dec_hw_ctx av1_dec; 275 }; 276}; 277 278/** 279 * struct hantro_fmt - information about supported video formats. 280 * @name: Human readable name of the format. 281 * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*. 282 * @codec_mode: Codec mode related to this format. See 283 * enum hantro_codec_mode. 284 * @header_size: Optional header size. Currently used by JPEG encoder. 285 * @max_depth: Maximum depth, for bitstream formats 286 * @enc_fmt: Format identifier for encoder registers. 287 * @frmsize: Supported range of frame sizes (only for bitstream formats). 288 * @postprocessed: Indicates if this format needs the post-processor. 289 * @match_depth: Indicates if format bit depth must match video bit depth 290 */ 291struct hantro_fmt { 292 char *name; 293 u32 fourcc; 294 enum hantro_codec_mode codec_mode; 295 int header_size; 296 int max_depth; 297 enum hantro_enc_fmt enc_fmt; 298 struct v4l2_frmsize_stepwise frmsize; 299 bool postprocessed; 300 bool match_depth; 301}; 302 303struct hantro_reg { 304 u32 base; 305 u32 shift; 306 u32 mask; 307}; 308 309struct hantro_postproc_regs { 310 struct hantro_reg pipeline_en; 311 struct hantro_reg max_burst; 312 struct hantro_reg clk_gate; 313 struct hantro_reg out_swap32; 314 struct hantro_reg out_endian; 315 struct hantro_reg out_luma_base; 316 struct hantro_reg input_width; 317 struct hantro_reg input_height; 318 struct hantro_reg output_width; 319 struct hantro_reg output_height; 320 struct hantro_reg input_fmt; 321 struct hantro_reg output_fmt; 322 struct hantro_reg orig_width; 323 struct hantro_reg display_width; 324}; 325 326struct hantro_vp9_decoded_buffer_info { 327 /* Info needed when the decoded frame serves as a reference frame. */ 328 unsigned short width; 329 unsigned short height; 330 size_t chroma_offset; 331 size_t mv_offset; 332 u32 bit_depth : 4; 333}; 334 335struct hantro_decoded_buffer { 336 /* Must be the first field in this struct. */ 337 struct v4l2_m2m_buffer base; 338 339 union { 340 struct hantro_vp9_decoded_buffer_info vp9; 341 }; 342}; 343 344/* Logging helpers */ 345 346/** 347 * DOC: hantro_debug: Module parameter to control level of debugging messages. 348 * 349 * Level of debugging messages can be controlled by bits of 350 * module parameter called "debug". Meaning of particular 351 * bits is as follows: 352 * 353 * bit 0 - global information: mode, size, init, release 354 * bit 1 - each run start/result information 355 * bit 2 - contents of small controls from userspace 356 * bit 3 - contents of big controls from userspace 357 * bit 4 - detail fmt, ctrl, buffer q/dq information 358 * bit 5 - detail function enter/leave trace information 359 * bit 6 - register write/read information 360 */ 361extern int hantro_debug; 362 363#define vpu_debug(level, fmt, args...) \ 364 do { \ 365 if (hantro_debug & BIT(level)) \ 366 pr_info("%s:%d: " fmt, \ 367 __func__, __LINE__, ##args); \ 368 } while (0) 369 370#define vpu_err(fmt, args...) \ 371 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args) 372 373/* Structure access helpers. */ 374static __always_inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh) 375{ 376 return container_of(fh, struct hantro_ctx, fh); 377} 378 379/* Register accessors. */ 380static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu, 381 u32 val, u32 reg) 382{ 383 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 384 writel_relaxed(val, vpu->enc_base + reg); 385} 386 387static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) 388{ 389 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 390 writel(val, vpu->enc_base + reg); 391} 392 393static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg) 394{ 395 u32 val = readl(vpu->enc_base + reg); 396 397 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 398 return val; 399} 400 401static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu, 402 u32 val, u32 reg) 403{ 404 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 405 writel_relaxed(val, vpu->dec_base + reg); 406} 407 408static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) 409{ 410 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 411 writel(val, vpu->dec_base + reg); 412} 413 414static __always_inline void hantro_write_addr(struct hantro_dev *vpu, 415 unsigned long offset, 416 dma_addr_t addr) 417{ 418 vdpu_write(vpu, addr & 0xffffffff, offset); 419} 420 421static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) 422{ 423 u32 val = readl(vpu->dec_base + reg); 424 425 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); 426 return val; 427} 428 429static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu, 430 const struct hantro_reg *reg, 431 u32 val) 432{ 433 u32 v; 434 435 v = vdpu_read(vpu, reg->base); 436 v &= ~(reg->mask << reg->shift); 437 v |= ((val & reg->mask) << reg->shift); 438 return v; 439} 440 441static __always_inline void hantro_reg_write(struct hantro_dev *vpu, 442 const struct hantro_reg *reg, 443 u32 val) 444{ 445 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); 446} 447 448static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu, 449 const struct hantro_reg *reg, 450 u32 val) 451{ 452 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base); 453} 454 455void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id); 456dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts); 457 458static inline struct vb2_v4l2_buffer * 459hantro_get_src_buf(struct hantro_ctx *ctx) 460{ 461 return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 462} 463 464static inline struct vb2_v4l2_buffer * 465hantro_get_dst_buf(struct hantro_ctx *ctx) 466{ 467 return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 468} 469 470bool hantro_needs_postproc(const struct hantro_ctx *ctx, 471 const struct hantro_fmt *fmt); 472 473dma_addr_t 474hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index); 475 476static inline dma_addr_t 477hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb) 478{ 479 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) 480 return hantro_postproc_get_dec_buf_addr(ctx, vb->index); 481 return vb2_dma_contig_plane_dma_addr(vb, 0); 482} 483 484static inline struct hantro_decoded_buffer * 485vb2_to_hantro_decoded_buf(struct vb2_buffer *buf) 486{ 487 return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf); 488} 489 490void hantro_postproc_disable(struct hantro_ctx *ctx); 491void hantro_postproc_enable(struct hantro_ctx *ctx); 492int hantro_postproc_init(struct hantro_ctx *ctx); 493void hantro_postproc_free(struct hantro_ctx *ctx); 494int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx, 495 struct v4l2_frmsizeenum *fsize); 496 497#endif /* HANTRO_H_ */ 498