1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020-2022 Bootlin
4 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
5 */
6
7#ifndef _SUN6I_MIPI_CSI2_REG_H_
8#define _SUN6I_MIPI_CSI2_REG_H_
9
10#define SUN6I_MIPI_CSI2_CTL_REG				0x0
11#define SUN6I_MIPI_CSI2_CTL_RESET_N			BIT(31)
12#define SUN6I_MIPI_CSI2_CTL_VERSION_EN			BIT(30)
13#define SUN6I_MIPI_CSI2_CTL_UNPK_EN			BIT(1)
14#define SUN6I_MIPI_CSI2_CTL_EN				BIT(0)
15
16#define SUN6I_MIPI_CSI2_CFG_REG				0x4
17#define SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(v)		((((v) - 1) << 8) & \
18							 GENMASK(9, 8))
19#define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v)		(((v) - 1) & GENMASK(1, 0))
20
21#define SUN6I_MIPI_CSI2_VCDT_RX_REG			0x8
22#define SUN6I_MIPI_CSI2_VCDT_RX_CH_VC(ch, vc)		(((vc) & GENMASK(1, 0)) << \
23							 ((ch) * 8 + 6))
24#define SUN6I_MIPI_CSI2_VCDT_RX_CH_DT(ch, t)		(((t) & GENMASK(5, 0)) << \
25							 ((ch) * 8))
26#define SUN6I_MIPI_CSI2_RX_PKT_NUM_REG			0xc
27
28#define SUN6I_MIPI_CSI2_VERSION_REG			0x3c
29
30#define SUN6I_MIPI_CSI2_CH_CFG_REG			0x40
31#define SUN6I_MIPI_CSI2_CH_INT_EN_REG			0x50
32#define SUN6I_MIPI_CSI2_CH_INT_EN_EOT_ERR		BIT(29)
33#define SUN6I_MIPI_CSI2_CH_INT_EN_CHKSUM_ERR		BIT(28)
34#define SUN6I_MIPI_CSI2_CH_INT_EN_ECC_WRN		BIT(27)
35#define SUN6I_MIPI_CSI2_CH_INT_EN_ECC_ERR		BIT(26)
36#define SUN6I_MIPI_CSI2_CH_INT_EN_LINE_SYNC_ERR		BIT(25)
37#define SUN6I_MIPI_CSI2_CH_INT_EN_FRAME_SYNC_ERR	BIT(24)
38#define SUN6I_MIPI_CSI2_CH_INT_EN_EMB_DATA		BIT(18)
39#define SUN6I_MIPI_CSI2_CH_INT_EN_PF			BIT(17)
40#define SUN6I_MIPI_CSI2_CH_INT_EN_PH_UPDATE		BIT(16)
41#define SUN6I_MIPI_CSI2_CH_INT_EN_LINE_START_SYNC	BIT(11)
42#define SUN6I_MIPI_CSI2_CH_INT_EN_LINE_END_SYNC		BIT(10)
43#define SUN6I_MIPI_CSI2_CH_INT_EN_FRAME_START_SYNC	BIT(9)
44#define SUN6I_MIPI_CSI2_CH_INT_EN_FRAME_END_SYNC	BIT(8)
45#define SUN6I_MIPI_CSI2_CH_INT_EN_FIFO_OVER		BIT(0)
46
47#define SUN6I_MIPI_CSI2_CH_INT_PD_REG			0x58
48#define SUN6I_MIPI_CSI2_CH_INT_PD_CLEAR			0xff
49#define SUN6I_MIPI_CSI2_CH_INT_PD_EOT_ERR		BIT(29)
50#define SUN6I_MIPI_CSI2_CH_INT_PD_CHKSUM_ERR		BIT(28)
51#define SUN6I_MIPI_CSI2_CH_INT_PD_ECC_WRN		BIT(27)
52#define SUN6I_MIPI_CSI2_CH_INT_PD_ECC_ERR		BIT(26)
53#define SUN6I_MIPI_CSI2_CH_INT_PD_LINE_SYNC_ERR		BIT(25)
54#define SUN6I_MIPI_CSI2_CH_INT_PD_FRAME_SYNC_ERR	BIT(24)
55#define SUN6I_MIPI_CSI2_CH_INT_PD_EMB_DATA		BIT(18)
56#define SUN6I_MIPI_CSI2_CH_INT_PD_PF			BIT(17)
57#define SUN6I_MIPI_CSI2_CH_INT_PD_PH_UPDATE		BIT(16)
58#define SUN6I_MIPI_CSI2_CH_INT_PD_LINE_START_SYNC	BIT(11)
59#define SUN6I_MIPI_CSI2_CH_INT_PD_LINE_END_SYNC		BIT(10)
60#define SUN6I_MIPI_CSI2_CH_INT_PD_FRAME_START_SYNC	BIT(9)
61#define SUN6I_MIPI_CSI2_CH_INT_PD_FRAME_END_SYNC	BIT(8)
62#define SUN6I_MIPI_CSI2_CH_INT_PD_FIFO_OVER		BIT(0)
63
64#define SUN6I_MIPI_CSI2_CH_DT_TRIGGER_REG		0x60
65#define SUN6I_MIPI_CSI2_CH_CUR_PH_REG			0x70
66#define SUN6I_MIPI_CSI2_CH_ECC_REG			0x74
67#define SUN6I_MIPI_CSI2_CH_CKS_REG			0x78
68#define SUN6I_MIPI_CSI2_CH_FRAME_NUM_REG		0x7c
69#define SUN6I_MIPI_CSI2_CH_LINE_NUM_REG			0x80
70
71#define SUN6I_MIPI_CSI2_CH_OFFSET			0x100
72
73#define SUN6I_MIPI_CSI2_CH_REG(reg, ch) \
74	(SUN6I_MIPI_CSI2_CH_OFFSET * (ch) + (reg))
75
76#endif
77