1// SPDX-License-Identifier: GPL-2.0 2/* 3 * camss-vfe-480.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v480 (SM8250) 6 * 7 * Copyright (C) 2020-2021 Linaro Ltd. 8 * Copyright (C) 2021 Jonathan Marek 9 */ 10 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/iopoll.h> 14 15#include "camss.h" 16#include "camss-vfe.h" 17 18#define VFE_HW_VERSION (0x00) 19 20#define VFE_GLOBAL_RESET_CMD (vfe_is_lite(vfe) ? 0x0c : 0x1c) 21#define GLOBAL_RESET_HW_AND_REG (vfe_is_lite(vfe) ? BIT(1) : BIT(0)) 22 23#define VFE_REG_UPDATE_CMD (vfe_is_lite(vfe) ? 0x20 : 0x34) 24static inline int reg_update_rdi(struct vfe_device *vfe, int n) 25{ 26 return vfe_is_lite(vfe) ? BIT(n) : BIT(1 + (n)); 27} 28 29#define REG_UPDATE_RDI reg_update_rdi 30#define VFE_IRQ_CMD (vfe_is_lite(vfe) ? 0x24 : 0x38) 31#define IRQ_CMD_GLOBAL_CLEAR BIT(0) 32 33#define VFE_IRQ_MASK(n) ((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4) 34#define IRQ_MASK_0_RESET_ACK (vfe_is_lite(vfe) ? BIT(17) : BIT(0)) 35#define IRQ_MASK_0_BUS_TOP_IRQ (vfe_is_lite(vfe) ? BIT(4) : BIT(7)) 36#define VFE_IRQ_CLEAR(n) ((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4) 37#define VFE_IRQ_STATUS(n) ((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4) 38 39#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x1a00 : 0xaa00) 40 41#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) 42#define WM_CGC_OVERRIDE_ALL (0x3FFFFFF) 43 44#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xdc) 45 46#define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) 47static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n) 48{ 49 return vfe_is_lite(vfe) ? BIT(n) : BIT(3 + (n)); 50} 51 52#define BUS_IRQ_MASK_0_RDI_RUP bus_irq_mask_0_rdi_rup 53static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) 54{ 55 return vfe_is_lite(vfe) ? BIT(4 + (n)) : BIT(6 + (n)); 56} 57 58#define BUS_IRQ_MASK_0_COMP_DONE bus_irq_mask_0_comp_done 59#define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) 60#define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) 61#define VFE_BUS_IRQ_CLEAR_GLOBAL (BUS_REG_BASE + 0x30) 62 63#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) 64#define WM_CFG_EN (0) 65#define WM_CFG_MODE (16) 66#define MODE_QCOM_PLAIN (0) 67#define MODE_MIPI_RAW (1) 68#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) 69#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) 70#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) 71#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) 72#define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100) 73#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) 74#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) 75#define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100) 76#define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100) 77#define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100) 78 79#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) 80#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) 81#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) 82#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) 83 84#define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) 85#define VFE_BUS_WM_BURST_LIMIT(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) 86 87/* for titan 480, each bus client is hardcoded to a specific path 88 * and each bus client is part of a hardcoded "comp group" 89 */ 90#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0 : 23) + (n)) 91#define RDI_COMP_GROUP(n) ((vfe_is_lite(vfe) ? 0 : 11) + (n)) 92 93#define MAX_VFE_OUTPUT_LINES 4 94 95static u32 vfe_hw_version(struct vfe_device *vfe) 96{ 97 u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); 98 99 u32 gen = (hw_version >> 28) & 0xF; 100 u32 rev = (hw_version >> 16) & 0xFFF; 101 u32 step = hw_version & 0xFFFF; 102 103 dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step); 104 105 return hw_version; 106} 107 108static void vfe_global_reset(struct vfe_device *vfe) 109{ 110 writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); 111 writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); 112} 113 114static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) 115{ 116 struct v4l2_pix_format_mplane *pix = 117 &line->video_out.active_fmt.fmt.pix_mp; 118 119 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ 120 121 /* no clock gating at bus input */ 122 writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); 123 124 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); 125 126 writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height, 127 vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); 128 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); 129 writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH, 130 vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); 131 writel_relaxed(pix->plane_fmt[0].bytesperline, 132 vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); 133 writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); 134 135 /* no dropped frames, one irq per frame */ 136 writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); 137 writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); 138 writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); 139 writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); 140 141 writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE, 142 vfe->base + VFE_BUS_WM_CFG(wm)); 143} 144 145static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) 146{ 147 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ 148 writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm)); 149} 150 151static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, 152 struct vfe_line *line) 153{ 154 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ 155 writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); 156} 157 158static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 159{ 160 vfe->reg_update |= REG_UPDATE_RDI(vfe, line_id); 161 writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD); 162} 163 164static inline void vfe_reg_update_clear(struct vfe_device *vfe, 165 enum vfe_line_id line_id) 166{ 167 vfe->reg_update &= ~REG_UPDATE_RDI(vfe, line_id); 168} 169 170static void vfe_enable_irq_common(struct vfe_device *vfe) 171{ 172 /* enable reset ack IRQ and top BUS status IRQ */ 173 writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, 174 vfe->base + VFE_IRQ_MASK(0)); 175} 176 177static void vfe_enable_lines_irq(struct vfe_device *vfe) 178{ 179 int i; 180 u32 bus_irq_mask = 0; 181 182 for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) { 183 /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */ 184 if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED || 185 vfe->line[i].output.state == VFE_OUTPUT_ON) { 186 bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i) 187 | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)); 188 } 189 } 190 191 writel_relaxed(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0)); 192} 193 194static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id); 195static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm); 196 197/* 198 * vfe_isr - VFE module interrupt handler 199 * @irq: Interrupt line 200 * @dev: VFE device 201 * 202 * Return IRQ_HANDLED on success 203 */ 204static irqreturn_t vfe_isr(int irq, void *dev) 205{ 206 struct vfe_device *vfe = dev; 207 u32 status; 208 int i; 209 210 status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0)); 211 writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0)); 212 writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD); 213 214 if (status & IRQ_MASK_0_RESET_ACK) 215 vfe_isr_reset_ack(vfe); 216 217 if (status & IRQ_MASK_0_BUS_TOP_IRQ) { 218 u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0)); 219 220 writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0)); 221 writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL); 222 223 /* Loop through all WMs IRQs */ 224 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) { 225 if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, i)) 226 vfe_isr_reg_update(vfe, i); 227 228 if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i))) 229 vfe_isr_wm_done(vfe, i); 230 } 231 } 232 233 return IRQ_HANDLED; 234} 235 236/* 237 * vfe_halt - Trigger halt on VFE module and wait to complete 238 * @vfe: VFE device 239 * 240 * Return 0 on success or a negative error code otherwise 241 */ 242static int vfe_halt(struct vfe_device *vfe) 243{ 244 /* rely on vfe_disable_output() to stop the VFE */ 245 return 0; 246} 247 248static int vfe_get_output(struct vfe_line *line) 249{ 250 struct vfe_device *vfe = to_vfe(line); 251 struct vfe_output *output; 252 unsigned long flags; 253 254 spin_lock_irqsave(&vfe->output_lock, flags); 255 256 output = &line->output; 257 if (output->state > VFE_OUTPUT_RESERVED) { 258 dev_err(vfe->camss->dev, "Output is running\n"); 259 goto error; 260 } 261 262 output->wm_num = 1; 263 264 /* Correspondence between VFE line number and WM number. 265 * line 0 -> RDI 0, line 1 -> RDI1, line 2 -> RDI2, line 3 -> PIX/RDI3 266 * Note this 1:1 mapping will not work for PIX streams. 267 */ 268 output->wm_idx[0] = line->id; 269 vfe->wm_output_map[line->id] = line->id; 270 271 output->drop_update_idx = 0; 272 273 spin_unlock_irqrestore(&vfe->output_lock, flags); 274 275 return 0; 276 277error: 278 spin_unlock_irqrestore(&vfe->output_lock, flags); 279 output->state = VFE_OUTPUT_OFF; 280 281 return -EINVAL; 282} 283 284static int vfe_enable_output(struct vfe_line *line) 285{ 286 struct vfe_device *vfe = to_vfe(line); 287 struct vfe_output *output = &line->output; 288 unsigned long flags; 289 unsigned int i; 290 291 spin_lock_irqsave(&vfe->output_lock, flags); 292 293 vfe_reg_update_clear(vfe, line->id); 294 295 if (output->state > VFE_OUTPUT_RESERVED) { 296 dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", 297 output->state); 298 spin_unlock_irqrestore(&vfe->output_lock, flags); 299 return -EINVAL; 300 } 301 302 WARN_ON(output->gen2.active_num); 303 304 output->state = VFE_OUTPUT_ON; 305 306 output->sequence = 0; 307 output->wait_reg_update = 0; 308 reinit_completion(&output->reg_update); 309 310 vfe_wm_start(vfe, output->wm_idx[0], line); 311 312 for (i = 0; i < 2; i++) { 313 output->buf[i] = vfe_buf_get_pending(output); 314 if (!output->buf[i]) 315 break; 316 output->gen2.active_num++; 317 vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); 318 } 319 320 vfe_reg_update(vfe, line->id); 321 322 spin_unlock_irqrestore(&vfe->output_lock, flags); 323 324 return 0; 325} 326 327/* 328 * vfe_enable - Enable streaming on VFE line 329 * @line: VFE line 330 * 331 * Return 0 on success or a negative error code otherwise 332 */ 333static int vfe_enable(struct vfe_line *line) 334{ 335 struct vfe_device *vfe = to_vfe(line); 336 int ret; 337 338 mutex_lock(&vfe->stream_lock); 339 340 if (!vfe->stream_count) 341 vfe_enable_irq_common(vfe); 342 343 vfe->stream_count++; 344 345 vfe_enable_lines_irq(vfe); 346 347 mutex_unlock(&vfe->stream_lock); 348 349 ret = vfe_get_output(line); 350 if (ret < 0) 351 goto error_get_output; 352 353 ret = vfe_enable_output(line); 354 if (ret < 0) 355 goto error_enable_output; 356 357 vfe->was_streaming = 1; 358 359 return 0; 360 361error_enable_output: 362 vfe_put_output(line); 363 364error_get_output: 365 mutex_lock(&vfe->stream_lock); 366 367 vfe->stream_count--; 368 369 mutex_unlock(&vfe->stream_lock); 370 371 return ret; 372} 373 374/* 375 * vfe_isr_reg_update - Process reg update interrupt 376 * @vfe: VFE Device 377 * @line_id: VFE line 378 */ 379static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 380{ 381 struct vfe_output *output; 382 unsigned long flags; 383 384 spin_lock_irqsave(&vfe->output_lock, flags); 385 vfe_reg_update_clear(vfe, line_id); 386 387 output = &vfe->line[line_id].output; 388 389 if (output->wait_reg_update) { 390 output->wait_reg_update = 0; 391 complete(&output->reg_update); 392 } 393 394 spin_unlock_irqrestore(&vfe->output_lock, flags); 395} 396 397/* 398 * vfe_isr_wm_done - Process write master done interrupt 399 * @vfe: VFE Device 400 * @wm: Write master id 401 */ 402static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) 403{ 404 struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]]; 405 struct camss_buffer *ready_buf; 406 struct vfe_output *output; 407 unsigned long flags; 408 u32 index; 409 u64 ts = ktime_get_ns(); 410 411 spin_lock_irqsave(&vfe->output_lock, flags); 412 413 if (vfe->wm_output_map[wm] == VFE_LINE_NONE) { 414 dev_err_ratelimited(vfe->camss->dev, 415 "Received wm done for unmapped index\n"); 416 goto out_unlock; 417 } 418 output = &vfe->line[vfe->wm_output_map[wm]].output; 419 420 ready_buf = output->buf[0]; 421 if (!ready_buf) { 422 dev_err_ratelimited(vfe->camss->dev, 423 "Missing ready buf %d!\n", output->state); 424 goto out_unlock; 425 } 426 427 ready_buf->vb.vb2_buf.timestamp = ts; 428 ready_buf->vb.sequence = output->sequence++; 429 430 index = 0; 431 output->buf[0] = output->buf[1]; 432 if (output->buf[0]) 433 index = 1; 434 435 output->buf[index] = vfe_buf_get_pending(output); 436 437 if (output->buf[index]) 438 vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line); 439 else 440 output->gen2.active_num--; 441 442 spin_unlock_irqrestore(&vfe->output_lock, flags); 443 444 vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 445 446 return; 447 448out_unlock: 449 spin_unlock_irqrestore(&vfe->output_lock, flags); 450} 451 452/* 453 * vfe_queue_buffer - Add empty buffer 454 * @vid: Video device structure 455 * @buf: Buffer to be enqueued 456 * 457 * Add an empty buffer - depending on the current number of buffers it will be 458 * put in pending buffer queue or directly given to the hardware to be filled. 459 * 460 * Return 0 on success or a negative error code otherwise 461 */ 462static int vfe_queue_buffer(struct camss_video *vid, 463 struct camss_buffer *buf) 464{ 465 struct vfe_line *line = container_of(vid, struct vfe_line, video_out); 466 struct vfe_device *vfe = to_vfe(line); 467 struct vfe_output *output; 468 unsigned long flags; 469 470 output = &line->output; 471 472 spin_lock_irqsave(&vfe->output_lock, flags); 473 474 if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) { 475 output->buf[output->gen2.active_num++] = buf; 476 vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line); 477 } else { 478 vfe_buf_add_pending(output, buf); 479 } 480 481 spin_unlock_irqrestore(&vfe->output_lock, flags); 482 483 return 0; 484} 485 486static const struct camss_video_ops vfe_video_ops_480 = { 487 .queue_buffer = vfe_queue_buffer, 488 .flush_buffers = vfe_flush_buffers, 489}; 490 491static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 492{ 493 vfe->video_ops = vfe_video_ops_480; 494} 495 496const struct vfe_hw_ops vfe_ops_480 = { 497 .global_reset = vfe_global_reset, 498 .hw_version = vfe_hw_version, 499 .isr = vfe_isr, 500 .pm_domain_off = vfe_pm_domain_off, 501 .pm_domain_on = vfe_pm_domain_on, 502 .subdev_init = vfe_subdev_init, 503 .vfe_disable = vfe_disable, 504 .vfe_enable = vfe_enable, 505 .vfe_halt = vfe_halt, 506 .vfe_wm_stop = vfe_wm_stop, 507}; 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