1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5 */ 6 7#ifndef __MTK_MDP3_COMP_H__ 8#define __MTK_MDP3_COMP_H__ 9 10#include "mtk-mdp3-cmdq.h" 11 12#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask, ...) \ 13 cmdq_pkt_write_mask(&((cmd)->pkt), id, \ 14 (base) + (ofst), (val), (mask), ##__VA_ARGS__) 15 16#define MM_REG_WRITE(cmd, id, base, ofst, val, mask, ...) \ 17do { \ 18 typeof(mask) (m) = (mask); \ 19 MM_REG_WRITE_MASK(cmd, id, base, ofst, val, \ 20 (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ 21 (0xffffffff) : (m), ##__VA_ARGS__); \ 22} while (0) 23 24#define MM_REG_WAIT(cmd, evt) \ 25do { \ 26 typeof(cmd) (c) = (cmd); \ 27 typeof(evt) (e) = (evt); \ 28 cmdq_pkt_wfe(&((c)->pkt), (e), true); \ 29} while (0) 30 31#define MM_REG_WAIT_NO_CLEAR(cmd, evt) \ 32do { \ 33 typeof(cmd) (c) = (cmd); \ 34 typeof(evt) (e) = (evt); \ 35 cmdq_pkt_wfe(&((c)->pkt), (e), false); \ 36} while (0) 37 38#define MM_REG_CLEAR(cmd, evt) \ 39do { \ 40 typeof(cmd) (c) = (cmd); \ 41 typeof(evt) (e) = (evt); \ 42 cmdq_pkt_clear_event(&((c)->pkt), (e)); \ 43} while (0) 44 45#define MM_REG_SET_EVENT(cmd, evt) \ 46do { \ 47 typeof(cmd) (c) = (cmd); \ 48 typeof(evt) (e) = (evt); \ 49 cmdq_pkt_set_event(&((c)->pkt), (e)); \ 50} while (0) 51 52#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask, ...) \ 53do { \ 54 typeof(_mask) (_m) = (_mask); \ 55 cmdq_pkt_poll_mask(&((cmd)->pkt), id, \ 56 (base) + (ofst), (val), (_m), ##__VA_ARGS__); \ 57} while (0) 58 59#define MM_REG_POLL(cmd, id, base, ofst, val, mask, ...) \ 60do { \ 61 typeof(mask) (m) = (mask); \ 62 MM_REG_POLL_MASK((cmd), id, base, ofst, val, \ 63 (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ 64 (0xffffffff) : (m), ##__VA_ARGS__); \ 65} while (0) 66 67enum mtk_mdp_comp_id { 68 MDP_COMP_NONE = -1, /* Invalid engine */ 69 70 /* ISP */ 71 MDP_COMP_WPEI = 0, 72 MDP_COMP_WPEO, /* 1 */ 73 MDP_COMP_WPEI2, /* 2 */ 74 MDP_COMP_WPEO2, /* 3 */ 75 MDP_COMP_ISP_IMGI, /* 4 */ 76 MDP_COMP_ISP_IMGO, /* 5 */ 77 MDP_COMP_ISP_IMG2O, /* 6 */ 78 79 /* IPU */ 80 MDP_COMP_IPUI, /* 7 */ 81 MDP_COMP_IPUO, /* 8 */ 82 83 /* MDP */ 84 MDP_COMP_CAMIN, /* 9 */ 85 MDP_COMP_CAMIN2, /* 10 */ 86 MDP_COMP_RDMA0, /* 11 */ 87 MDP_COMP_RDMA1, /* 12 */ 88 MDP_COMP_RDMA2, /* 13 */ 89 MDP_COMP_RDMA3, /* 14 */ 90 MDP_COMP_AAL0, /* 15 */ 91 MDP_COMP_AAL1, /* 16 */ 92 MDP_COMP_AAL2, /* 17 */ 93 MDP_COMP_AAL3, /* 18 */ 94 MDP_COMP_CCORR0, /* 19 */ 95 MDP_COMP_RSZ0, /* 20 */ 96 MDP_COMP_RSZ1, /* 21 */ 97 MDP_COMP_RSZ2, /* 22 */ 98 MDP_COMP_RSZ3, /* 23 */ 99 MDP_COMP_TDSHP0, /* 24 */ 100 MDP_COMP_TDSHP1, /* 25 */ 101 MDP_COMP_TDSHP2, /* 26 */ 102 MDP_COMP_TDSHP3, /* 27 */ 103 MDP_COMP_COLOR0, /* 28 */ 104 MDP_COMP_COLOR1, /* 29 */ 105 MDP_COMP_COLOR2, /* 30 */ 106 MDP_COMP_COLOR3, /* 31 */ 107 MDP_COMP_PATH0_SOUT, /* 32 */ 108 MDP_COMP_PATH1_SOUT, /* 33 */ 109 MDP_COMP_WROT0, /* 34 */ 110 MDP_COMP_WROT1, /* 35 */ 111 MDP_COMP_WROT2, /* 36 */ 112 MDP_COMP_WROT3, /* 37 */ 113 MDP_COMP_WDMA, /* 38 */ 114 MDP_COMP_SPLIT, /* 39 */ 115 MDP_COMP_SPLIT2, /* 40 */ 116 MDP_COMP_STITCH, /* 41 */ 117 MDP_COMP_FG0, /* 42 */ 118 MDP_COMP_FG1, /* 43 */ 119 MDP_COMP_FG2, /* 44 */ 120 MDP_COMP_FG3, /* 45 */ 121 MDP_COMP_TO_SVPP2MOUT, /* 46 */ 122 MDP_COMP_TO_SVPP3MOUT, /* 47 */ 123 MDP_COMP_TO_WARP0MOUT, /* 48 */ 124 MDP_COMP_TO_WARP1MOUT, /* 49 */ 125 MDP_COMP_VPP0_SOUT, /* 50 */ 126 MDP_COMP_VPP1_SOUT, /* 51 */ 127 MDP_COMP_PQ0_SOUT, /* 52 */ 128 MDP_COMP_PQ1_SOUT, /* 53 */ 129 MDP_COMP_HDR0, /* 54 */ 130 MDP_COMP_HDR1, /* 55 */ 131 MDP_COMP_HDR2, /* 56 */ 132 MDP_COMP_HDR3, /* 57 */ 133 MDP_COMP_OVL0, /* 58 */ 134 MDP_COMP_OVL1, /* 59 */ 135 MDP_COMP_PAD0, /* 60 */ 136 MDP_COMP_PAD1, /* 61 */ 137 MDP_COMP_PAD2, /* 62 */ 138 MDP_COMP_PAD3, /* 63 */ 139 MDP_COMP_TCC0, /* 64 */ 140 MDP_COMP_TCC1, /* 65 */ 141 MDP_COMP_MERGE2, /* 66 */ 142 MDP_COMP_MERGE3, /* 67 */ 143 MDP_COMP_VDO0DL0, /* 68 */ 144 MDP_COMP_VDO1DL0, /* 69 */ 145 MDP_COMP_VDO0DL1, /* 70 */ 146 MDP_COMP_VDO1DL1, /* 71 */ 147 148 MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */ 149}; 150 151enum mdp_comp_type { 152 MDP_COMP_TYPE_INVALID = 0, 153 154 MDP_COMP_TYPE_RDMA, 155 MDP_COMP_TYPE_RSZ, 156 MDP_COMP_TYPE_WROT, 157 MDP_COMP_TYPE_WDMA, 158 MDP_COMP_TYPE_PATH, 159 160 MDP_COMP_TYPE_TDSHP, 161 MDP_COMP_TYPE_COLOR, 162 MDP_COMP_TYPE_DRE, 163 MDP_COMP_TYPE_CCORR, 164 MDP_COMP_TYPE_AAL, 165 MDP_COMP_TYPE_TCC, 166 MDP_COMP_TYPE_HDR, 167 MDP_COMP_TYPE_SPLIT, 168 MDP_COMP_TYPE_STITCH, 169 MDP_COMP_TYPE_FG, 170 MDP_COMP_TYPE_OVL, 171 MDP_COMP_TYPE_PAD, 172 MDP_COMP_TYPE_MERGE, 173 174 MDP_COMP_TYPE_IMGI, 175 MDP_COMP_TYPE_WPEI, 176 MDP_COMP_TYPE_EXTO, /* External path */ 177 MDP_COMP_TYPE_DL_PATH, /* Direct-link path */ 178 MDP_COMP_TYPE_DUMMY, 179 180 MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */ 181}; 182 183#define MDP_GCE_NO_EVENT (-1) 184enum { 185 MDP_GCE_EVENT_SOF = 0, 186 MDP_GCE_EVENT_EOF = 1, 187 MDP_GCE_EVENT_MAX, 188}; 189 190struct mdp_comp_match { 191 enum mdp_comp_type type; 192 u32 alias_id; 193 s32 inner_id; 194 s32 subsys_id; 195}; 196 197/* Used to describe the item order in MDP property */ 198struct mdp_comp_info { 199 u32 clk_num; 200 u32 clk_ofst; 201 u32 dts_reg_ofst; 202}; 203 204struct mdp_comp_blend { 205 enum mtk_mdp_comp_id b_id; 206 bool aid_mod; 207 bool aid_clk; 208}; 209 210struct mdp_comp_data { 211 struct mdp_comp_match match; 212 struct mdp_comp_info info; 213 struct mdp_comp_blend blend; 214}; 215 216struct mdp_comp_ops; 217 218struct mdp_comp { 219 struct mdp_dev *mdp_dev; 220 void __iomem *regs; 221 phys_addr_t reg_base; 222 u8 subsys_id; 223 u8 clk_num; 224 struct clk **clks; 225 struct device *comp_dev; 226 enum mdp_comp_type type; 227 enum mtk_mdp_comp_id public_id; 228 s32 inner_id; 229 u32 alias_id; 230 s32 gce_event[MDP_GCE_EVENT_MAX]; 231 const struct mdp_comp_ops *ops; 232}; 233 234struct mdp_comp_ctx { 235 struct mdp_comp *comp; 236 const struct img_compparam *param; 237 const struct img_input *input; 238 const struct img_output *outputs[IMG_MAX_HW_OUTPUTS]; 239}; 240 241struct mdp_comp_ops { 242 s64 (*get_comp_flag)(const struct mdp_comp_ctx *ctx); 243 int (*init_comp)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd); 244 int (*config_frame)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, 245 const struct v4l2_rect *compose); 246 int (*config_subfrm)(struct mdp_comp_ctx *ctx, 247 struct mdp_cmdq_cmd *cmd, u32 index); 248 int (*wait_comp_event)(struct mdp_comp_ctx *ctx, 249 struct mdp_cmdq_cmd *cmd); 250 int (*advance_subfrm)(struct mdp_comp_ctx *ctx, 251 struct mdp_cmdq_cmd *cmd, u32 index); 252 int (*post_process)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd); 253}; 254 255struct mdp_dev; 256 257int mdp_comp_config(struct mdp_dev *mdp); 258void mdp_comp_destroy(struct mdp_dev *mdp); 259int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp); 260void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp); 261int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num); 262void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num); 263int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, 264 const struct img_compparam *param, 265 const struct img_ipi_frameparam *frame); 266 267#endif /* __MTK_MDP3_COMP_H__ */ 268