1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Driver for the Conexant CX23885 PCIe bridge 4 * 5 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 6 */ 7 8#ifndef _CX23885_REG_H_ 9#define _CX23885_REG_H_ 10 11/* 12Address Map 130x00000000 -> 0x00009000 TX SRAM (Fifos) 140x00010000 -> 0x00013c00 RX SRAM CMDS + CDT 15 16EACH CMDS struct is 0x80 bytes long 17 18DMAx_PTR1 = 0x03040 address of first cluster 19DMAx_PTR2 = 0x10600 address of the CDT 20DMAx_CNT1 = cluster size in (bytes >> 4) -1 21DMAx_CNT2 = total cdt size for all entries >> 3 22 23Cluster Descriptor entry = 4 DWORDS 24 DWORD 0 -> ptr to cluster 25 DWORD 1 Reserved 26 DWORD 2 Reserved 27 DWORD 3 Reserved 28 29Channel manager Data Structure entry = 20 DWORD 30 0 IntialProgramCounterLow 31 1 IntialProgramCounterHigh 32 2 ClusterDescriptorTableBase 33 3 ClusterDescriptorTableSize 34 4 InstructionQueueBase 35 5 InstructionQueueSize 36... Reserved 37 19 Reserved 38*/ 39 40/* Risc Instructions */ 41#define RISC_CNT_INC 0x00010000 42#define RISC_CNT_RESET 0x00030000 43#define RISC_IRQ1 0x01000000 44#define RISC_IRQ2 0x02000000 45#define RISC_EOL 0x04000000 46#define RISC_SOL 0x08000000 47#define RISC_WRITE 0x10000000 48#define RISC_SKIP 0x20000000 49#define RISC_JUMP 0x70000000 50#define RISC_SYNC 0x80000000 51#define RISC_RESYNC 0x80008000 52#define RISC_READ 0x90000000 53#define RISC_WRITERM 0xB0000000 54#define RISC_WRITECM 0xC0000000 55#define RISC_WRITECR 0xD0000000 56#define RISC_WRITEC 0x50000000 57#define RISC_READC 0xA0000000 58 59 60/* Audio and Video Core */ 61#define HOST_REG1 0x00000000 62#define HOST_REG2 0x00000001 63#define HOST_REG3 0x00000002 64 65/* Chip Configuration Registers */ 66#define CHIP_CTRL 0x00000100 67#define AFE_CTRL 0x00000104 68#define VID_PLL_INT_POST 0x00000108 69#define VID_PLL_FRAC 0x0000010C 70#define AUX_PLL_INT_POST 0x00000110 71#define AUX_PLL_FRAC 0x00000114 72#define SYS_PLL_INT_POST 0x00000118 73#define SYS_PLL_FRAC 0x0000011C 74#define PIN_CTRL 0x00000120 75#define AUD_IO_CTRL 0x00000124 76#define AUD_LOCK1 0x00000128 77#define AUD_LOCK2 0x0000012C 78#define POWER_CTRL 0x00000130 79#define AFE_DIAG_CTRL1 0x00000134 80#define AFE_DIAG_CTRL3 0x0000013C 81#define PLL_DIAG_CTRL 0x00000140 82#define AFE_CLK_OUT_CTRL 0x00000144 83#define DLL1_DIAG_CTRL 0x0000015C 84 85/* GPIO[23:19] Output Enable */ 86#define GPIO2_OUT_EN_REG 0x00000160 87/* GPIO[23:19] Data Registers */ 88#define GPIO2 0x00000164 89 90#define IFADC_CTRL 0x00000180 91 92/* Infrared Remote Registers */ 93#define IR_CNTRL_REG 0x00000200 94#define IR_TXCLK_REG 0x00000204 95#define IR_RXCLK_REG 0x00000208 96#define IR_CDUTY_REG 0x0000020C 97#define IR_STAT_REG 0x00000210 98#define IR_IRQEN_REG 0x00000214 99#define IR_FILTR_REG 0x00000218 100#define IR_FIFO_REG 0x0000023C 101 102/* Video Decoder Registers */ 103#define MODE_CTRL 0x00000400 104#define OUT_CTRL1 0x00000404 105#define OUT_CTRL2 0x00000408 106#define GEN_STAT 0x0000040C 107#define INT_STAT_MASK 0x00000410 108#define LUMA_CTRL 0x00000414 109#define HSCALE_CTRL 0x00000418 110#define VSCALE_CTRL 0x0000041C 111#define CHROMA_CTRL 0x00000420 112#define VBI_LINE_CTRL1 0x00000424 113#define VBI_LINE_CTRL2 0x00000428 114#define VBI_LINE_CTRL3 0x0000042C 115#define VBI_LINE_CTRL4 0x00000430 116#define VBI_LINE_CTRL5 0x00000434 117#define VBI_FC_CFG 0x00000438 118#define VBI_MISC_CFG1 0x0000043C 119#define VBI_MISC_CFG2 0x00000440 120#define VBI_PAY1 0x00000444 121#define VBI_PAY2 0x00000448 122#define VBI_CUST1_CFG1 0x0000044C 123#define VBI_CUST1_CFG2 0x00000450 124#define VBI_CUST1_CFG3 0x00000454 125#define VBI_CUST2_CFG1 0x00000458 126#define VBI_CUST2_CFG2 0x0000045C 127#define VBI_CUST2_CFG3 0x00000460 128#define VBI_CUST3_CFG1 0x00000464 129#define VBI_CUST3_CFG2 0x00000468 130#define VBI_CUST3_CFG3 0x0000046C 131#define HORIZ_TIM_CTRL 0x00000470 132#define VERT_TIM_CTRL 0x00000474 133#define SRC_COMB_CFG 0x00000478 134#define CHROMA_VBIOFF_CFG 0x0000047C 135#define FIELD_COUNT 0x00000480 136#define MISC_TIM_CTRL 0x00000484 137#define DFE_CTRL1 0x00000488 138#define DFE_CTRL2 0x0000048C 139#define DFE_CTRL3 0x00000490 140#define PLL_CTRL 0x00000494 141#define HTL_CTRL 0x00000498 142#define COMB_CTRL 0x0000049C 143#define CRUSH_CTRL 0x000004A0 144#define SOFT_RST_CTRL 0x000004A4 145#define CX885_VERSION 0x000004B4 146#define VBI_PASS_CTRL 0x000004BC 147 148/* Audio Decoder Registers */ 149/* 8051 Configuration */ 150#define DL_CTL 0x00000800 151#define STD_DET_STATUS 0x00000804 152#define STD_DET_CTL 0x00000808 153#define DW8051_INT 0x0000080C 154#define GENERAL_CTL 0x00000810 155#define AAGC_CTL 0x00000814 156#define DEMATRIX_CTL 0x000008CC 157#define PATH1_CTL1 0x000008D0 158#define PATH1_VOL_CTL 0x000008D4 159#define PATH1_EQ_CTL 0x000008D8 160#define PATH1_SC_CTL 0x000008DC 161#define PATH2_CTL1 0x000008E0 162#define PATH2_VOL_CTL 0x000008E4 163#define PATH2_EQ_CTL 0x000008E8 164#define PATH2_SC_CTL 0x000008EC 165 166/* Sample Rate Converter */ 167#define SRC_CTL 0x000008F0 168#define SRC_LF_COEF 0x000008F4 169#define SRC1_CTL 0x000008F8 170#define SRC2_CTL 0x000008FC 171#define SRC3_CTL 0x00000900 172#define SRC4_CTL 0x00000904 173#define SRC5_CTL 0x00000908 174#define SRC6_CTL 0x0000090C 175#define BAND_OUT_SEL 0x00000910 176#define I2S_N_CTL 0x00000914 177#define I2S_OUT_CTL 0x00000918 178#define AUTOCONFIG_REG 0x000009C4 179 180/* Audio ADC Registers */ 181#define DSM_CTRL1 0x00000000 182#define DSM_CTRL2 0x00000001 183#define CHP_EN_CTRL 0x00000002 184#define CHP_CLK_CTRL1 0x00000004 185#define CHP_CLK_CTRL2 0x00000005 186#define BG_REF_CTRL 0x00000006 187#define SD2_SW_CTRL1 0x00000008 188#define SD2_SW_CTRL2 0x00000009 189#define SD2_BIAS_CTRL 0x0000000A 190#define AMP_BIAS_CTRL 0x0000000C 191#define CH_PWR_CTRL1 0x0000000E 192#define FLD_CH_SEL (1 << 3) 193#define CH_PWR_CTRL2 0x0000000F 194#define DSM_STATUS1 0x00000010 195#define DSM_STATUS2 0x00000011 196#define DIG_CTL1 0x00000012 197#define DIG_CTL2 0x00000013 198#define I2S_TX_CFG 0x0000001A 199 200#define DEV_CNTRL2 0x00040000 201 202#define PCI_MSK_IR (1 << 28) 203#define PCI_MSK_AV_CORE (1 << 27) 204#define PCI_MSK_GPIO1 (1 << 24) 205#define PCI_MSK_GPIO0 (1 << 23) 206#define PCI_MSK_APB_DMA (1 << 12) 207#define PCI_MSK_AL_WR (1 << 11) 208#define PCI_MSK_AL_RD (1 << 10) 209#define PCI_MSK_RISC_WR (1 << 9) 210#define PCI_MSK_RISC_RD (1 << 8) 211#define PCI_MSK_AUD_EXT (1 << 4) 212#define PCI_MSK_AUD_INT (1 << 3) 213#define PCI_MSK_VID_C (1 << 2) 214#define PCI_MSK_VID_B (1 << 1) 215#define PCI_MSK_VID_A 1 216#define PCI_INT_MSK 0x00040010 217 218#define PCI_INT_STAT 0x00040014 219#define PCI_INT_MSTAT 0x00040018 220 221#define VID_A_INT_MSK 0x00040020 222#define VID_A_INT_STAT 0x00040024 223#define VID_A_INT_MSTAT 0x00040028 224#define VID_A_INT_SSTAT 0x0004002C 225 226#define VID_B_INT_MSK 0x00040030 227#define VID_B_MSK_BAD_PKT (1 << 20) 228#define VID_B_MSK_VBI_OPC_ERR (1 << 17) 229#define VID_B_MSK_OPC_ERR (1 << 16) 230#define VID_B_MSK_VBI_SYNC (1 << 13) 231#define VID_B_MSK_SYNC (1 << 12) 232#define VID_B_MSK_VBI_OF (1 << 9) 233#define VID_B_MSK_OF (1 << 8) 234#define VID_B_MSK_VBI_RISCI2 (1 << 5) 235#define VID_B_MSK_RISCI2 (1 << 4) 236#define VID_B_MSK_VBI_RISCI1 (1 << 1) 237#define VID_B_MSK_RISCI1 1 238#define VID_B_INT_STAT 0x00040034 239#define VID_B_INT_MSTAT 0x00040038 240#define VID_B_INT_SSTAT 0x0004003C 241 242#define VID_B_MSK_BAD_PKT (1 << 20) 243#define VID_B_MSK_OPC_ERR (1 << 16) 244#define VID_B_MSK_SYNC (1 << 12) 245#define VID_B_MSK_OF (1 << 8) 246#define VID_B_MSK_RISCI2 (1 << 4) 247#define VID_B_MSK_RISCI1 1 248 249#define VID_C_MSK_BAD_PKT (1 << 20) 250#define VID_C_MSK_OPC_ERR (1 << 16) 251#define VID_C_MSK_SYNC (1 << 12) 252#define VID_C_MSK_OF (1 << 8) 253#define VID_C_MSK_RISCI2 (1 << 4) 254#define VID_C_MSK_RISCI1 1 255 256/* A superset for testing purposes */ 257#define VID_BC_MSK_BAD_PKT (1 << 20) 258#define VID_BC_MSK_OPC_ERR (1 << 16) 259#define VID_BC_MSK_SYNC (1 << 12) 260#define VID_BC_MSK_OF (1 << 8) 261#define VID_BC_MSK_VBI_RISCI2 (1 << 5) 262#define VID_BC_MSK_RISCI2 (1 << 4) 263#define VID_BC_MSK_VBI_RISCI1 (1 << 1) 264#define VID_BC_MSK_RISCI1 1 265 266#define VID_C_INT_MSK 0x00040040 267#define VID_C_INT_STAT 0x00040044 268#define VID_C_INT_MSTAT 0x00040048 269#define VID_C_INT_SSTAT 0x0004004C 270 271#define AUDIO_INT_INT_MSK 0x00040050 272#define AUDIO_INT_INT_STAT 0x00040054 273#define AUDIO_INT_INT_MSTAT 0x00040058 274#define AUDIO_INT_INT_SSTAT 0x0004005C 275 276#define AUDIO_EXT_INT_MSK 0x00040060 277#define AUDIO_EXT_INT_STAT 0x00040064 278#define AUDIO_EXT_INT_MSTAT 0x00040068 279#define AUDIO_EXT_INT_SSTAT 0x0004006C 280 281/* Bits [7:0] set in both TC_REQ and TC_REQ_SET 282 * indicate a stall in the RISC engine for a 283 * particular rider traffic class. This causes 284 * the 885 and 888 bridges (unknown about 887) 285 * to become inoperable. Setting bits in 286 * TC_REQ_SET resets the corresponding bits 287 * in TC_REQ (and TC_REQ_SET) allowing 288 * operation to continue. 289 */ 290#define TC_REQ 0x00040090 291#define TC_REQ_SET 0x00040094 292 293#define RDR_CFG0 0x00050000 294#define RDR_CFG1 0x00050004 295#define RDR_CFG2 0x00050008 296#define RDR_RDRCTL1 0x0005030c 297#define RDR_TLCTL0 0x00050318 298 299/* APB DMAC Current Buffer Pointer */ 300#define DMA1_PTR1 0x00100000 301#define DMA2_PTR1 0x00100004 302#define DMA3_PTR1 0x00100008 303#define DMA4_PTR1 0x0010000C 304#define DMA5_PTR1 0x00100010 305#define DMA6_PTR1 0x00100014 306#define DMA7_PTR1 0x00100018 307#define DMA8_PTR1 0x0010001C 308 309/* APB DMAC Current Table Pointer */ 310#define DMA1_PTR2 0x00100040 311#define DMA2_PTR2 0x00100044 312#define DMA3_PTR2 0x00100048 313#define DMA4_PTR2 0x0010004C 314#define DMA5_PTR2 0x00100050 315#define DMA6_PTR2 0x00100054 316#define DMA7_PTR2 0x00100058 317#define DMA8_PTR2 0x0010005C 318 319/* APB DMAC Buffer Limit */ 320#define DMA1_CNT1 0x00100080 321#define DMA2_CNT1 0x00100084 322#define DMA3_CNT1 0x00100088 323#define DMA4_CNT1 0x0010008C 324#define DMA5_CNT1 0x00100090 325#define DMA6_CNT1 0x00100094 326#define DMA7_CNT1 0x00100098 327#define DMA8_CNT1 0x0010009C 328 329/* APB DMAC Table Size */ 330#define DMA1_CNT2 0x001000C0 331#define DMA2_CNT2 0x001000C4 332#define DMA3_CNT2 0x001000C8 333#define DMA4_CNT2 0x001000CC 334#define DMA5_CNT2 0x001000D0 335#define DMA6_CNT2 0x001000D4 336#define DMA7_CNT2 0x001000D8 337#define DMA8_CNT2 0x001000DC 338 339/* Timer Counters */ 340#define TM_CNT_LDW 0x00110000 341#define TM_CNT_UW 0x00110004 342#define TM_LMT_LDW 0x00110008 343#define TM_LMT_UW 0x0011000C 344 345/* GPIO */ 346#define GP0_IO 0x00110010 347#define GPIO_ISM 0x00110014 348#define SOFT_RESET 0x0011001C 349 350/* GPIO (417 Microsoftcontroller) RW Data */ 351#define MC417_RWD 0x00110020 352 353/* GPIO (417 Microsoftcontroller) Output Enable, Low Active */ 354#define MC417_OEN 0x00110024 355#define MC417_CTL 0x00110028 356#define ALT_PIN_OUT_SEL 0x0011002C 357#define CLK_DELAY 0x00110048 358#define PAD_CTRL 0x0011004C 359 360/* Video A Interface */ 361#define VID_A_GPCNT 0x00130020 362#define VBI_A_GPCNT 0x00130024 363#define VID_A_GPCNT_CTL 0x00130030 364#define VBI_A_GPCNT_CTL 0x00130034 365#define VID_A_DMA_CTL 0x00130040 366#define VID_A_VIP_CTRL 0x00130080 367#define VID_A_PIXEL_FRMT 0x00130084 368#define VID_A_VBI_CTRL 0x00130088 369 370/* Video B Interface */ 371#define VID_B_DMA 0x00130100 372#define VBI_B_DMA 0x00130108 373#define VID_B_GPCNT 0x00130120 374#define VBI_B_GPCNT 0x00130124 375#define VID_B_GPCNT_CTL 0x00130134 376#define VBI_B_GPCNT_CTL 0x00130138 377#define VID_B_DMA_CTL 0x00130140 378#define VID_B_SRC_SEL 0x00130144 379#define VID_B_LNGTH 0x00130150 380#define VID_B_HW_SOP_CTL 0x00130154 381#define VID_B_GEN_CTL 0x00130158 382#define VID_B_BD_PKT_STATUS 0x0013015C 383#define VID_B_SOP_STATUS 0x00130160 384#define VID_B_FIFO_OVFL_STAT 0x00130164 385#define VID_B_VLD_MISC 0x00130168 386#define VID_B_TS_CLK_EN 0x0013016C 387#define VID_B_VIP_CTRL 0x00130180 388#define VID_B_PIXEL_FRMT 0x00130184 389 390/* Video C Interface */ 391#define VID_C_DMA 0x00130200 392#define VBI_C_DMA 0x00130208 393#define VID_C_GPCNT 0x00130220 394#define VID_C_GPCNT_CTL 0x00130230 395#define VBI_C_GPCNT_CTL 0x00130234 396#define VID_C_DMA_CTL 0x00130240 397#define VID_C_LNGTH 0x00130250 398#define VID_C_HW_SOP_CTL 0x00130254 399#define VID_C_GEN_CTL 0x00130258 400#define VID_C_BD_PKT_STATUS 0x0013025C 401#define VID_C_SOP_STATUS 0x00130260 402#define VID_C_FIFO_OVFL_STAT 0x00130264 403#define VID_C_VLD_MISC 0x00130268 404#define VID_C_TS_CLK_EN 0x0013026C 405 406/* Internal Audio Interface */ 407#define AUD_INT_A_GPCNT 0x00140020 408#define AUD_INT_B_GPCNT 0x00140024 409#define AUD_INT_A_GPCNT_CTL 0x00140030 410#define AUD_INT_B_GPCNT_CTL 0x00140034 411#define AUD_INT_DMA_CTL 0x00140040 412#define AUD_INT_A_LNGTH 0x00140050 413#define AUD_INT_B_LNGTH 0x00140054 414#define AUD_INT_A_MODE 0x00140058 415#define AUD_INT_B_MODE 0x0014005C 416 417/* External Audio Interface */ 418#define AUD_EXT_DMA 0x00140100 419#define AUD_EXT_GPCNT 0x00140120 420#define AUD_EXT_GPCNT_CTL 0x00140130 421#define AUD_EXT_DMA_CTL 0x00140140 422#define AUD_EXT_LNGTH 0x00140150 423#define AUD_EXT_A_MODE 0x00140158 424 425/* I2C Bus 1 */ 426#define I2C1_ADDR 0x00180000 427#define I2C1_WDATA 0x00180004 428#define I2C1_CTRL 0x00180008 429#define I2C1_RDATA 0x0018000C 430#define I2C1_STAT 0x00180010 431 432/* I2C Bus 2 */ 433#define I2C2_ADDR 0x00190000 434#define I2C2_WDATA 0x00190004 435#define I2C2_CTRL 0x00190008 436#define I2C2_RDATA 0x0019000C 437#define I2C2_STAT 0x00190010 438 439/* I2C Bus 3 */ 440#define I2C3_ADDR 0x001A0000 441#define I2C3_WDATA 0x001A0004 442#define I2C3_CTRL 0x001A0008 443#define I2C3_RDATA 0x001A000C 444#define I2C3_STAT 0x001A0010 445 446/* UART */ 447#define UART_CTL 0x001B0000 448#define UART_BRD 0x001B0004 449#define UART_ISR 0x001B000C 450#define UART_CNT 0x001B0010 451 452#endif /* _CX23885_REG_H_ */ 453