11573Srgrimes/* SPDX-License-Identifier: GPL-2.0-only */ 21573Srgrimes/* 31573Srgrimes * drx3973d_map_firm.h 41573Srgrimes * 51573Srgrimes * Copyright (C) 2006-2007 Micronas 61573Srgrimes */ 71573Srgrimes 81573Srgrimes#ifndef __DRX3973D_MAP__H__ 91573Srgrimes#define __DRX3973D_MAP__H__ 101573Srgrimes 111573Srgrimes/* 121573Srgrimes * Note: originally, this file contained 12000+ lines of data 131573Srgrimes * Probably a few lines for every firwmare assembler instruction. However, 141573Srgrimes * only a few defines were actually used. So, removed all uneeded lines. 151573Srgrimes * If ever needed, the other lines can be easily obtained via git history. 161573Srgrimes */ 171573Srgrimes 181573Srgrimes#define HI_COMM_EXEC__A 0x400000 191573Srgrimes#define HI_COMM_MB__A 0x400002 201573Srgrimes#define HI_CT_REG_COMM_STATE__A 0x410001 211573Srgrimes#define HI_RA_RAM_SRV_RES__A 0x420031 221573Srgrimes#define HI_RA_RAM_SRV_CMD__A 0x420032 231573Srgrimes#define HI_RA_RAM_SRV_CMD_RESET 0x2 241573Srgrimes#define HI_RA_RAM_SRV_CMD_CONFIG 0x3 251573Srgrimes#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 261573Srgrimes#define HI_RA_RAM_SRV_RST_KEY__A 0x420033 271573Srgrimes#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 281573Srgrimes#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 291573Srgrimes#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 301573Srgrimes#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 311573Srgrimes#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 321573Srgrimes#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 331573Srgrimes#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 341573Srgrimes#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 351573Srgrimes#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 3690045Sobrien#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 3790045Sobrien#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 381573Srgrimes#define HI_RA_RAM_USR_BEGIN__A 0x420040 391573Srgrimes#define HI_IF_RAM_TRP_BPT0__AX 0x430000 401573Srgrimes#define HI_IF_RAM_USR_BEGIN__A 0x430200 411573Srgrimes#define SC_COMM_EXEC__A 0x800000 421573Srgrimes#define SC_COMM_EXEC_CTL_STOP 0x0 431573Srgrimes#define SC_COMM_STATE__A 0x800001 44132812Stjr#define SC_RA_RAM_PARAM0__A 0x820040 45132812Stjr#define SC_RA_RAM_PARAM1__A 0x820041 46132812Stjr#define SC_RA_RAM_CMD_ADDR__A 0x820042 47132812Stjr#define SC_RA_RAM_CMD__A 0x820043 48132812Stjr#define SC_RA_RAM_CMD_PROC_START 0x1 49132812Stjr#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 50132812Stjr#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 51132812Stjr#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 52132812Stjr#define SC_RA_RAM_LOCKTRACK_MIN 0x1 53132812Stjr#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 54132812Stjr#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 551573Srgrimes#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 56132812Stjr#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 571573Srgrimes#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 58132812Stjr#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC 59132812Stjr#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 601573Srgrimes#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 6119276Sache#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 6219276Sache#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 631573Srgrimes#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 641573Srgrimes#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 6526484Sache#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 6626484Sache#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 6726484Sache#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 681573Srgrimes#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 69132812Stjr#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 70206711Sjilles#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 71206711Sjilles#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 7226484Sache#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 731573Srgrimes#define SC_RA_RAM_OP_AUTO_MODE__M 0x1 741573Srgrimes#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 751573Srgrimes#define SC_RA_RAM_OP_AUTO_CONST__M 0x4 761573Srgrimes#define SC_RA_RAM_OP_AUTO_HIER__M 0x8 771573Srgrimes#define SC_RA_RAM_OP_AUTO_RATE__M 0x10 78132812Stjr#define SC_RA_RAM_LOCK__A 0x82004B 79132812Stjr#define SC_RA_RAM_LOCK_DEMOD__M 0x1 80206711Sjilles#define SC_RA_RAM_LOCK_FEC__M 0x2 81132812Stjr#define SC_RA_RAM_LOCK_MPEG__M 0x4 82132812Stjr#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C 83132812Stjr#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 84206711Sjilles#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 85206711Sjilles#define SC_RA_RAM_CONFIG__A 0x820050 86132812Stjr#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 87132812Stjr#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 88132812Stjr#define SC_RA_RAM_CONFIG_SLAVE__M 0x20 8926484Sache#define SC_RA_RAM_IF_SAVE__AX 0x82008E 90132812Stjr#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 91132812Stjr#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 92132812Stjr#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 931573Srgrimes#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 94206711Sjilles#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 95132812Stjr#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 96132812Stjr#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 97132812Stjr#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 98132812Stjr#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 99132812Stjr#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 100132812Stjr#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 101132812Stjr#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 102132812Stjr#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 103132812Stjr#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 104132812Stjr#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 105132812Stjr#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 1061573Srgrimes#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 107132812Stjr#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 10819132Sache#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 109132812Stjr#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 1101573Srgrimes#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 111132812Stjr#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 1121573Srgrimes#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 113132812Stjr#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 1141573Srgrimes#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 115132812Stjr#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 1161573Srgrimes#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 1171573Srgrimes#define SC_RA_RAM_BAND__A 0x8200EC 1181573Srgrimes#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 119132812Stjr#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F 1201573Srgrimes#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 1211573Srgrimes#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F 1221573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 1231573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 1241573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB 1251573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 1261573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF 127132812Stjr#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 1281573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E 1291573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 1301573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A 1311573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 1321573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB 1331573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 1341573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F 13525269Sjdp#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 13625269Sjdp#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 1371573Srgrimes#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 1381573Srgrimes#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 1391573Srgrimes#define SC_RA_RAM_PROC_LOCKTRACK 0x0 1401573Srgrimes#define FE_COMM_EXEC__A 0xC00000 1411573Srgrimes#define FE_AD_REG_COMM_EXEC__A 0xC10000 1421573Srgrimes#define FE_AD_REG_FDB_IN__A 0xC10012 1431573Srgrimes#define FE_AD_REG_PD__A 0xC10013 1441573Srgrimes#define FE_AD_REG_INVEXT__A 0xC10014 1451573Srgrimes#define FE_AD_REG_CLKNEG__A 0xC10015 1461573Srgrimes#define FE_AG_REG_COMM_EXEC__A 0xC20000 147132812Stjr#define FE_AG_REG_AG_MODE_LOP__A 0xC20010 148206711Sjilles#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 149206711Sjilles#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 1501573Srgrimes#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 151132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 152132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 153132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 154132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 155132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 156132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 157132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 158132812Stjr#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 159132812Stjr#define FE_AG_REG_AG_MODE_HIP__A 0xC20011 1601573Srgrimes#define FE_AG_REG_AG_PGA_MODE__A 0xC20012 161132812Stjr#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 1621573Srgrimes#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 1631573Srgrimes#define FE_AG_REG_AG_AGC_SIO__A 0xC20013 1641573Srgrimes#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 165132812Stjr#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 1661573Srgrimes#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 167132812Stjr#define FE_AG_REG_AG_PWD__A 0xC20015 1681573Srgrimes#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 169132812Stjr#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 17026486Sache#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 17126486Sache#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 17226486Sache#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 17326486Sache#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 174132812Stjr#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 175132812Stjr#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 17626484Sache#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 17726484Sache#define FE_AG_REG_EGC_SET_LVL__A 0xC20025 17826484Sache#define FE_AG_REG_EGC_SET_LVL__M 0x1FF 17926484Sache#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 18026484Sache#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 18126484Sache#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 1821573Srgrimes#define FE_AG_REG_EGC_FLA_INC__A 0xC20029 18326484Sache#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 184132812Stjr#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B 1851573Srgrimes#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 1861573Srgrimes#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D 1871573Srgrimes#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 188132812Stjr#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 189132812Stjr#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF 190132812Stjr#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 191132812Stjr#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 192132812Stjr#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 193132812Stjr#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 194132812Stjr#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 1951573Srgrimes#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF 1961573Srgrimes#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 1971573Srgrimes#define FE_AG_REG_IND_WIN__A 0xC2003C 19826484Sache#define FE_AG_REG_IND_THD_LOL__A 0xC2003D 199132812Stjr#define FE_AG_REG_IND_THD_HIL__A 0xC2003E 20019059Swosch#define FE_AG_REG_IND_DEL__A 0xC2003F 20119132Sache#define FE_AG_REG_IND_PD1_WRI__A 0xC20040 202132812Stjr#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 20319059Swosch#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 20419059Swosch#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 2051573Srgrimes#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 206132812Stjr#define FE_AG_REG_PDC_SET_LVL__A 0xC20045 2071573Srgrimes#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 2081573Srgrimes#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 209132812Stjr#define FE_AG_REG_PDC_FLA_STP__A 0xC20048 2101573Srgrimes#define FE_AG_REG_PDC_SLO_STP__A 0xC20049 2111573Srgrimes#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 2121573Srgrimes#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 21326484Sache#define FE_AG_REG_PDC_MAX__A 0xC2004C 214132812Stjr#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 2151573Srgrimes#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 216132812Stjr#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 21719132Sache#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 21826484Sache#define FE_AG_REG_TGC_SET_LVL__A 0xC20051 219132812Stjr#define FE_AG_REG_TGC_SET_LVL__M 0x3F 2201573Srgrimes#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 22126492Sache#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 222132812Stjr#define FE_AG_REG_TGC_FLA_STP__A 0xC20054 223132812Stjr#define FE_AG_REG_TGC_SLO_STP__A 0xC20055 224132812Stjr#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 2251573Srgrimes#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 2261573Srgrimes#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 2271573Srgrimes#define FE_AG_REG_FGM_WRI__A 0xC20061 2281573Srgrimes#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 2291573Srgrimes#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 2301573Srgrimes#define FE_FS_REG_COMM_EXEC__A 0xC30000 2311573Srgrimes#define FE_FS_REG_ADD_INC_LOP__A 0xC30010 2321573Srgrimes#define FE_FD_REG_COMM_EXEC__A 0xC40000 23326486Sache#define FE_FD_REG_SCL__A 0xC40010 2341573Srgrimes#define FE_FD_REG_MAX_LEV__A 0xC40011 2358870Srgrimes#define FE_FD_REG_NR__A 0xC40012 23619132Sache#define FE_FD_REG_MEAS_VAL__A 0xC40014 237132812Stjr#define FE_IF_REG_COMM_EXEC__A 0xC50000 23819059Swosch#define FE_IF_REG_INCR0__A 0xC50010 23926484Sache#define FE_IF_REG_INCR0__W 16 24026484Sache#define FE_IF_REG_INCR0__M 0xFFFF 24126484Sache#define FE_IF_REG_INCR1__A 0xC50011 24226484Sache#define FE_IF_REG_INCR1__M 0xFF 24326484Sache#define FE_CF_REG_COMM_EXEC__A 0xC60000 24426492Sache#define FE_CF_REG_SCL__A 0xC60010 245132812Stjr#define FE_CF_REG_MAX_LEV__A 0xC60011 246132812Stjr#define FE_CF_REG_NR__A 0xC60012 247132812Stjr#define FE_CF_REG_IMP_VAL__A 0xC60013 248132812Stjr#define FE_CF_REG_MEAS_VAL__A 0xC60014 249132812Stjr#define FE_CU_REG_COMM_EXEC__A 0xC70000 250132812Stjr#define FE_CU_REG_FRM_CNT_RST__A 0xC70011 25126484Sache#define FE_CU_REG_FRM_CNT_STR__A 0xC70012 252132812Stjr#define FT_COMM_EXEC__A 0x1000000 25326486Sache#define FT_REG_COMM_EXEC__A 0x1010000 254132812Stjr#define CP_COMM_EXEC__A 0x1400000 255132812Stjr#define CP_REG_COMM_EXEC__A 0x1410000 256132812Stjr#define CP_REG_INTERVAL__A 0x1410011 257132812Stjr#define CP_REG_BR_SPL_OFFSET__A 0x1410023 258132812Stjr#define CP_REG_BR_STR_DEL__A 0x1410024 259132812Stjr#define CP_REG_RT_ANG_INC0__A 0x1410030 26026486Sache#define CP_REG_RT_ANG_INC1__A 0x1410031 26119132Sache#define CP_REG_RT_DETECT_ENA__A 0x1410032 262132812Stjr#define CP_REG_RT_DETECT_TRH__A 0x1410033 26319059Swosch#define CP_REG_RT_EXP_MARG__A 0x141003E 264132812Stjr#define CP_REG_AC_NEXP_OFFS__A 0x1410040 265132812Stjr#define CP_REG_AC_AVER_POW__A 0x1410041 266132812Stjr#define CP_REG_AC_MAX_POW__A 0x1410042 267132812Stjr#define CP_REG_AC_WEIGHT_MAN__A 0x1410043 268132812Stjr#define CP_REG_AC_WEIGHT_EXP__A 0x1410044 269132812Stjr#define CP_REG_AC_AMP_MODE__A 0x1410047 270132812Stjr#define CP_REG_AC_AMP_FIX__A 0x1410048 271132812Stjr#define CP_REG_AC_ANG_MODE__A 0x141004A 272132812Stjr#define CE_COMM_EXEC__A 0x1800000 2731573Srgrimes#define CE_REG_COMM_EXEC__A 0x1810000 27426484Sache#define CE_REG_TAPSET__A 0x1810011 27519059Swosch#define CE_REG_AVG_POW__A 0x1810012 27619132Sache#define CE_REG_MAX_POW__A 0x1810013 277132812Stjr#define CE_REG_ATT__A 0x1810014 27819059Swosch#define CE_REG_NRED__A 0x1810015 27924632Sache#define CE_REG_NE_ERR_SELECT__A 0x1810043 28024632Sache#define CE_REG_NE_TD_CAL__A 0x1810044 28124632Sache#define CE_REG_NE_MIXAVG__A 0x1810046 28224632Sache#define CE_REG_NE_NUPD_OFS__A 0x1810047 28317533Sache#define CE_REG_PE_NEXP_OFFS__A 0x1810050 2841573Srgrimes#define CE_REG_PE_TIMESHIFT__A 0x1810051 2851573Srgrimes#define CE_REG_TP_A0_TAP_NEW__A 0x1810064 2861573Srgrimes#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 287132812Stjr#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 28826492Sache#define CE_REG_TP_A1_TAP_NEW__A 0x1810068 28926484Sache#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 29026484Sache#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 2911573Srgrimes#define CE_REG_TI_NEXP_OFFS__A 0x1810070 292#define CE_REG_FI_SHT_INCR__A 0x1810090 293#define CE_REG_FI_EXP_NORM__A 0x1810091 294#define CE_REG_IR_INPUTSEL__A 0x18100A0 295#define CE_REG_IR_STARTPOS__A 0x18100A1 296#define CE_REG_IR_NEXP_THRES__A 0x18100A2 297#define CE_REG_FR_TREAL00__A 0x1820010 298#define CE_REG_FR_TIMAG00__A 0x1820011 299#define CE_REG_FR_TREAL01__A 0x1820012 300#define CE_REG_FR_TIMAG01__A 0x1820013 301#define CE_REG_FR_TREAL02__A 0x1820014 302#define CE_REG_FR_TIMAG02__A 0x1820015 303#define CE_REG_FR_TREAL03__A 0x1820016 304#define CE_REG_FR_TIMAG03__A 0x1820017 305#define CE_REG_FR_TREAL04__A 0x1820018 306#define CE_REG_FR_TIMAG04__A 0x1820019 307#define CE_REG_FR_TREAL05__A 0x182001A 308#define CE_REG_FR_TIMAG05__A 0x182001B 309#define CE_REG_FR_TREAL06__A 0x182001C 310#define CE_REG_FR_TIMAG06__A 0x182001D 311#define CE_REG_FR_TREAL07__A 0x182001E 312#define CE_REG_FR_TIMAG07__A 0x182001F 313#define CE_REG_FR_TREAL08__A 0x1820020 314#define CE_REG_FR_TIMAG08__A 0x1820021 315#define CE_REG_FR_TREAL09__A 0x1820022 316#define CE_REG_FR_TIMAG09__A 0x1820023 317#define CE_REG_FR_TREAL10__A 0x1820024 318#define CE_REG_FR_TIMAG10__A 0x1820025 319#define CE_REG_FR_TREAL11__A 0x1820026 320#define CE_REG_FR_TIMAG11__A 0x1820027 321#define CE_REG_FR_MID_TAP__A 0x1820028 322#define CE_REG_FR_SQS_G00__A 0x1820029 323#define CE_REG_FR_SQS_G01__A 0x182002A 324#define CE_REG_FR_SQS_G02__A 0x182002B 325#define CE_REG_FR_SQS_G03__A 0x182002C 326#define CE_REG_FR_SQS_G04__A 0x182002D 327#define CE_REG_FR_SQS_G05__A 0x182002E 328#define CE_REG_FR_SQS_G06__A 0x182002F 329#define CE_REG_FR_SQS_G07__A 0x1820030 330#define CE_REG_FR_SQS_G08__A 0x1820031 331#define CE_REG_FR_SQS_G09__A 0x1820032 332#define CE_REG_FR_SQS_G10__A 0x1820033 333#define CE_REG_FR_SQS_G11__A 0x1820034 334#define CE_REG_FR_SQS_G12__A 0x1820035 335#define CE_REG_FR_RIO_G00__A 0x1820036 336#define CE_REG_FR_RIO_G01__A 0x1820037 337#define CE_REG_FR_RIO_G02__A 0x1820038 338#define CE_REG_FR_RIO_G03__A 0x1820039 339#define CE_REG_FR_RIO_G04__A 0x182003A 340#define CE_REG_FR_RIO_G05__A 0x182003B 341#define CE_REG_FR_RIO_G06__A 0x182003C 342#define CE_REG_FR_RIO_G07__A 0x182003D 343#define CE_REG_FR_RIO_G08__A 0x182003E 344#define CE_REG_FR_RIO_G09__A 0x182003F 345#define CE_REG_FR_RIO_G10__A 0x1820040 346#define CE_REG_FR_MODE__A 0x1820041 347#define CE_REG_FR_SQS_TRH__A 0x1820042 348#define CE_REG_FR_RIO_GAIN__A 0x1820043 349#define CE_REG_FR_BYPASS__A 0x1820044 350#define CE_REG_FR_PM_SET__A 0x1820045 351#define CE_REG_FR_ERR_SH__A 0x1820046 352#define CE_REG_FR_MAN_SH__A 0x1820047 353#define CE_REG_FR_TAP_SH__A 0x1820048 354#define EQ_COMM_EXEC__A 0x1C00000 355#define EQ_REG_COMM_EXEC__A 0x1C10000 356#define EQ_REG_COMM_MB__A 0x1C10002 357#define EQ_REG_IS_GAIN_MAN__A 0x1C10015 358#define EQ_REG_IS_GAIN_EXP__A 0x1C10016 359#define EQ_REG_IS_CLIP_EXP__A 0x1C10017 360#define EQ_REG_SN_CEGAIN__A 0x1C1002A 361#define EQ_REG_SN_OFFSET__A 0x1C1002B 362#define EQ_REG_RC_SEL_CAR__A 0x1C10032 363#define EQ_REG_RC_SEL_CAR_INIT 0x0 364#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 365#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 366#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 367#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 368#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 369#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 370#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 371#define EQ_REG_OT_CONST__A 0x1C10046 372#define EQ_REG_OT_ALPHA__A 0x1C10047 373#define EQ_REG_OT_QNT_THRES0__A 0x1C10048 374#define EQ_REG_OT_QNT_THRES1__A 0x1C10049 375#define EQ_REG_OT_CSI_STEP__A 0x1C1004A 376#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 377#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 378#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 379#define EC_SB_REG_COMM_EXEC__A 0x2010000 380#define EC_SB_REG_TR_MODE__A 0x2010010 381#define EC_SB_REG_TR_MODE_8K 0x0 382#define EC_SB_REG_TR_MODE_2K 0x1 383#define EC_SB_REG_CONST__A 0x2010011 384#define EC_SB_REG_CONST_QPSK 0x0 385#define EC_SB_REG_CONST_16QAM 0x1 386#define EC_SB_REG_CONST_64QAM 0x2 387#define EC_SB_REG_ALPHA__A 0x2010012 388#define EC_SB_REG_PRIOR__A 0x2010013 389#define EC_SB_REG_PRIOR_HI 0x0 390#define EC_SB_REG_PRIOR_LO 0x1 391#define EC_SB_REG_CSI_HI__A 0x2010014 392#define EC_SB_REG_CSI_LO__A 0x2010015 393#define EC_SB_REG_SMB_TGL__A 0x2010016 394#define EC_SB_REG_SNR_HI__A 0x2010017 395#define EC_SB_REG_SNR_MID__A 0x2010018 396#define EC_SB_REG_SNR_LO__A 0x2010019 397#define EC_SB_REG_SCALE_MSB__A 0x201001A 398#define EC_SB_REG_SCALE_BIT2__A 0x201001B 399#define EC_SB_REG_SCALE_LSB__A 0x201001C 400#define EC_SB_REG_CSI_OFS__A 0x201001D 401#define EC_VD_REG_COMM_EXEC__A 0x2090000 402#define EC_VD_REG_FORCE__A 0x2090010 403#define EC_VD_REG_SET_CODERATE__A 0x2090011 404#define EC_VD_REG_SET_CODERATE_C1_2 0x0 405#define EC_VD_REG_SET_CODERATE_C2_3 0x1 406#define EC_VD_REG_SET_CODERATE_C3_4 0x2 407#define EC_VD_REG_SET_CODERATE_C5_6 0x3 408#define EC_VD_REG_SET_CODERATE_C7_8 0x4 409#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 410#define EC_VD_REG_RLK_ENA__A 0x2090014 411#define EC_OD_REG_COMM_EXEC__A 0x2110000 412#define EC_OD_REG_SYNC__A 0x2110010 413#define EC_OD_DEINT_RAM__A 0x2120000 414#define EC_RS_REG_COMM_EXEC__A 0x2130000 415#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 416#define EC_RS_REG_VAL__A 0x2130011 417#define EC_RS_REG_VAL_PCK 0x1 418#define EC_RS_EC_RAM__A 0x2140000 419#define EC_OC_REG_COMM_EXEC__A 0x2150000 420#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 421#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 422#define EC_OC_REG_COMM_INT_STA__A 0x2150007 423#define EC_OC_REG_OC_MODE_LOP__A 0x2150010 424#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 425#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 426#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 427#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 428#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 429#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 430#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 431#define EC_OC_REG_OC_MODE_HIP__A 0x2150011 432#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 433#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 434#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 435#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 436#define EC_OC_REG_OC_MPG_SIO__A 0x2150012 437#define EC_OC_REG_OC_MPG_SIO__M 0xFFF 438#define EC_OC_REG_OC_MON_SIO__A 0x2150013 439#define EC_OC_REG_DTO_INC_LOP__A 0x2150014 440#define EC_OC_REG_DTO_INC_HIP__A 0x2150015 441#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 442#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 443#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D 444#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E 445#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F 446#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 447#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 448#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 449#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 450#define EC_OC_REG_RCN_MODE__A 0x2150027 451#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 452#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 453#define EC_OC_REG_RCN_CST_LOP__A 0x215002A 454#define EC_OC_REG_RCN_CST_HIP__A 0x215002B 455#define EC_OC_REG_RCN_SET_LVL__A 0x215002C 456#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D 457#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 458#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 459#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 460#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 461#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 462#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF 463#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 464#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 465#define EC_OC_REG_OCR_MON_UOS__A 0x2150039 466#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 467#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 468#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 469#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 470#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 471#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 472#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 473#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 474#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 475#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 476#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 477#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 478#define EC_OC_REG_OCR_MON_WRI__A 0x215003A 479#define EC_OC_REG_OCR_MON_WRI_INIT 0x0 480#define EC_OC_REG_IPR_INV_MPG__A 0x2150045 481#define CC_REG_OSC_MODE__A 0x2410010 482#define CC_REG_OSC_MODE_M20 0x1 483#define CC_REG_PLL_MODE__A 0x2410011 484#define CC_REG_PLL_MODE_BYPASS_PLL 0x1 485#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 486#define CC_REG_REF_DIVIDE__A 0x2410012 487#define CC_REG_PWD_MODE__A 0x2410015 488#define CC_REG_PWD_MODE_DOWN_PLL 0x2 489#define CC_REG_UPDATE__A 0x2410017 490#define CC_REG_UPDATE_KEY 0x3973 491#define CC_REG_JTAGID_L__A 0x2410019 492#define LC_COMM_EXEC__A 0x2800000 493#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 494#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 495#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 496#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 497#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 498#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 499#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 500#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 501#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 502#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 503#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 504#define B_HI_COMM_EXEC__A 0x400000 505#define B_HI_COMM_MB__A 0x400002 506#define B_HI_CT_REG_COMM_STATE__A 0x410001 507#define B_HI_RA_RAM_SRV_RES__A 0x420031 508#define B_HI_RA_RAM_SRV_CMD__A 0x420032 509#define B_HI_RA_RAM_SRV_CMD_RESET 0x2 510#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 511#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 512#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 513#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 514#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 515#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 516#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 517#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 518#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 519#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 520#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 521#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 522#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 523#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 524#define B_HI_RA_RAM_USR_BEGIN__A 0x420040 525#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 526#define B_HI_IF_RAM_USR_BEGIN__A 0x430200 527#define B_SC_COMM_EXEC__A 0x800000 528#define B_SC_COMM_EXEC_CTL_STOP 0x0 529#define B_SC_COMM_STATE__A 0x800001 530#define B_SC_RA_RAM_PARAM0__A 0x820040 531#define B_SC_RA_RAM_PARAM1__A 0x820041 532#define B_SC_RA_RAM_CMD_ADDR__A 0x820042 533#define B_SC_RA_RAM_CMD__A 0x820043 534#define B_SC_RA_RAM_CMD_PROC_START 0x1 535#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 536#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 537#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 538#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 539#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 540#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 541#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 542#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 543#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 544#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC 545#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 546#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 547#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 548#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 549#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 550#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 551#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 552#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 553#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 554#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 555#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 556#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 557#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 558#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 559#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 560#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 561#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 562#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 563#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 564#define B_SC_RA_RAM_LOCK__A 0x82004B 565#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 566#define B_SC_RA_RAM_LOCK_FEC__M 0x2 567#define B_SC_RA_RAM_LOCK_MPEG__M 0x4 568#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C 569#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 570#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 571#define B_SC_RA_RAM_CONFIG__A 0x820050 572#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 573#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 574#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 575#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 576#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 577#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D 578#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E 579#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E 580#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 581#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 582#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A 583#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B 584#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C 585#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D 586#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E 587#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F 588#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 589#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 590#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 591#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 592#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 593#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 594#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 595#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 596#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 597#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 598#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 599#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 600#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 601#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 602#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 603#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 604#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 605#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 606#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 607#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 608#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 609#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 610#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 611#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 612#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 613#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 614#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 615#define B_SC_RA_RAM_BAND__A 0x8200EC 616#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 617#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F 618#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 619#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F 620#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 621#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 622#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 623#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 624#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D 625#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 626#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D 627#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 628#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 629#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 630#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 631#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 632#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A 633#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 634#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB 635#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 636#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 637#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 638#define B_FE_COMM_EXEC__A 0xC00000 639#define B_FE_AD_REG_COMM_EXEC__A 0xC10000 640#define B_FE_AD_REG_FDB_IN__A 0xC10012 641#define B_FE_AD_REG_PD__A 0xC10013 642#define B_FE_AD_REG_INVEXT__A 0xC10014 643#define B_FE_AD_REG_CLKNEG__A 0xC10015 644#define B_FE_AG_REG_COMM_EXEC__A 0xC20000 645#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 646#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 647#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 648#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 649#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 650#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 651#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 652#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 653#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 654#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 655#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 656#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 657#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 658#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 659#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 660#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 661#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 662#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 663#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 664#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 665#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 666#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 667#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 668#define B_FE_AG_REG_AG_PWD__A 0xC20015 669#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 670#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 671#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 672#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 673#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 674#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 675#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 676#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 677#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 678#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 679#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF 680#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 681#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 682#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 683#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 684#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 685#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B 686#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 687#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D 688#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 689#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 690#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF 691#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 692#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 693#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 694#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 695#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 696#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF 697#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 698#define B_FE_AG_REG_IND_WIN__A 0xC2003C 699#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D 700#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E 701#define B_FE_AG_REG_IND_DEL__A 0xC2003F 702#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 703#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 704#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 705#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 706#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 707#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 708#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 709#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 710#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 711#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 712#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 713#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 714#define B_FE_AG_REG_PDC_MAX__A 0xC2004C 715#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 716#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 717#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 718#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 719#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 720#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F 721#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 722#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 723#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 724#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 725#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 726#define B_FE_AG_REG_FGM_WRI__A 0xC20061 727#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 728#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 729#define B_FE_FS_REG_COMM_EXEC__A 0xC30000 730#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 731#define B_FE_FD_REG_COMM_EXEC__A 0xC40000 732#define B_FE_FD_REG_SCL__A 0xC40010 733#define B_FE_FD_REG_MAX_LEV__A 0xC40011 734#define B_FE_FD_REG_NR__A 0xC40012 735#define B_FE_FD_REG_MEAS_VAL__A 0xC40014 736#define B_FE_IF_REG_COMM_EXEC__A 0xC50000 737#define B_FE_IF_REG_INCR0__A 0xC50010 738#define B_FE_IF_REG_INCR0__W 16 739#define B_FE_IF_REG_INCR0__M 0xFFFF 740#define B_FE_IF_REG_INCR1__A 0xC50011 741#define B_FE_IF_REG_INCR1__M 0xFF 742#define B_FE_CF_REG_COMM_EXEC__A 0xC60000 743#define B_FE_CF_REG_SCL__A 0xC60010 744#define B_FE_CF_REG_MAX_LEV__A 0xC60011 745#define B_FE_CF_REG_NR__A 0xC60012 746#define B_FE_CF_REG_IMP_VAL__A 0xC60013 747#define B_FE_CF_REG_MEAS_VAL__A 0xC60014 748#define B_FE_CU_REG_COMM_EXEC__A 0xC70000 749#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 750#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 751#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 752#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 753#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 754#define B_FT_COMM_EXEC__A 0x1000000 755#define B_FT_REG_COMM_EXEC__A 0x1010000 756#define B_CP_COMM_EXEC__A 0x1400000 757#define B_CP_REG_COMM_EXEC__A 0x1410000 758#define B_CP_REG_INTERVAL__A 0x1410011 759#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 760#define B_CP_REG_BR_STR_DEL__A 0x1410024 761#define B_CP_REG_RT_ANG_INC0__A 0x1410030 762#define B_CP_REG_RT_ANG_INC1__A 0x1410031 763#define B_CP_REG_RT_DETECT_TRH__A 0x1410033 764#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 765#define B_CP_REG_AC_AVER_POW__A 0x1410041 766#define B_CP_REG_AC_MAX_POW__A 0x1410042 767#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 768#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 769#define B_CP_REG_AC_AMP_MODE__A 0x1410047 770#define B_CP_REG_AC_AMP_FIX__A 0x1410048 771#define B_CP_REG_AC_ANG_MODE__A 0x141004A 772#define B_CE_COMM_EXEC__A 0x1800000 773#define B_CE_REG_COMM_EXEC__A 0x1810000 774#define B_CE_REG_TAPSET__A 0x1810011 775#define B_CE_REG_AVG_POW__A 0x1810012 776#define B_CE_REG_MAX_POW__A 0x1810013 777#define B_CE_REG_ATT__A 0x1810014 778#define B_CE_REG_NRED__A 0x1810015 779#define B_CE_REG_NE_ERR_SELECT__A 0x1810043 780#define B_CE_REG_NE_TD_CAL__A 0x1810044 781#define B_CE_REG_NE_MIXAVG__A 0x1810046 782#define B_CE_REG_NE_NUPD_OFS__A 0x1810047 783#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 784#define B_CE_REG_PE_TIMESHIFT__A 0x1810051 785#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 786#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 787#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 788#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 789#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 790#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 791#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 792#define B_CE_REG_FI_SHT_INCR__A 0x1810090 793#define B_CE_REG_FI_EXP_NORM__A 0x1810091 794#define B_CE_REG_IR_INPUTSEL__A 0x18100A0 795#define B_CE_REG_IR_STARTPOS__A 0x18100A1 796#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 797#define B_CE_REG_FR_TREAL00__A 0x1820010 798#define B_CE_REG_FR_TIMAG00__A 0x1820011 799#define B_CE_REG_FR_TREAL01__A 0x1820012 800#define B_CE_REG_FR_TIMAG01__A 0x1820013 801#define B_CE_REG_FR_TREAL02__A 0x1820014 802#define B_CE_REG_FR_TIMAG02__A 0x1820015 803#define B_CE_REG_FR_TREAL03__A 0x1820016 804#define B_CE_REG_FR_TIMAG03__A 0x1820017 805#define B_CE_REG_FR_TREAL04__A 0x1820018 806#define B_CE_REG_FR_TIMAG04__A 0x1820019 807#define B_CE_REG_FR_TREAL05__A 0x182001A 808#define B_CE_REG_FR_TIMAG05__A 0x182001B 809#define B_CE_REG_FR_TREAL06__A 0x182001C 810#define B_CE_REG_FR_TIMAG06__A 0x182001D 811#define B_CE_REG_FR_TREAL07__A 0x182001E 812#define B_CE_REG_FR_TIMAG07__A 0x182001F 813#define B_CE_REG_FR_TREAL08__A 0x1820020 814#define B_CE_REG_FR_TIMAG08__A 0x1820021 815#define B_CE_REG_FR_TREAL09__A 0x1820022 816#define B_CE_REG_FR_TIMAG09__A 0x1820023 817#define B_CE_REG_FR_TREAL10__A 0x1820024 818#define B_CE_REG_FR_TIMAG10__A 0x1820025 819#define B_CE_REG_FR_TREAL11__A 0x1820026 820#define B_CE_REG_FR_TIMAG11__A 0x1820027 821#define B_CE_REG_FR_MID_TAP__A 0x1820028 822#define B_CE_REG_FR_SQS_G00__A 0x1820029 823#define B_CE_REG_FR_SQS_G01__A 0x182002A 824#define B_CE_REG_FR_SQS_G02__A 0x182002B 825#define B_CE_REG_FR_SQS_G03__A 0x182002C 826#define B_CE_REG_FR_SQS_G04__A 0x182002D 827#define B_CE_REG_FR_SQS_G05__A 0x182002E 828#define B_CE_REG_FR_SQS_G06__A 0x182002F 829#define B_CE_REG_FR_SQS_G07__A 0x1820030 830#define B_CE_REG_FR_SQS_G08__A 0x1820031 831#define B_CE_REG_FR_SQS_G09__A 0x1820032 832#define B_CE_REG_FR_SQS_G10__A 0x1820033 833#define B_CE_REG_FR_SQS_G11__A 0x1820034 834#define B_CE_REG_FR_SQS_G12__A 0x1820035 835#define B_CE_REG_FR_RIO_G00__A 0x1820036 836#define B_CE_REG_FR_RIO_G01__A 0x1820037 837#define B_CE_REG_FR_RIO_G02__A 0x1820038 838#define B_CE_REG_FR_RIO_G03__A 0x1820039 839#define B_CE_REG_FR_RIO_G04__A 0x182003A 840#define B_CE_REG_FR_RIO_G05__A 0x182003B 841#define B_CE_REG_FR_RIO_G06__A 0x182003C 842#define B_CE_REG_FR_RIO_G07__A 0x182003D 843#define B_CE_REG_FR_RIO_G08__A 0x182003E 844#define B_CE_REG_FR_RIO_G09__A 0x182003F 845#define B_CE_REG_FR_RIO_G10__A 0x1820040 846#define B_CE_REG_FR_MODE__A 0x1820041 847#define B_CE_REG_FR_SQS_TRH__A 0x1820042 848#define B_CE_REG_FR_RIO_GAIN__A 0x1820043 849#define B_CE_REG_FR_BYPASS__A 0x1820044 850#define B_CE_REG_FR_PM_SET__A 0x1820045 851#define B_CE_REG_FR_ERR_SH__A 0x1820046 852#define B_CE_REG_FR_MAN_SH__A 0x1820047 853#define B_CE_REG_FR_TAP_SH__A 0x1820048 854#define B_EQ_COMM_EXEC__A 0x1C00000 855#define B_EQ_REG_COMM_EXEC__A 0x1C10000 856#define B_EQ_REG_COMM_MB__A 0x1C10002 857#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 858#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 859#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 860#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A 861#define B_EQ_REG_SN_OFFSET__A 0x1C1002B 862#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 863#define B_EQ_REG_RC_SEL_CAR_INIT 0x2 864#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 865#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 866#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 867#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 868#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 869#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 870#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 871#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 872#define B_EQ_REG_OT_CONST__A 0x1C10046 873#define B_EQ_REG_OT_ALPHA__A 0x1C10047 874#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 875#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 876#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A 877#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 878#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 879#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 880#define B_EC_SB_REG_COMM_EXEC__A 0x2010000 881#define B_EC_SB_REG_TR_MODE__A 0x2010010 882#define B_EC_SB_REG_TR_MODE_8K 0x0 883#define B_EC_SB_REG_TR_MODE_2K 0x1 884#define B_EC_SB_REG_CONST__A 0x2010011 885#define B_EC_SB_REG_CONST_QPSK 0x0 886#define B_EC_SB_REG_CONST_16QAM 0x1 887#define B_EC_SB_REG_CONST_64QAM 0x2 888#define B_EC_SB_REG_ALPHA__A 0x2010012 889#define B_EC_SB_REG_PRIOR__A 0x2010013 890#define B_EC_SB_REG_PRIOR_HI 0x0 891#define B_EC_SB_REG_PRIOR_LO 0x1 892#define B_EC_SB_REG_CSI_HI__A 0x2010014 893#define B_EC_SB_REG_CSI_LO__A 0x2010015 894#define B_EC_SB_REG_SMB_TGL__A 0x2010016 895#define B_EC_SB_REG_SNR_HI__A 0x2010017 896#define B_EC_SB_REG_SNR_MID__A 0x2010018 897#define B_EC_SB_REG_SNR_LO__A 0x2010019 898#define B_EC_SB_REG_SCALE_MSB__A 0x201001A 899#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B 900#define B_EC_SB_REG_SCALE_LSB__A 0x201001C 901#define B_EC_SB_REG_CSI_OFS0__A 0x201001D 902#define B_EC_SB_REG_CSI_OFS1__A 0x201001E 903#define B_EC_SB_REG_CSI_OFS2__A 0x201001F 904#define B_EC_VD_REG_COMM_EXEC__A 0x2090000 905#define B_EC_VD_REG_FORCE__A 0x2090010 906#define B_EC_VD_REG_SET_CODERATE__A 0x2090011 907#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 908#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 909#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 910#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 911#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 912#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 913#define B_EC_VD_REG_RLK_ENA__A 0x2090014 914#define B_EC_OD_REG_COMM_EXEC__A 0x2110000 915#define B_EC_OD_REG_SYNC__A 0x2110664 916#define B_EC_OD_DEINT_RAM__A 0x2120000 917#define B_EC_RS_REG_COMM_EXEC__A 0x2130000 918#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 919#define B_EC_RS_REG_VAL__A 0x2130011 920#define B_EC_RS_REG_VAL_PCK 0x1 921#define B_EC_RS_EC_RAM__A 0x2140000 922#define B_EC_OC_REG_COMM_EXEC__A 0x2150000 923#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 924#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 925#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 926#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 927#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 928#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 929#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 930#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 931#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 932#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 933#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 934#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 935#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 936#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 937#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 938#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 939#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 940#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF 941#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 942#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 943#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 944#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 945#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D 946#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E 947#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F 948#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 949#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 950#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 951#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 952#define B_EC_OC_REG_RCN_MODE__A 0x2150027 953#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 954#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 955#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A 956#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B 957#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C 958#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D 959#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 960#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 961#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 962#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 963#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 964#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF 965#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 966#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 967#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 968#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 969#define B_EC_OC_REG_DTO_PER__A 0x2150048 970#define B_EC_OC_REG_DTO_BUR__A 0x2150049 971#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A 972#define B_CC_REG_OSC_MODE__A 0x2410010 973#define B_CC_REG_OSC_MODE_M20 0x1 974#define B_CC_REG_PLL_MODE__A 0x2410011 975#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 976#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 977#define B_CC_REG_REF_DIVIDE__A 0x2410012 978#define B_CC_REG_PWD_MODE__A 0x2410015 979#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 980#define B_CC_REG_UPDATE__A 0x2410017 981#define B_CC_REG_UPDATE_KEY 0x3973 982#define B_CC_REG_JTAGID_L__A 0x2410019 983#define B_CC_REG_DIVERSITY__A 0x241001B 984#define B_LC_COMM_EXEC__A 0x2800000 985#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 986#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 987#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 988#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 989#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 990#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 991#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 992#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 993#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 994#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 995#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 996 997#endif 998