1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Tegra CEC register definitions
4 *
5 * The original 3.10 CEC driver using a custom API:
6 *
7 * Copyright (c) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
8 *
9 * Conversion to the CEC framework and to the mainline kernel:
10 *
11 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
12 */
13
14#ifndef TEGRA_CEC_H
15#define TEGRA_CEC_H
16
17/* CEC registers */
18#define TEGRA_CEC_SW_CONTROL	0x000
19#define TEGRA_CEC_HW_CONTROL	0x004
20#define TEGRA_CEC_INPUT_FILTER	0x008
21#define TEGRA_CEC_TX_REGISTER	0x010
22#define TEGRA_CEC_RX_REGISTER	0x014
23#define TEGRA_CEC_RX_TIMING_0	0x018
24#define TEGRA_CEC_RX_TIMING_1	0x01c
25#define TEGRA_CEC_RX_TIMING_2	0x020
26#define TEGRA_CEC_TX_TIMING_0	0x024
27#define TEGRA_CEC_TX_TIMING_1	0x028
28#define TEGRA_CEC_TX_TIMING_2	0x02c
29#define TEGRA_CEC_INT_STAT	0x030
30#define TEGRA_CEC_INT_MASK	0x034
31#define TEGRA_CEC_HW_DEBUG_RX	0x038
32#define TEGRA_CEC_HW_DEBUG_TX	0x03c
33
34#define TEGRA_CEC_HWCTRL_RX_LADDR_MASK				0x7fff
35#define TEGRA_CEC_HWCTRL_RX_LADDR(x)	\
36	((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK)
37#define TEGRA_CEC_HWCTRL_RX_SNOOP				BIT(15)
38#define TEGRA_CEC_HWCTRL_RX_NAK_MODE				BIT(16)
39#define TEGRA_CEC_HWCTRL_TX_NAK_MODE				BIT(24)
40#define TEGRA_CEC_HWCTRL_FAST_SIM_MODE				BIT(30)
41#define TEGRA_CEC_HWCTRL_TX_RX_MODE				BIT(31)
42
43#define TEGRA_CEC_INPUT_FILTER_MODE				BIT(31)
44#define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT		0
45
46#define TEGRA_CEC_TX_REG_DATA_SHIFT				0
47#define TEGRA_CEC_TX_REG_EOM					BIT(8)
48#define TEGRA_CEC_TX_REG_BCAST					BIT(12)
49#define TEGRA_CEC_TX_REG_START_BIT				BIT(16)
50#define TEGRA_CEC_TX_REG_RETRY					BIT(17)
51
52#define TEGRA_CEC_RX_REGISTER_SHIFT				0
53#define TEGRA_CEC_RX_REGISTER_EOM				BIT(8)
54#define TEGRA_CEC_RX_REGISTER_ACK				BIT(9)
55
56#define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT		0
57#define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT		8
58#define TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT		16
59#define TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT		24
60
61#define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT		0
62#define TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT		8
63#define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT		16
64#define TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT		24
65
66#define TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT		0
67
68#define TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT		0
69#define TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT		8
70#define TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT			16
71#define TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT		24
72
73#define TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT		0
74#define TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT		8
75#define TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT		16
76#define TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT		24
77
78#define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT	0
79#define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT		4
80#define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT	8
81
82#define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY			BIT(0)
83#define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN			BIT(1)
84#define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD		BIT(2)
85#define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED		BIT(3)
86#define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED		BIT(4)
87#define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED			BIT(5)
88#define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL			BIT(8)
89#define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN			BIT(9)
90#define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED		BIT(10)
91#define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED		BIT(11)
92#define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED		BIT(12)
93#define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L	BIT(13)
94#define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H	BIT(14)
95
96#define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY			BIT(0)
97#define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN			BIT(1)
98#define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD		BIT(2)
99#define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED		BIT(3)
100#define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED		BIT(4)
101#define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED			BIT(5)
102#define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL			BIT(8)
103#define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN			BIT(9)
104#define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED		BIT(10)
105#define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED		BIT(11)
106#define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED		BIT(12)
107#define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L	BIT(13)
108#define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H	BIT(14)
109
110#define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT		0
111#define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT			17
112#define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT			21
113#define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT			BIT(25)
114#define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER		BIT(26)
115
116#endif /* TEGRA_CEC_H */
117