1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7#include <linux/device.h> 8#include <linux/interconnect.h> 9#include <linux/interconnect-provider.h> 10#include <linux/mod_devicetable.h> 11#include <linux/module.h> 12#include <linux/platform_device.h> 13#include <dt-bindings/interconnect/qcom,sm7150-rpmh.h> 14 15#include "bcm-voter.h" 16#include "icc-rpmh.h" 17#include "sm7150.h" 18 19static struct qcom_icc_node qhm_a1noc_cfg = { 20 .name = "qhm-a1noc-cfg", 21 .id = SM7150_MASTER_A1NOC_CFG, 22 .channels = 1, 23 .buswidth = 4, 24 .num_links = 1, 25 .links = { SM7150_SLAVE_SERVICE_A1NOC }, 26}; 27 28static struct qcom_icc_node qhm_qup_center = { 29 .name = "qhm_qup_center", 30 .id = SM7150_MASTER_QUP_0, 31 .channels = 1, 32 .buswidth = 4, 33 .num_links = 1, 34 .links = { SM7150_A1NOC_SNOC_SLV }, 35}; 36 37static struct qcom_icc_node qhm_tsif = { 38 .name = "qhm_tsif", 39 .id = SM7150_MASTER_TSIF, 40 .channels = 1, 41 .buswidth = 4, 42 .num_links = 1, 43 .links = { SM7150_A1NOC_SNOC_SLV }, 44}; 45 46static struct qcom_icc_node xm_emmc = { 47 .name = "xm_emmc", 48 .id = SM7150_MASTER_EMMC, 49 .channels = 1, 50 .buswidth = 8, 51 .num_links = 1, 52 .links = { SM7150_A1NOC_SNOC_SLV }, 53}; 54 55static struct qcom_icc_node xm_sdc2 = { 56 .name = "xm_sdc2", 57 .id = SM7150_MASTER_SDCC_2, 58 .channels = 1, 59 .buswidth = 8, 60 .num_links = 1, 61 .links = { SM7150_A1NOC_SNOC_SLV }, 62}; 63 64static struct qcom_icc_node xm_sdc4 = { 65 .name = "xm_sdc4", 66 .id = SM7150_MASTER_SDCC_4, 67 .channels = 1, 68 .buswidth = 8, 69 .num_links = 1, 70 .links = { SM7150_A1NOC_SNOC_SLV }, 71}; 72 73static struct qcom_icc_node xm_ufs_mem = { 74 .name = "xm_ufs_mem", 75 .id = SM7150_MASTER_UFS_MEM, 76 .channels = 1, 77 .buswidth = 8, 78 .num_links = 1, 79 .links = { SM7150_A1NOC_SNOC_SLV }, 80}; 81 82static struct qcom_icc_node qhm_a2noc_cfg = { 83 .name = "qhm_a2noc_cfg", 84 .id = SM7150_MASTER_A2NOC_CFG, 85 .channels = 1, 86 .buswidth = 4, 87 .num_links = 1, 88 .links = { SM7150_SLAVE_SERVICE_A2NOC }, 89}; 90 91static struct qcom_icc_node qhm_qdss_bam = { 92 .name = "qhm_qdss_bam", 93 .id = SM7150_MASTER_QDSS_BAM, 94 .channels = 1, 95 .buswidth = 4, 96 .num_links = 1, 97 .links = { SM7150_A2NOC_SNOC_SLV }, 98}; 99 100static struct qcom_icc_node qhm_qup_north = { 101 .name = "qhm_qup_north", 102 .id = SM7150_MASTER_QUP_1, 103 .channels = 1, 104 .buswidth = 4, 105 .num_links = 1, 106 .links = { SM7150_A2NOC_SNOC_SLV }, 107}; 108 109static struct qcom_icc_node qnm_cnoc = { 110 .name = "qnm_cnoc", 111 .id = SM7150_MASTER_CNOC_A2NOC, 112 .channels = 1, 113 .buswidth = 8, 114 .num_links = 1, 115 .links = { SM7150_A2NOC_SNOC_SLV }, 116}; 117 118static struct qcom_icc_node qxm_crypto = { 119 .name = "qxm_crypto", 120 .id = SM7150_MASTER_CRYPTO_CORE_0, 121 .channels = 1, 122 .buswidth = 8, 123 .num_links = 1, 124 .links = { SM7150_A2NOC_SNOC_SLV }, 125}; 126 127static struct qcom_icc_node qxm_ipa = { 128 .name = "qxm_ipa", 129 .id = SM7150_MASTER_IPA, 130 .channels = 1, 131 .buswidth = 8, 132 .num_links = 1, 133 .links = { SM7150_A2NOC_SNOC_SLV }, 134}; 135 136static struct qcom_icc_node xm_pcie3_0 = { 137 .name = "xm_pcie3_0", 138 .id = SM7150_MASTER_PCIE, 139 .channels = 1, 140 .buswidth = 8, 141 .num_links = 1, 142 .links = { SM7150_SLAVE_ANOC_PCIE_GEM_NOC }, 143}; 144 145static struct qcom_icc_node xm_qdss_etr = { 146 .name = "xm_qdss_etr", 147 .id = SM7150_MASTER_QDSS_ETR, 148 .channels = 1, 149 .buswidth = 8, 150 .num_links = 1, 151 .links = { SM7150_A2NOC_SNOC_SLV }, 152}; 153 154static struct qcom_icc_node xm_usb3_0 = { 155 .name = "xm_usb3_0", 156 .id = SM7150_MASTER_USB3, 157 .channels = 1, 158 .buswidth = 8, 159 .num_links = 1, 160 .links = { SM7150_A2NOC_SNOC_SLV }, 161}; 162 163static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 164 .name = "qxm_camnoc_hf0_uncomp", 165 .id = SM7150_MASTER_CAMNOC_HF0_UNCOMP, 166 .channels = 2, 167 .buswidth = 32, 168 .num_links = 1, 169 .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, 170}; 171 172static struct qcom_icc_node qxm_camnoc_rt_uncomp = { 173 .name = "qxm_camnoc_rt_uncomp", 174 .id = SM7150_MASTER_CAMNOC_RT_UNCOMP, 175 .channels = 1, 176 .buswidth = 32, 177 .num_links = 1, 178 .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, 179}; 180 181static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 182 .name = "qxm_camnoc_sf_uncomp", 183 .id = SM7150_MASTER_CAMNOC_SF_UNCOMP, 184 .channels = 1, 185 .buswidth = 32, 186 .num_links = 1, 187 .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, 188}; 189 190static struct qcom_icc_node qxm_camnoc_nrt_uncomp = { 191 .name = "qxm_camnoc_nrt_uncomp", 192 .id = SM7150_MASTER_CAMNOC_NRT_UNCOMP, 193 .channels = 1, 194 .buswidth = 32, 195 .num_links = 1, 196 .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, 197}; 198 199static struct qcom_icc_node qnm_npu = { 200 .name = "qnm_npu", 201 .id = SM7150_MASTER_NPU, 202 .channels = 1, 203 .buswidth = 32, 204 .num_links = 1, 205 .links = { SM7150_SLAVE_CDSP_GEM_NOC }, 206}; 207 208static struct qcom_icc_node qhm_spdm = { 209 .name = "qhm_spdm", 210 .id = SM7150_MASTER_SPDM, 211 .channels = 1, 212 .buswidth = 4, 213 .num_links = 1, 214 .links = { SM7150_SLAVE_CNOC_A2NOC }, 215}; 216 217static struct qcom_icc_node qnm_snoc = { 218 .name = "qnm_snoc", 219 .id = SM7150_SNOC_CNOC_MAS, 220 .channels = 1, 221 .buswidth = 8, 222 .num_links = 47, 223 .links = { SM7150_SLAVE_TLMM_SOUTH, 224 SM7150_SLAVE_CAMERA_CFG, 225 SM7150_SLAVE_SDCC_4, 226 SM7150_SLAVE_SDCC_2, 227 SM7150_SLAVE_CNOC_MNOC_CFG, 228 SM7150_SLAVE_UFS_MEM_CFG, 229 SM7150_SLAVE_QUP_0, 230 SM7150_SLAVE_GLM, 231 SM7150_SLAVE_PDM, 232 SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, 233 SM7150_SLAVE_A2NOC_CFG, 234 SM7150_SLAVE_QDSS_CFG, 235 SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, 236 SM7150_SLAVE_DISPLAY_CFG, 237 SM7150_SLAVE_PCIE_CFG, 238 SM7150_SLAVE_DISPLAY_THROTTLE_CFG, 239 SM7150_SLAVE_TCSR, 240 SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, 241 SM7150_SLAVE_CNOC_DDRSS, 242 SM7150_SLAVE_AHB2PHY_NORTH, 243 SM7150_SLAVE_SNOC_CFG, 244 SM7150_SLAVE_GRAPHICS_3D_CFG, 245 SM7150_SLAVE_VENUS_CFG, 246 SM7150_SLAVE_TSIF, 247 SM7150_SLAVE_CDSP_CFG, 248 SM7150_SLAVE_CLK_CTL, 249 SM7150_SLAVE_AOP, 250 SM7150_SLAVE_QUP_1, 251 SM7150_SLAVE_AHB2PHY_SOUTH, 252 SM7150_SLAVE_SERVICE_CNOC, 253 SM7150_SLAVE_AHB2PHY_WEST, 254 SM7150_SLAVE_USB3, 255 SM7150_SLAVE_VENUS_THROTTLE_CFG, 256 SM7150_SLAVE_IPA_CFG, 257 SM7150_SLAVE_RBCPR_CX_CFG, 258 SM7150_SLAVE_TLMM_WEST, 259 SM7150_SLAVE_A1NOC_CFG, 260 SM7150_SLAVE_AOSS, 261 SM7150_SLAVE_PRNG, 262 SM7150_SLAVE_VSENSE_CTRL_CFG, 263 SM7150_SLAVE_EMMC_CFG, 264 SM7150_SLAVE_SPDM_WRAPPER, 265 SM7150_SLAVE_CRYPTO_0_CFG, 266 SM7150_SLAVE_PIMEM_CFG, 267 SM7150_SLAVE_TLMM_NORTH, 268 SM7150_SLAVE_RBCPR_MX_CFG, 269 SM7150_SLAVE_IMEM_CFG 270 }, 271}; 272 273static struct qcom_icc_node xm_qdss_dap = { 274 .name = "xm_qdss_dap", 275 .id = SM7150_MASTER_QDSS_DAP, 276 .channels = 1, 277 .buswidth = 8, 278 .num_links = 48, 279 .links = { SM7150_SLAVE_TLMM_SOUTH, 280 SM7150_SLAVE_CAMERA_CFG, 281 SM7150_SLAVE_SDCC_4, 282 SM7150_SLAVE_SDCC_2, 283 SM7150_SLAVE_CNOC_MNOC_CFG, 284 SM7150_SLAVE_UFS_MEM_CFG, 285 SM7150_SLAVE_QUP_0, 286 SM7150_SLAVE_GLM, 287 SM7150_SLAVE_PDM, 288 SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, 289 SM7150_SLAVE_A2NOC_CFG, 290 SM7150_SLAVE_QDSS_CFG, 291 SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, 292 SM7150_SLAVE_DISPLAY_CFG, 293 SM7150_SLAVE_PCIE_CFG, 294 SM7150_SLAVE_DISPLAY_THROTTLE_CFG, 295 SM7150_SLAVE_TCSR, 296 SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, 297 SM7150_SLAVE_CNOC_DDRSS, 298 SM7150_SLAVE_CNOC_A2NOC, 299 SM7150_SLAVE_AHB2PHY_NORTH, 300 SM7150_SLAVE_SNOC_CFG, 301 SM7150_SLAVE_GRAPHICS_3D_CFG, 302 SM7150_SLAVE_VENUS_CFG, 303 SM7150_SLAVE_TSIF, 304 SM7150_SLAVE_CDSP_CFG, 305 SM7150_SLAVE_CLK_CTL, 306 SM7150_SLAVE_AOP, 307 SM7150_SLAVE_QUP_1, 308 SM7150_SLAVE_AHB2PHY_SOUTH, 309 SM7150_SLAVE_SERVICE_CNOC, 310 SM7150_SLAVE_AHB2PHY_WEST, 311 SM7150_SLAVE_USB3, 312 SM7150_SLAVE_VENUS_THROTTLE_CFG, 313 SM7150_SLAVE_IPA_CFG, 314 SM7150_SLAVE_RBCPR_CX_CFG, 315 SM7150_SLAVE_TLMM_WEST, 316 SM7150_SLAVE_A1NOC_CFG, 317 SM7150_SLAVE_AOSS, 318 SM7150_SLAVE_PRNG, 319 SM7150_SLAVE_VSENSE_CTRL_CFG, 320 SM7150_SLAVE_EMMC_CFG, 321 SM7150_SLAVE_SPDM_WRAPPER, 322 SM7150_SLAVE_CRYPTO_0_CFG, 323 SM7150_SLAVE_PIMEM_CFG, 324 SM7150_SLAVE_TLMM_NORTH, 325 SM7150_SLAVE_RBCPR_MX_CFG, 326 SM7150_SLAVE_IMEM_CFG 327 }, 328}; 329 330static struct qcom_icc_node qhm_cnoc_dc_noc = { 331 .name = "qhm_cnoc_dc_noc", 332 .id = SM7150_MASTER_CNOC_DC_NOC, 333 .channels = 1, 334 .buswidth = 4, 335 .num_links = 2, 336 .links = { SM7150_SLAVE_LLCC_CFG, 337 SM7150_SLAVE_GEM_NOC_CFG 338 }, 339}; 340 341static struct qcom_icc_node acm_apps = { 342 .name = "acm_apps", 343 .id = SM7150_MASTER_AMPSS_M0, 344 .channels = 1, 345 .buswidth = 16, 346 .num_links = 2, 347 .links = { SM7150_SLAVE_LLCC, 348 SM7150_SLAVE_GEM_NOC_SNOC 349 }, 350}; 351 352static struct qcom_icc_node acm_sys_tcu = { 353 .name = "acm_sys_tcu", 354 .id = SM7150_MASTER_SYS_TCU, 355 .channels = 1, 356 .buswidth = 8, 357 .num_links = 2, 358 .links = { SM7150_SLAVE_LLCC, 359 SM7150_SLAVE_GEM_NOC_SNOC 360 }, 361}; 362 363static struct qcom_icc_node qhm_gemnoc_cfg = { 364 .name = "qhm_gemnoc_cfg", 365 .id = SM7150_MASTER_GEM_NOC_CFG, 366 .channels = 1, 367 .buswidth = 4, 368 .num_links = 2, 369 .links = { SM7150_SLAVE_SERVICE_GEM_NOC, 370 SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 371 }, 372}; 373 374static struct qcom_icc_node qnm_cmpnoc = { 375 .name = "qnm_cmpnoc", 376 .id = SM7150_MASTER_COMPUTE_NOC, 377 .channels = 1, 378 .buswidth = 32, 379 .num_links = 2, 380 .links = { SM7150_SLAVE_LLCC, 381 SM7150_SLAVE_GEM_NOC_SNOC 382 }, 383}; 384 385static struct qcom_icc_node qnm_mnoc_hf = { 386 .name = "qnm_mnoc_hf", 387 .id = SM7150_MASTER_MNOC_HF_MEM_NOC, 388 .channels = 2, 389 .buswidth = 32, 390 .num_links = 1, 391 .links = { SM7150_SLAVE_LLCC }, 392}; 393 394static struct qcom_icc_node qnm_mnoc_sf = { 395 .name = "qnm_mnoc_sf", 396 .id = SM7150_MASTER_MNOC_SF_MEM_NOC, 397 .channels = 1, 398 .buswidth = 32, 399 .num_links = 2, 400 .links = { SM7150_SLAVE_LLCC, 401 SM7150_SLAVE_GEM_NOC_SNOC 402 }, 403}; 404 405static struct qcom_icc_node qnm_pcie = { 406 .name = "qnm_pcie", 407 .id = SM7150_MASTER_GEM_NOC_PCIE_SNOC, 408 .channels = 1, 409 .buswidth = 8, 410 .num_links = 2, 411 .links = { SM7150_SLAVE_LLCC, 412 SM7150_SLAVE_GEM_NOC_SNOC 413 }, 414}; 415 416static struct qcom_icc_node qnm_snoc_gc = { 417 .name = "qnm_snoc_gc", 418 .id = SM7150_MASTER_SNOC_GC_MEM_NOC, 419 .channels = 1, 420 .buswidth = 8, 421 .num_links = 1, 422 .links = { SM7150_SLAVE_LLCC }, 423}; 424 425static struct qcom_icc_node qnm_snoc_sf = { 426 .name = "qnm_snoc_sf", 427 .id = SM7150_MASTER_SNOC_SF_MEM_NOC, 428 .channels = 1, 429 .buswidth = 16, 430 .num_links = 1, 431 .links = { SM7150_SLAVE_LLCC }, 432}; 433 434static struct qcom_icc_node qxm_gpu = { 435 .name = "qxm_gpu", 436 .id = SM7150_MASTER_GRAPHICS_3D, 437 .channels = 2, 438 .buswidth = 32, 439 .num_links = 2, 440 .links = { SM7150_SLAVE_LLCC, 441 SM7150_SLAVE_GEM_NOC_SNOC 442 }, 443}; 444 445static struct qcom_icc_node llcc_mc = { 446 .name = "llcc_mc", 447 .id = SM7150_MASTER_LLCC, 448 .channels = 2, 449 .buswidth = 4, 450 .num_links = 1, 451 .links = { SM7150_SLAVE_EBI_CH0 }, 452}; 453 454static struct qcom_icc_node qhm_mnoc_cfg = { 455 .name = "qhm_mnoc_cfg", 456 .id = SM7150_MASTER_CNOC_MNOC_CFG, 457 .channels = 1, 458 .buswidth = 4, 459 .num_links = 1, 460 .links = { SM7150_SLAVE_SERVICE_MNOC }, 461}; 462 463static struct qcom_icc_node qxm_camnoc_hf = { 464 .name = "qxm_camnoc_hf", 465 .id = SM7150_MASTER_CAMNOC_HF0, 466 .channels = 2, 467 .buswidth = 32, 468 .num_links = 1, 469 .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, 470}; 471 472static struct qcom_icc_node qxm_camnoc_nrt = { 473 .name = "qxm_camnoc_nrt", 474 .id = SM7150_MASTER_CAMNOC_NRT, 475 .channels = 1, 476 .buswidth = 8, 477 .num_links = 1, 478 .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, 479}; 480 481static struct qcom_icc_node qxm_camnoc_rt = { 482 .name = "qxm_camnoc_rt", 483 .id = SM7150_MASTER_CAMNOC_RT, 484 .channels = 1, 485 .buswidth = 32, 486 .num_links = 1, 487 .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, 488}; 489 490static struct qcom_icc_node qxm_camnoc_sf = { 491 .name = "qxm_camnoc_sf", 492 .id = SM7150_MASTER_CAMNOC_SF, 493 .channels = 1, 494 .buswidth = 32, 495 .num_links = 1, 496 .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, 497}; 498 499static struct qcom_icc_node qxm_mdp0 = { 500 .name = "qxm_mdp0", 501 .id = SM7150_MASTER_MDP_PORT0, 502 .channels = 1, 503 .buswidth = 32, 504 .num_links = 1, 505 .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, 506}; 507 508static struct qcom_icc_node qxm_mdp1 = { 509 .name = "qxm_mdp1", 510 .id = SM7150_MASTER_MDP_PORT1, 511 .channels = 1, 512 .buswidth = 32, 513 .num_links = 1, 514 .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, 515}; 516 517static struct qcom_icc_node qxm_rot = { 518 .name = "qxm_rot", 519 .id = SM7150_MASTER_ROTATOR, 520 .channels = 1, 521 .buswidth = 32, 522 .num_links = 1, 523 .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, 524}; 525 526static struct qcom_icc_node qxm_venus0 = { 527 .name = "qxm_venus0", 528 .id = SM7150_MASTER_VIDEO_P0, 529 .channels = 1, 530 .buswidth = 32, 531 .num_links = 1, 532 .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, 533}; 534 535static struct qcom_icc_node qxm_venus1 = { 536 .name = "qxm_venus1", 537 .id = SM7150_MASTER_VIDEO_P1, 538 .channels = 1, 539 .buswidth = 32, 540 .num_links = 1, 541 .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, 542}; 543 544static struct qcom_icc_node qxm_venus_arm9 = { 545 .name = "qxm_venus_arm9", 546 .id = SM7150_MASTER_VIDEO_PROC, 547 .channels = 1, 548 .buswidth = 8, 549 .num_links = 1, 550 .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, 551}; 552 553static struct qcom_icc_node qhm_snoc_cfg = { 554 .name = "qhm_snoc_cfg", 555 .id = SM7150_MASTER_SNOC_CFG, 556 .channels = 1, 557 .buswidth = 4, 558 .num_links = 1, 559 .links = { SM7150_SLAVE_SERVICE_SNOC }, 560}; 561 562static struct qcom_icc_node qnm_aggre1_noc = { 563 .name = "qnm_aggre1_noc", 564 .id = SM7150_A1NOC_SNOC_MAS, 565 .channels = 1, 566 .buswidth = 16, 567 .num_links = 6, 568 .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF, 569 SM7150_SLAVE_PIMEM, 570 SM7150_SLAVE_OCIMEM, 571 SM7150_SLAVE_APPSS, 572 SM7150_SNOC_CNOC_SLV, 573 SM7150_SLAVE_QDSS_STM 574 }, 575}; 576 577static struct qcom_icc_node qnm_aggre2_noc = { 578 .name = "qnm_aggre2_noc", 579 .id = SM7150_A2NOC_SNOC_MAS, 580 .channels = 1, 581 .buswidth = 16, 582 .num_links = 7, 583 .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF, 584 SM7150_SLAVE_PIMEM, 585 SM7150_SLAVE_OCIMEM, 586 SM7150_SLAVE_APPSS, 587 SM7150_SNOC_CNOC_SLV, 588 SM7150_SLAVE_TCU, 589 SM7150_SLAVE_QDSS_STM 590 }, 591}; 592 593static struct qcom_icc_node qnm_gemnoc = { 594 .name = "qnm_gemnoc", 595 .id = SM7150_MASTER_GEM_NOC_SNOC, 596 .channels = 1, 597 .buswidth = 8, 598 .num_links = 6, 599 .links = { SM7150_SLAVE_PIMEM, 600 SM7150_SLAVE_OCIMEM, 601 SM7150_SLAVE_APPSS, 602 SM7150_SNOC_CNOC_SLV, 603 SM7150_SLAVE_TCU, 604 SM7150_SLAVE_QDSS_STM 605 }, 606}; 607 608static struct qcom_icc_node qxm_pimem = { 609 .name = "qxm_pimem", 610 .id = SM7150_MASTER_PIMEM, 611 .channels = 1, 612 .buswidth = 8, 613 .num_links = 2, 614 .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC, 615 SM7150_SLAVE_OCIMEM 616 }, 617}; 618 619static struct qcom_icc_node xm_gic = { 620 .name = "xm_gic", 621 .id = SM7150_MASTER_GIC, 622 .channels = 1, 623 .buswidth = 8, 624 .num_links = 2, 625 .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC, 626 SM7150_SLAVE_OCIMEM 627 }, 628}; 629 630static struct qcom_icc_node qns_a1noc_snoc = { 631 .name = "qns_a1noc_snoc", 632 .id = SM7150_A1NOC_SNOC_SLV, 633 .channels = 1, 634 .buswidth = 16, 635 .num_links = 1, 636 .links = { SM7150_A1NOC_SNOC_MAS }, 637}; 638 639static struct qcom_icc_node srvc_aggre1_noc = { 640 .name = "srvc_aggre1_noc", 641 .id = SM7150_SLAVE_SERVICE_A1NOC, 642 .channels = 1, 643 .buswidth = 4, 644}; 645 646static struct qcom_icc_node qns_a2noc_snoc = { 647 .name = "qns_a2noc_snoc", 648 .id = SM7150_A2NOC_SNOC_SLV, 649 .channels = 1, 650 .buswidth = 16, 651 .num_links = 1, 652 .links = { SM7150_A2NOC_SNOC_MAS }, 653}; 654 655static struct qcom_icc_node qns_pcie_gemnoc = { 656 .name = "qns_pcie_gemnoc", 657 .id = SM7150_SLAVE_ANOC_PCIE_GEM_NOC, 658 .channels = 1, 659 .buswidth = 8, 660 .num_links = 1, 661 .links = { SM7150_MASTER_GEM_NOC_PCIE_SNOC }, 662}; 663 664static struct qcom_icc_node srvc_aggre2_noc = { 665 .name = "srvc_aggre2_noc", 666 .id = SM7150_SLAVE_SERVICE_A2NOC, 667 .channels = 1, 668 .buswidth = 4, 669}; 670 671static struct qcom_icc_node qns_camnoc_uncomp = { 672 .name = "qns_camnoc_uncomp", 673 .id = SM7150_SLAVE_CAMNOC_UNCOMP, 674 .channels = 1, 675 .buswidth = 32, 676}; 677 678static struct qcom_icc_node qns_cdsp_gemnoc = { 679 .name = "qns_cdsp_gemnoc", 680 .id = SM7150_SLAVE_CDSP_GEM_NOC, 681 .channels = 1, 682 .buswidth = 32, 683 .num_links = 1, 684 .links = { SM7150_MASTER_COMPUTE_NOC }, 685}; 686 687static struct qcom_icc_node qhs_a1_noc_cfg = { 688 .name = "qhs_a1_noc_cfg", 689 .id = SM7150_SLAVE_A1NOC_CFG, 690 .channels = 1, 691 .buswidth = 4, 692 .num_links = 1, 693 .links = { SM7150_MASTER_A1NOC_CFG }, 694}; 695 696static struct qcom_icc_node qhs_a2_noc_cfg = { 697 .name = "qhs_a2_noc_cfg", 698 .id = SM7150_SLAVE_A2NOC_CFG, 699 .channels = 1, 700 .buswidth = 4, 701 .num_links = 1, 702 .links = { SM7150_MASTER_A2NOC_CFG }, 703}; 704 705static struct qcom_icc_node qhs_ahb2phy_north = { 706 .name = "qhs_ahb2phy_north", 707 .id = SM7150_SLAVE_AHB2PHY_NORTH, 708 .channels = 1, 709 .buswidth = 4, 710}; 711 712static struct qcom_icc_node qhs_ahb2phy_south = { 713 .name = "qhs_ahb2phy_south", 714 .id = SM7150_SLAVE_AHB2PHY_SOUTH, 715 .channels = 1, 716 .buswidth = 4, 717}; 718 719static struct qcom_icc_node qhs_ahb2phy_west = { 720 .name = "qhs_ahb2phy_west", 721 .id = SM7150_SLAVE_AHB2PHY_WEST, 722 .channels = 1, 723 .buswidth = 4, 724}; 725 726static struct qcom_icc_node qhs_aop = { 727 .name = "qhs_aop", 728 .id = SM7150_SLAVE_AOP, 729 .channels = 1, 730 .buswidth = 4, 731}; 732 733static struct qcom_icc_node qhs_aoss = { 734 .name = "qhs_aoss", 735 .id = SM7150_SLAVE_AOSS, 736 .channels = 1, 737 .buswidth = 4, 738}; 739 740static struct qcom_icc_node qhs_camera_cfg = { 741 .name = "qhs_camera_cfg", 742 .id = SM7150_SLAVE_CAMERA_CFG, 743 .channels = 1, 744 .buswidth = 4, 745}; 746 747static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { 748 .name = "qhs_camera_nrt_thrott_cfg", 749 .id = SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, 750 .channels = 1, 751 .buswidth = 4, 752}; 753 754static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 755 .name = "qhs_camera_rt_throttle_cfg", 756 .id = SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, 757 .channels = 1, 758 .buswidth = 4, 759}; 760 761static struct qcom_icc_node qhs_clk_ctl = { 762 .name = "qhs_clk_ctl", 763 .id = SM7150_SLAVE_CLK_CTL, 764 .channels = 1, 765 .buswidth = 4, 766}; 767 768static struct qcom_icc_node qhs_compute_dsp_cfg = { 769 .name = "qhs_compute_dsp_cfg", 770 .id = SM7150_SLAVE_CDSP_CFG, 771 .channels = 1, 772 .buswidth = 4, 773}; 774 775static struct qcom_icc_node qhs_cpr_cx = { 776 .name = "qhs_cpr_cx", 777 .id = SM7150_SLAVE_RBCPR_CX_CFG, 778 .channels = 1, 779 .buswidth = 4, 780}; 781 782static struct qcom_icc_node qhs_cpr_mx = { 783 .name = "qhs_cpr_mx", 784 .id = SM7150_SLAVE_RBCPR_MX_CFG, 785 .channels = 1, 786 .buswidth = 4, 787}; 788 789static struct qcom_icc_node qhs_crypto0_cfg = { 790 .name = "qhs_crypto0_cfg", 791 .id = SM7150_SLAVE_CRYPTO_0_CFG, 792 .channels = 1, 793 .buswidth = 4, 794}; 795 796static struct qcom_icc_node qhs_ddrss_cfg = { 797 .name = "qhs_ddrss_cfg", 798 .id = SM7150_SLAVE_CNOC_DDRSS, 799 .channels = 1, 800 .buswidth = 4, 801 .num_links = 1, 802 .links = { SM7150_MASTER_CNOC_DC_NOC }, 803}; 804 805static struct qcom_icc_node qhs_display_cfg = { 806 .name = "qhs_display_cfg", 807 .id = SM7150_SLAVE_DISPLAY_CFG, 808 .channels = 1, 809 .buswidth = 4, 810}; 811 812static struct qcom_icc_node qhs_display_throttle_cfg = { 813 .name = "qhs_display_throttle_cfg", 814 .id = SM7150_SLAVE_DISPLAY_THROTTLE_CFG, 815 .channels = 1, 816 .buswidth = 4, 817}; 818 819static struct qcom_icc_node qhs_emmc_cfg = { 820 .name = "qhs_emmc_cfg", 821 .id = SM7150_SLAVE_EMMC_CFG, 822 .channels = 1, 823 .buswidth = 4, 824}; 825 826static struct qcom_icc_node qhs_glm = { 827 .name = "qhs_glm", 828 .id = SM7150_SLAVE_GLM, 829 .channels = 1, 830 .buswidth = 4, 831}; 832 833static struct qcom_icc_node qhs_gpuss_cfg = { 834 .name = "qhs_gpuss_cfg", 835 .id = SM7150_SLAVE_GRAPHICS_3D_CFG, 836 .channels = 1, 837 .buswidth = 8, 838}; 839 840static struct qcom_icc_node qhs_imem_cfg = { 841 .name = "qhs_imem_cfg", 842 .id = SM7150_SLAVE_IMEM_CFG, 843 .channels = 1, 844 .buswidth = 4, 845}; 846 847static struct qcom_icc_node qhs_ipa = { 848 .name = "qhs_ipa", 849 .id = SM7150_SLAVE_IPA_CFG, 850 .channels = 1, 851 .buswidth = 4, 852}; 853 854static struct qcom_icc_node qhs_mnoc_cfg = { 855 .name = "qhs_mnoc_cfg", 856 .id = SM7150_SLAVE_CNOC_MNOC_CFG, 857 .channels = 1, 858 .buswidth = 4, 859 .num_links = 1, 860 .links = { SM7150_MASTER_CNOC_MNOC_CFG }, 861}; 862 863static struct qcom_icc_node qhs_pcie_cfg = { 864 .name = "qhs_pcie_cfg", 865 .id = SM7150_SLAVE_PCIE_CFG, 866 .channels = 1, 867 .buswidth = 4, 868}; 869 870static struct qcom_icc_node qhs_pdm = { 871 .name = "qhs_pdm", 872 .id = SM7150_SLAVE_PDM, 873 .channels = 1, 874 .buswidth = 4, 875}; 876 877static struct qcom_icc_node qhs_pimem_cfg = { 878 .name = "qhs_pimem_cfg", 879 .id = SM7150_SLAVE_PIMEM_CFG, 880 .channels = 1, 881 .buswidth = 4, 882}; 883 884static struct qcom_icc_node qhs_prng = { 885 .name = "qhs_prng", 886 .id = SM7150_SLAVE_PRNG, 887 .channels = 1, 888 .buswidth = 4, 889}; 890 891static struct qcom_icc_node qhs_qdss_cfg = { 892 .name = "qhs_qdss_cfg", 893 .id = SM7150_SLAVE_QDSS_CFG, 894 .channels = 1, 895 .buswidth = 4, 896}; 897 898static struct qcom_icc_node qhs_qupv3_center = { 899 .name = "qhs_qupv3_center", 900 .id = SM7150_SLAVE_QUP_0, 901 .channels = 1, 902 .buswidth = 4, 903}; 904 905static struct qcom_icc_node qhs_qupv3_north = { 906 .name = "qhs_qupv3_north", 907 .id = SM7150_SLAVE_QUP_1, 908 .channels = 1, 909 .buswidth = 4, 910}; 911 912static struct qcom_icc_node qhs_sdc2 = { 913 .name = "qhs_sdc2", 914 .id = SM7150_SLAVE_SDCC_2, 915 .channels = 1, 916 .buswidth = 4, 917}; 918 919static struct qcom_icc_node qhs_sdc4 = { 920 .name = "qhs_sdc4", 921 .id = SM7150_SLAVE_SDCC_4, 922 .channels = 1, 923 .buswidth = 4, 924}; 925 926static struct qcom_icc_node qhs_snoc_cfg = { 927 .name = "qhs_snoc_cfg", 928 .id = SM7150_SLAVE_SNOC_CFG, 929 .channels = 1, 930 .buswidth = 4, 931 .num_links = 1, 932 .links = { SM7150_MASTER_SNOC_CFG }, 933}; 934 935static struct qcom_icc_node qhs_spdm = { 936 .name = "qhs_spdm", 937 .id = SM7150_SLAVE_SPDM_WRAPPER, 938 .channels = 1, 939 .buswidth = 4, 940}; 941 942static struct qcom_icc_node qhs_tcsr = { 943 .name = "qhs_tcsr", 944 .id = SM7150_SLAVE_TCSR, 945 .channels = 1, 946 .buswidth = 4, 947}; 948 949static struct qcom_icc_node qhs_tlmm_north = { 950 .name = "qhs_tlmm_north", 951 .id = SM7150_SLAVE_TLMM_NORTH, 952 .channels = 1, 953 .buswidth = 4, 954}; 955 956static struct qcom_icc_node qhs_tlmm_south = { 957 .name = "qhs_tlmm_south", 958 .id = SM7150_SLAVE_TLMM_SOUTH, 959 .channels = 1, 960 .buswidth = 4, 961}; 962 963static struct qcom_icc_node qhs_tlmm_west = { 964 .name = "qhs_tlmm_west", 965 .id = SM7150_SLAVE_TLMM_WEST, 966 .channels = 1, 967 .buswidth = 4, 968}; 969 970static struct qcom_icc_node qhs_tsif = { 971 .name = "qhs_tsif", 972 .id = SM7150_SLAVE_TSIF, 973 .channels = 1, 974 .buswidth = 4, 975}; 976 977static struct qcom_icc_node qhs_ufs_mem_cfg = { 978 .name = "qhs_ufs_mem_cfg", 979 .id = SM7150_SLAVE_UFS_MEM_CFG, 980 .channels = 1, 981 .buswidth = 4, 982}; 983 984static struct qcom_icc_node qhs_usb3_0 = { 985 .name = "qhs_usb3_0", 986 .id = SM7150_SLAVE_USB3, 987 .channels = 1, 988 .buswidth = 4, 989}; 990 991static struct qcom_icc_node qhs_venus_cfg = { 992 .name = "qhs_venus_cfg", 993 .id = SM7150_SLAVE_VENUS_CFG, 994 .channels = 1, 995 .buswidth = 4, 996}; 997 998static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { 999 .name = "qhs_venus_cvp_throttle_cfg", 1000 .id = SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, 1001 .channels = 1, 1002 .buswidth = 4, 1003}; 1004 1005static struct qcom_icc_node qhs_venus_throttle_cfg = { 1006 .name = "qhs_venus_throttle_cfg", 1007 .id = SM7150_SLAVE_VENUS_THROTTLE_CFG, 1008 .channels = 1, 1009 .buswidth = 4, 1010}; 1011 1012static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1013 .name = "qhs_vsense_ctrl_cfg", 1014 .id = SM7150_SLAVE_VSENSE_CTRL_CFG, 1015 .channels = 1, 1016 .buswidth = 4, 1017}; 1018 1019static struct qcom_icc_node qns_cnoc_a2noc = { 1020 .name = "qns_cnoc_a2noc", 1021 .id = SM7150_SLAVE_CNOC_A2NOC, 1022 .channels = 1, 1023 .buswidth = 8, 1024 .num_links = 1, 1025 .links = { SM7150_MASTER_CNOC_A2NOC }, 1026}; 1027 1028static struct qcom_icc_node srvc_cnoc = { 1029 .name = "srvc_cnoc", 1030 .id = SM7150_SLAVE_SERVICE_CNOC, 1031 .channels = 1, 1032 .buswidth = 4, 1033}; 1034 1035static struct qcom_icc_node qhs_gemnoc = { 1036 .name = "qhs_gemnoc", 1037 .id = SM7150_SLAVE_GEM_NOC_CFG, 1038 .channels = 1, 1039 .buswidth = 4, 1040 .num_links = 1, 1041 .links = { SM7150_MASTER_GEM_NOC_CFG }, 1042}; 1043 1044static struct qcom_icc_node qhs_llcc = { 1045 .name = "qhs_llcc", 1046 .id = SM7150_SLAVE_LLCC_CFG, 1047 .channels = 1, 1048 .buswidth = 4, 1049}; 1050 1051static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1052 .name = "qhs_mdsp_ms_mpu_cfg", 1053 .id = SM7150_SLAVE_MSS_PROC_MS_MPU_CFG, 1054 .channels = 1, 1055 .buswidth = 4, 1056}; 1057 1058static struct qcom_icc_node qns_gem_noc_snoc = { 1059 .name = "qns_gem_noc_snoc", 1060 .id = SM7150_SLAVE_GEM_NOC_SNOC, 1061 .channels = 1, 1062 .buswidth = 8, 1063 .num_links = 1, 1064 .links = { SM7150_MASTER_GEM_NOC_SNOC }, 1065}; 1066 1067static struct qcom_icc_node qns_llcc = { 1068 .name = "qns_llcc", 1069 .id = SM7150_SLAVE_LLCC, 1070 .channels = 2, 1071 .buswidth = 16, 1072 .num_links = 1, 1073 .links = { SM7150_MASTER_LLCC }, 1074}; 1075 1076static struct qcom_icc_node srvc_gemnoc = { 1077 .name = "srvc_gemnoc", 1078 .id = SM7150_SLAVE_SERVICE_GEM_NOC, 1079 .channels = 1, 1080 .buswidth = 4, 1081}; 1082 1083static struct qcom_icc_node ebi = { 1084 .name = "ebi", 1085 .id = SM7150_SLAVE_EBI_CH0, 1086 .channels = 2, 1087 .buswidth = 4, 1088}; 1089 1090static struct qcom_icc_node qns2_mem_noc = { 1091 .name = "qns2_mem_noc", 1092 .id = SM7150_SLAVE_MNOC_SF_MEM_NOC, 1093 .channels = 1, 1094 .buswidth = 32, 1095 .num_links = 1, 1096 .links = { SM7150_MASTER_MNOC_SF_MEM_NOC }, 1097}; 1098 1099static struct qcom_icc_node qns_mem_noc_hf = { 1100 .name = "qns_mem_noc_hf", 1101 .id = SM7150_SLAVE_MNOC_HF_MEM_NOC, 1102 .channels = 2, 1103 .buswidth = 32, 1104 .num_links = 1, 1105 .links = { SM7150_MASTER_MNOC_HF_MEM_NOC }, 1106}; 1107 1108static struct qcom_icc_node srvc_mnoc = { 1109 .name = "srvc_mnoc", 1110 .id = SM7150_SLAVE_SERVICE_MNOC, 1111 .channels = 1, 1112 .buswidth = 4, 1113}; 1114 1115static struct qcom_icc_node qhs_apss = { 1116 .name = "qhs_apss", 1117 .id = SM7150_SLAVE_APPSS, 1118 .channels = 1, 1119 .buswidth = 8, 1120}; 1121 1122static struct qcom_icc_node qns_cnoc = { 1123 .name = "qns_cnoc", 1124 .id = SM7150_SNOC_CNOC_SLV, 1125 .channels = 1, 1126 .buswidth = 8, 1127 .num_links = 1, 1128 .links = { SM7150_SNOC_CNOC_MAS }, 1129}; 1130 1131static struct qcom_icc_node qns_gemnoc_gc = { 1132 .name = "qns_gemnoc_gc", 1133 .id = SM7150_SLAVE_SNOC_GEM_NOC_GC, 1134 .channels = 1, 1135 .buswidth = 8, 1136 .num_links = 1, 1137 .links = { SM7150_MASTER_SNOC_GC_MEM_NOC }, 1138}; 1139 1140static struct qcom_icc_node qns_gemnoc_sf = { 1141 .name = "qns_gemnoc_sf", 1142 .id = SM7150_SLAVE_SNOC_GEM_NOC_SF, 1143 .channels = 1, 1144 .buswidth = 16, 1145 .num_links = 1, 1146 .links = { SM7150_MASTER_SNOC_SF_MEM_NOC }, 1147}; 1148 1149static struct qcom_icc_node qxs_imem = { 1150 .name = "qxs_imem", 1151 .id = SM7150_SLAVE_OCIMEM, 1152 .channels = 1, 1153 .buswidth = 8, 1154}; 1155 1156static struct qcom_icc_node qxs_pimem = { 1157 .name = "qxs_pimem", 1158 .id = SM7150_SLAVE_PIMEM, 1159 .channels = 1, 1160 .buswidth = 8, 1161}; 1162 1163static struct qcom_icc_node srvc_snoc = { 1164 .name = "srvc_snoc", 1165 .id = SM7150_SLAVE_SERVICE_SNOC, 1166 .channels = 1, 1167 .buswidth = 4, 1168}; 1169 1170static struct qcom_icc_node xs_qdss_stm = { 1171 .name = "xs_qdss_stm", 1172 .id = SM7150_SLAVE_QDSS_STM, 1173 .channels = 1, 1174 .buswidth = 4, 1175}; 1176 1177static struct qcom_icc_node xs_sys_tcu_cfg = { 1178 .name = "xs_sys_tcu_cfg", 1179 .id = SM7150_SLAVE_TCU, 1180 .channels = 1, 1181 .buswidth = 8, 1182}; 1183 1184static struct qcom_icc_bcm bcm_acv = { 1185 .name = "ACV", 1186 .enable_mask = BIT(3), 1187 .keepalive = false, 1188 .num_nodes = 1, 1189 .nodes = { &ebi }, 1190}; 1191 1192static struct qcom_icc_bcm bcm_mc0 = { 1193 .name = "MC0", 1194 .keepalive = true, 1195 .num_nodes = 1, 1196 .nodes = { &ebi }, 1197}; 1198 1199static struct qcom_icc_bcm bcm_sh0 = { 1200 .name = "SH0", 1201 .keepalive = true, 1202 .num_nodes = 1, 1203 .nodes = { &qns_llcc }, 1204}; 1205 1206static struct qcom_icc_bcm bcm_mm0 = { 1207 .name = "MM0", 1208 .keepalive = true, 1209 .num_nodes = 1, 1210 .nodes = { &qns_mem_noc_hf }, 1211}; 1212 1213static struct qcom_icc_bcm bcm_mm1 = { 1214 .name = "MM1", 1215 .keepalive = true, 1216 .num_nodes = 8, 1217 .nodes = { &qxm_camnoc_hf0_uncomp, 1218 &qxm_camnoc_rt_uncomp, 1219 &qxm_camnoc_sf_uncomp, 1220 &qxm_camnoc_nrt_uncomp, 1221 &qxm_camnoc_hf, 1222 &qxm_camnoc_rt, 1223 &qxm_mdp0, 1224 &qxm_mdp1 1225 }, 1226}; 1227 1228static struct qcom_icc_bcm bcm_sh2 = { 1229 .name = "SH2", 1230 .keepalive = false, 1231 .num_nodes = 1, 1232 .nodes = { &qns_gem_noc_snoc }, 1233}; 1234 1235static struct qcom_icc_bcm bcm_sh3 = { 1236 .name = "SH3", 1237 .keepalive = false, 1238 .num_nodes = 1, 1239 .nodes = { &acm_sys_tcu }, 1240}; 1241 1242static struct qcom_icc_bcm bcm_mm2 = { 1243 .name = "MM2", 1244 .keepalive = false, 1245 .num_nodes = 2, 1246 .nodes = { &qxm_camnoc_nrt, 1247 &qns2_mem_noc 1248 }, 1249}; 1250 1251static struct qcom_icc_bcm bcm_mm3 = { 1252 .name = "MM3", 1253 .keepalive = false, 1254 .num_nodes = 5, 1255 .nodes = { &qxm_camnoc_sf, 1256 &qxm_rot, 1257 &qxm_venus0, 1258 &qxm_venus1, 1259 &qxm_venus_arm9 1260 }, 1261}; 1262 1263static struct qcom_icc_bcm bcm_sh5 = { 1264 .name = "SH5", 1265 .keepalive = false, 1266 .num_nodes = 1, 1267 .nodes = { &acm_apps }, 1268}; 1269 1270static struct qcom_icc_bcm bcm_sn0 = { 1271 .name = "SN0", 1272 .keepalive = true, 1273 .num_nodes = 1, 1274 .nodes = { &qns_gemnoc_sf }, 1275}; 1276 1277static struct qcom_icc_bcm bcm_sh8 = { 1278 .name = "SH8", 1279 .keepalive = false, 1280 .num_nodes = 1, 1281 .nodes = { &qns_cdsp_gemnoc }, 1282}; 1283 1284static struct qcom_icc_bcm bcm_sh10 = { 1285 .name = "SH10", 1286 .keepalive = false, 1287 .num_nodes = 1, 1288 .nodes = { &qnm_npu }, 1289}; 1290 1291static struct qcom_icc_bcm bcm_ce0 = { 1292 .name = "CE0", 1293 .keepalive = false, 1294 .num_nodes = 1, 1295 .nodes = { &qxm_crypto }, 1296}; 1297 1298static struct qcom_icc_bcm bcm_cn0 = { 1299 .name = "CN0", 1300 .keepalive = true, 1301 .num_nodes = 54, 1302 .nodes = { &qhm_tsif, 1303 &xm_emmc, 1304 &xm_sdc2, 1305 &xm_sdc4, 1306 &qhm_spdm, 1307 &qnm_snoc, 1308 &qhs_a1_noc_cfg, 1309 &qhs_a2_noc_cfg, 1310 &qhs_ahb2phy_north, 1311 &qhs_ahb2phy_south, 1312 &qhs_ahb2phy_west, 1313 &qhs_aop, 1314 &qhs_aoss, 1315 &qhs_camera_cfg, 1316 &qhs_camera_nrt_thrott_cfg, 1317 &qhs_camera_rt_throttle_cfg, 1318 &qhs_clk_ctl, 1319 &qhs_compute_dsp_cfg, 1320 &qhs_cpr_cx, 1321 &qhs_cpr_mx, 1322 &qhs_crypto0_cfg, 1323 &qhs_ddrss_cfg, 1324 &qhs_display_cfg, 1325 &qhs_display_throttle_cfg, 1326 &qhs_emmc_cfg, 1327 &qhs_glm, 1328 &qhs_gpuss_cfg, 1329 &qhs_imem_cfg, 1330 &qhs_ipa, 1331 &qhs_mnoc_cfg, 1332 &qhs_pcie_cfg, 1333 &qhs_pdm, 1334 &qhs_pimem_cfg, 1335 &qhs_prng, 1336 &qhs_qdss_cfg, 1337 &qhs_qupv3_center, 1338 &qhs_qupv3_north, 1339 &qhs_sdc2, 1340 &qhs_sdc4, 1341 &qhs_snoc_cfg, 1342 &qhs_spdm, 1343 &qhs_tcsr, 1344 &qhs_tlmm_north, 1345 &qhs_tlmm_south, 1346 &qhs_tlmm_west, 1347 &qhs_tsif, 1348 &qhs_ufs_mem_cfg, 1349 &qhs_usb3_0, 1350 &qhs_venus_cfg, 1351 &qhs_venus_cvp_throttle_cfg, 1352 &qhs_venus_throttle_cfg, 1353 &qhs_vsense_ctrl_cfg, 1354 &qns_cnoc_a2noc, 1355 &srvc_cnoc 1356 }, 1357}; 1358 1359static struct qcom_icc_bcm bcm_qup0 = { 1360 .name = "QUP0", 1361 .keepalive = false, 1362 .num_nodes = 2, 1363 .nodes = { &qhm_qup_center, 1364 &qhm_qup_north 1365 }, 1366}; 1367 1368static struct qcom_icc_bcm bcm_sn1 = { 1369 .name = "SN1", 1370 .keepalive = false, 1371 .num_nodes = 1, 1372 .nodes = { &qxs_imem }, 1373}; 1374 1375static struct qcom_icc_bcm bcm_sn2 = { 1376 .name = "SN2", 1377 .keepalive = false, 1378 .num_nodes = 1, 1379 .nodes = { &qns_gemnoc_gc }, 1380}; 1381 1382static struct qcom_icc_bcm bcm_sn4 = { 1383 .name = "SN4", 1384 .keepalive = false, 1385 .num_nodes = 1, 1386 .nodes = { &qxs_pimem }, 1387}; 1388 1389static struct qcom_icc_bcm bcm_sn9 = { 1390 .name = "SN9", 1391 .keepalive = false, 1392 .num_nodes = 2, 1393 .nodes = { &qnm_aggre1_noc, 1394 &qns_a1noc_snoc 1395 }, 1396}; 1397 1398static struct qcom_icc_bcm bcm_sn11 = { 1399 .name = "SN11", 1400 .keepalive = false, 1401 .num_nodes = 2, 1402 .nodes = { &qnm_aggre2_noc, 1403 &qns_a2noc_snoc 1404 }, 1405}; 1406 1407static struct qcom_icc_bcm bcm_sn12 = { 1408 .name = "SN12", 1409 .keepalive = false, 1410 .num_nodes = 2, 1411 .nodes = { &qxm_pimem, 1412 &xm_gic 1413 }, 1414}; 1415 1416static struct qcom_icc_bcm bcm_sn14 = { 1417 .name = "SN14", 1418 .keepalive = false, 1419 .num_nodes = 1, 1420 .nodes = { &qns_pcie_gemnoc }, 1421}; 1422 1423static struct qcom_icc_bcm bcm_sn15 = { 1424 .name = "SN15", 1425 .keepalive = false, 1426 .num_nodes = 1, 1427 .nodes = { &qnm_gemnoc }, 1428}; 1429 1430static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1431 &bcm_cn0, 1432 &bcm_qup0, 1433 &bcm_sn9, 1434}; 1435 1436static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1437 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1438 [MASTER_QUP_0] = &qhm_qup_center, 1439 [MASTER_TSIF] = &qhm_tsif, 1440 [MASTER_EMMC] = &xm_emmc, 1441 [MASTER_SDCC_2] = &xm_sdc2, 1442 [MASTER_SDCC_4] = &xm_sdc4, 1443 [MASTER_UFS_MEM] = &xm_ufs_mem, 1444 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1445 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1446}; 1447 1448static const struct qcom_icc_desc sm7150_aggre1_noc = { 1449 .nodes = aggre1_noc_nodes, 1450 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1451 .bcms = aggre1_noc_bcms, 1452 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1453}; 1454 1455static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1456 &bcm_ce0, 1457 &bcm_qup0, 1458 &bcm_sn11, 1459 &bcm_sn14, 1460}; 1461 1462static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1463 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1464 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1465 [MASTER_QUP_1] = &qhm_qup_north, 1466 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1467 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1468 [MASTER_IPA] = &qxm_ipa, 1469 [MASTER_PCIE] = &xm_pcie3_0, 1470 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1471 [MASTER_USB3] = &xm_usb3_0, 1472 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1473 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, 1474 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1475}; 1476 1477static const struct qcom_icc_desc sm7150_aggre2_noc = { 1478 .nodes = aggre2_noc_nodes, 1479 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1480 .bcms = aggre2_noc_bcms, 1481 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1482}; 1483 1484static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1485 &bcm_mm1, 1486}; 1487 1488static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1489 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1490 [MASTER_CAMNOC_RT_UNCOMP] = &qxm_camnoc_rt_uncomp, 1491 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1492 [MASTER_CAMNOC_NRT_UNCOMP] = &qxm_camnoc_nrt_uncomp, 1493 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1494}; 1495 1496static const struct qcom_icc_desc sm7150_camnoc_virt = { 1497 .nodes = camnoc_virt_nodes, 1498 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1499 .bcms = camnoc_virt_bcms, 1500 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1501}; 1502 1503static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1504 &bcm_sh10, 1505 &bcm_sh8, 1506}; 1507 1508static struct qcom_icc_node * const compute_noc_nodes[] = { 1509 [MASTER_NPU] = &qnm_npu, 1510 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1511}; 1512 1513static const struct qcom_icc_desc sm7150_compute_noc = { 1514 .nodes = compute_noc_nodes, 1515 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1516 .bcms = compute_noc_bcms, 1517 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1518}; 1519 1520static struct qcom_icc_bcm * const config_noc_bcms[] = { 1521 &bcm_cn0, 1522}; 1523 1524static struct qcom_icc_node * const config_noc_nodes[] = { 1525 [MASTER_SPDM] = &qhm_spdm, 1526 [SNOC_CNOC_MAS] = &qnm_snoc, 1527 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1528 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1529 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1530 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy_north, 1531 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south, 1532 [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west, 1533 [SLAVE_AOP] = &qhs_aop, 1534 [SLAVE_AOSS] = &qhs_aoss, 1535 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1536 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, 1537 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1538 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1539 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 1540 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1541 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1542 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1543 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1544 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1545 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1546 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1547 [SLAVE_GLM] = &qhs_glm, 1548 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1549 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1550 [SLAVE_IPA_CFG] = &qhs_ipa, 1551 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1552 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, 1553 [SLAVE_PDM] = &qhs_pdm, 1554 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1555 [SLAVE_PRNG] = &qhs_prng, 1556 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1557 [SLAVE_QUP_0] = &qhs_qupv3_center, 1558 [SLAVE_QUP_1] = &qhs_qupv3_north, 1559 [SLAVE_SDCC_2] = &qhs_sdc2, 1560 [SLAVE_SDCC_4] = &qhs_sdc4, 1561 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1562 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1563 [SLAVE_TCSR] = &qhs_tcsr, 1564 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1565 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1566 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1567 [SLAVE_TSIF] = &qhs_tsif, 1568 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1569 [SLAVE_USB3] = &qhs_usb3_0, 1570 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1571 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, 1572 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1573 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1574 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1575 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1576}; 1577 1578static const struct qcom_icc_desc sm7150_config_noc = { 1579 .nodes = config_noc_nodes, 1580 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1581 .bcms = config_noc_bcms, 1582 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1583}; 1584 1585static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1586}; 1587 1588static struct qcom_icc_node * const dc_noc_nodes[] = { 1589 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1590 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 1591 [SLAVE_LLCC_CFG] = &qhs_llcc, 1592}; 1593 1594static const struct qcom_icc_desc sm7150_dc_noc = { 1595 .nodes = dc_noc_nodes, 1596 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1597 .bcms = dc_noc_bcms, 1598 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1599}; 1600 1601static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1602 &bcm_sh0, 1603 &bcm_sh2, 1604 &bcm_sh3, 1605 &bcm_sh5, 1606}; 1607 1608static struct qcom_icc_node * const gem_noc_nodes[] = { 1609 [MASTER_AMPSS_M0] = &acm_apps, 1610 [MASTER_SYS_TCU] = &acm_sys_tcu, 1611 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1612 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1613 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1614 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1615 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie, 1616 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1617 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1618 [MASTER_GRAPHICS_3D] = &qxm_gpu, 1619 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1620 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1621 [SLAVE_LLCC] = &qns_llcc, 1622 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1623}; 1624 1625static const struct qcom_icc_desc sm7150_gem_noc = { 1626 .nodes = gem_noc_nodes, 1627 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1628 .bcms = gem_noc_bcms, 1629 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1630}; 1631 1632static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1633 &bcm_acv, 1634 &bcm_mc0, 1635}; 1636 1637static struct qcom_icc_node * const mc_virt_nodes[] = { 1638 [MASTER_LLCC] = &llcc_mc, 1639 [SLAVE_EBI_CH0] = &ebi, 1640}; 1641 1642static const struct qcom_icc_desc sm7150_mc_virt = { 1643 .nodes = mc_virt_nodes, 1644 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1645 .bcms = mc_virt_bcms, 1646 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1647}; 1648 1649static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1650 &bcm_mm0, 1651 &bcm_mm1, 1652 &bcm_mm2, 1653 &bcm_mm3, 1654}; 1655 1656static struct qcom_icc_node * const mmss_noc_nodes[] = { 1657 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1658 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf, 1659 [MASTER_CAMNOC_NRT] = &qxm_camnoc_nrt, 1660 [MASTER_CAMNOC_RT] = &qxm_camnoc_rt, 1661 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1662 [MASTER_MDP_PORT0] = &qxm_mdp0, 1663 [MASTER_MDP_PORT1] = &qxm_mdp1, 1664 [MASTER_ROTATOR] = &qxm_rot, 1665 [MASTER_VIDEO_P0] = &qxm_venus0, 1666 [MASTER_VIDEO_P1] = &qxm_venus1, 1667 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1668 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1669 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1670 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1671}; 1672 1673static const struct qcom_icc_desc sm7150_mmss_noc = { 1674 .nodes = mmss_noc_nodes, 1675 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1676 .bcms = mmss_noc_bcms, 1677 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1678}; 1679 1680static struct qcom_icc_bcm * const system_noc_bcms[] = { 1681 &bcm_sn0, 1682 &bcm_sn1, 1683 &bcm_sn11, 1684 &bcm_sn12, 1685 &bcm_sn15, 1686 &bcm_sn2, 1687 &bcm_sn4, 1688 &bcm_sn9, 1689}; 1690 1691static struct qcom_icc_node * const system_noc_nodes[] = { 1692 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1693 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1694 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1695 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1696 [MASTER_PIMEM] = &qxm_pimem, 1697 [MASTER_GIC] = &xm_gic, 1698 [SLAVE_APPSS] = &qhs_apss, 1699 [SNOC_CNOC_SLV] = &qns_cnoc, 1700 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1701 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1702 [SLAVE_OCIMEM] = &qxs_imem, 1703 [SLAVE_PIMEM] = &qxs_pimem, 1704 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1705 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1706 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1707}; 1708 1709static const struct qcom_icc_desc sm7150_system_noc = { 1710 .nodes = system_noc_nodes, 1711 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1712 .bcms = system_noc_bcms, 1713 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1714}; 1715 1716static const struct of_device_id qnoc_of_match[] = { 1717 { .compatible = "qcom,sm7150-aggre1-noc", .data = &sm7150_aggre1_noc }, 1718 { .compatible = "qcom,sm7150-aggre2-noc", .data = &sm7150_aggre2_noc }, 1719 { .compatible = "qcom,sm7150-camnoc-virt", .data = &sm7150_camnoc_virt }, 1720 { .compatible = "qcom,sm7150-compute-noc", .data = &sm7150_compute_noc }, 1721 { .compatible = "qcom,sm7150-config-noc", .data = &sm7150_config_noc }, 1722 { .compatible = "qcom,sm7150-dc-noc", .data = &sm7150_dc_noc }, 1723 { .compatible = "qcom,sm7150-gem-noc", .data = &sm7150_gem_noc }, 1724 { .compatible = "qcom,sm7150-mc-virt", .data = &sm7150_mc_virt }, 1725 { .compatible = "qcom,sm7150-mmss-noc", .data = &sm7150_mmss_noc }, 1726 { .compatible = "qcom,sm7150-system-noc", .data = &sm7150_system_noc }, 1727 { } 1728}; 1729MODULE_DEVICE_TABLE(of, qnoc_of_match); 1730 1731static struct platform_driver qnoc_driver = { 1732 .probe = qcom_icc_rpmh_probe, 1733 .remove_new = qcom_icc_rpmh_remove, 1734 .driver = { 1735 .name = "qnoc-sm7150", 1736 .of_match_table = qnoc_of_match, 1737 .sync_state = icc_sync_state, 1738 }, 1739}; 1740 1741static int __init qnoc_driver_init(void) 1742{ 1743 return platform_driver_register(&qnoc_driver); 1744} 1745core_initcall(qnoc_driver_init); 1746 1747static void __exit qnoc_driver_exit(void) 1748{ 1749 platform_driver_unregister(&qnoc_driver); 1750} 1751module_exit(qnoc_driver_exit); 1752 1753MODULE_DESCRIPTION("Qualcomm SM7150 NoC driver"); 1754MODULE_LICENSE("GPL"); 1755