1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2022, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/device.h> 7#include <linux/interconnect.h> 8#include <linux/interconnect-provider.h> 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 13 14#include "bcm-voter.h" 15#include "icc-rpmh.h" 16#include "sdm670.h" 17 18static struct qcom_icc_node qhm_a1noc_cfg = { 19 .name = "qhm_a1noc_cfg", 20 .id = SDM670_MASTER_A1NOC_CFG, 21 .channels = 1, 22 .buswidth = 4, 23 .num_links = 1, 24 .links = { SDM670_SLAVE_SERVICE_A1NOC }, 25}; 26 27static struct qcom_icc_node qhm_qup1 = { 28 .name = "qhm_qup1", 29 .id = SDM670_MASTER_BLSP_1, 30 .channels = 1, 31 .buswidth = 4, 32 .num_links = 1, 33 .links = { SDM670_SLAVE_A1NOC_SNOC }, 34}; 35 36static struct qcom_icc_node qhm_tsif = { 37 .name = "qhm_tsif", 38 .id = SDM670_MASTER_TSIF, 39 .channels = 1, 40 .buswidth = 4, 41 .num_links = 1, 42 .links = { SDM670_SLAVE_A1NOC_SNOC }, 43}; 44 45static struct qcom_icc_node xm_emmc = { 46 .name = "xm_emmc", 47 .id = SDM670_MASTER_EMMC, 48 .channels = 1, 49 .buswidth = 8, 50 .num_links = 1, 51 .links = { SDM670_SLAVE_A1NOC_SNOC }, 52}; 53 54static struct qcom_icc_node xm_sdc2 = { 55 .name = "xm_sdc2", 56 .id = SDM670_MASTER_SDCC_2, 57 .channels = 1, 58 .buswidth = 8, 59 .num_links = 1, 60 .links = { SDM670_SLAVE_A1NOC_SNOC }, 61}; 62 63static struct qcom_icc_node xm_sdc4 = { 64 .name = "xm_sdc4", 65 .id = SDM670_MASTER_SDCC_4, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { SDM670_SLAVE_A1NOC_SNOC }, 70}; 71 72static struct qcom_icc_node xm_ufs_mem = { 73 .name = "xm_ufs_mem", 74 .id = SDM670_MASTER_UFS_MEM, 75 .channels = 1, 76 .buswidth = 8, 77 .num_links = 1, 78 .links = { SDM670_SLAVE_A1NOC_SNOC }, 79}; 80 81static struct qcom_icc_node qhm_a2noc_cfg = { 82 .name = "qhm_a2noc_cfg", 83 .id = SDM670_MASTER_A2NOC_CFG, 84 .channels = 1, 85 .buswidth = 4, 86 .num_links = 1, 87 .links = { SDM670_SLAVE_SERVICE_A2NOC }, 88}; 89 90static struct qcom_icc_node qhm_qdss_bam = { 91 .name = "qhm_qdss_bam", 92 .id = SDM670_MASTER_QDSS_BAM, 93 .channels = 1, 94 .buswidth = 4, 95 .num_links = 1, 96 .links = { SDM670_SLAVE_A2NOC_SNOC }, 97}; 98 99static struct qcom_icc_node qhm_qup2 = { 100 .name = "qhm_qup2", 101 .id = SDM670_MASTER_BLSP_2, 102 .channels = 1, 103 .buswidth = 4, 104 .num_links = 1, 105 .links = { SDM670_SLAVE_A2NOC_SNOC }, 106}; 107 108static struct qcom_icc_node qnm_cnoc = { 109 .name = "qnm_cnoc", 110 .id = SDM670_MASTER_CNOC_A2NOC, 111 .channels = 1, 112 .buswidth = 8, 113 .num_links = 1, 114 .links = { SDM670_SLAVE_A2NOC_SNOC }, 115}; 116 117static struct qcom_icc_node qxm_crypto = { 118 .name = "qxm_crypto", 119 .id = SDM670_MASTER_CRYPTO_CORE_0, 120 .channels = 1, 121 .buswidth = 8, 122 .num_links = 1, 123 .links = { SDM670_SLAVE_A2NOC_SNOC }, 124}; 125 126static struct qcom_icc_node qxm_ipa = { 127 .name = "qxm_ipa", 128 .id = SDM670_MASTER_IPA, 129 .channels = 1, 130 .buswidth = 8, 131 .num_links = 1, 132 .links = { SDM670_SLAVE_A2NOC_SNOC }, 133}; 134 135static struct qcom_icc_node xm_qdss_etr = { 136 .name = "xm_qdss_etr", 137 .id = SDM670_MASTER_QDSS_ETR, 138 .channels = 1, 139 .buswidth = 8, 140 .num_links = 1, 141 .links = { SDM670_SLAVE_A2NOC_SNOC }, 142}; 143 144static struct qcom_icc_node xm_usb3_0 = { 145 .name = "xm_usb3_0", 146 .id = SDM670_MASTER_USB3, 147 .channels = 1, 148 .buswidth = 8, 149 .num_links = 1, 150 .links = { SDM670_SLAVE_A2NOC_SNOC }, 151}; 152 153static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 154 .name = "qxm_camnoc_hf0_uncomp", 155 .id = SDM670_MASTER_CAMNOC_HF0_UNCOMP, 156 .channels = 1, 157 .buswidth = 32, 158 .num_links = 1, 159 .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, 160}; 161 162static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 163 .name = "qxm_camnoc_hf1_uncomp", 164 .id = SDM670_MASTER_CAMNOC_HF1_UNCOMP, 165 .channels = 1, 166 .buswidth = 32, 167 .num_links = 1, 168 .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, 169}; 170 171static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 172 .name = "qxm_camnoc_sf_uncomp", 173 .id = SDM670_MASTER_CAMNOC_SF_UNCOMP, 174 .channels = 1, 175 .buswidth = 32, 176 .num_links = 1, 177 .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, 178}; 179 180static struct qcom_icc_node qhm_spdm = { 181 .name = "qhm_spdm", 182 .id = SDM670_MASTER_SPDM, 183 .channels = 1, 184 .buswidth = 4, 185 .num_links = 1, 186 .links = { SDM670_SLAVE_CNOC_A2NOC }, 187}; 188 189static struct qcom_icc_node qnm_snoc = { 190 .name = "qnm_snoc", 191 .id = SDM670_MASTER_SNOC_CNOC, 192 .channels = 1, 193 .buswidth = 8, 194 .num_links = 38, 195 .links = { SDM670_SLAVE_TLMM_SOUTH, 196 SDM670_SLAVE_CAMERA_CFG, 197 SDM670_SLAVE_SDCC_4, 198 SDM670_SLAVE_SDCC_2, 199 SDM670_SLAVE_CNOC_MNOC_CFG, 200 SDM670_SLAVE_UFS_MEM_CFG, 201 SDM670_SLAVE_GLM, 202 SDM670_SLAVE_PDM, 203 SDM670_SLAVE_A2NOC_CFG, 204 SDM670_SLAVE_QDSS_CFG, 205 SDM670_SLAVE_DISPLAY_CFG, 206 SDM670_SLAVE_TCSR, 207 SDM670_SLAVE_DCC_CFG, 208 SDM670_SLAVE_CNOC_DDRSS, 209 SDM670_SLAVE_SNOC_CFG, 210 SDM670_SLAVE_SOUTH_PHY_CFG, 211 SDM670_SLAVE_GRAPHICS_3D_CFG, 212 SDM670_SLAVE_VENUS_CFG, 213 SDM670_SLAVE_TSIF, 214 SDM670_SLAVE_CDSP_CFG, 215 SDM670_SLAVE_AOP, 216 SDM670_SLAVE_BLSP_2, 217 SDM670_SLAVE_SERVICE_CNOC, 218 SDM670_SLAVE_USB3, 219 SDM670_SLAVE_IPA_CFG, 220 SDM670_SLAVE_RBCPR_CX_CFG, 221 SDM670_SLAVE_A1NOC_CFG, 222 SDM670_SLAVE_AOSS, 223 SDM670_SLAVE_PRNG, 224 SDM670_SLAVE_VSENSE_CTRL_CFG, 225 SDM670_SLAVE_EMMC_CFG, 226 SDM670_SLAVE_BLSP_1, 227 SDM670_SLAVE_SPDM_WRAPPER, 228 SDM670_SLAVE_CRYPTO_0_CFG, 229 SDM670_SLAVE_PIMEM_CFG, 230 SDM670_SLAVE_TLMM_NORTH, 231 SDM670_SLAVE_CLK_CTL, 232 SDM670_SLAVE_IMEM_CFG 233 }, 234}; 235 236static struct qcom_icc_node qhm_cnoc = { 237 .name = "qhm_cnoc", 238 .id = SDM670_MASTER_CNOC_DC_NOC, 239 .channels = 1, 240 .buswidth = 4, 241 .num_links = 2, 242 .links = { SDM670_SLAVE_MEM_NOC_CFG, 243 SDM670_SLAVE_LLCC_CFG 244 }, 245}; 246 247static struct qcom_icc_node acm_l3 = { 248 .name = "acm_l3", 249 .id = SDM670_MASTER_AMPSS_M0, 250 .channels = 1, 251 .buswidth = 16, 252 .num_links = 3, 253 .links = { SDM670_SLAVE_SERVICE_GNOC, 254 SDM670_SLAVE_GNOC_SNOC, 255 SDM670_SLAVE_GNOC_MEM_NOC 256 }, 257}; 258 259static struct qcom_icc_node pm_gnoc_cfg = { 260 .name = "pm_gnoc_cfg", 261 .id = SDM670_MASTER_GNOC_CFG, 262 .channels = 1, 263 .buswidth = 4, 264 .num_links = 1, 265 .links = { SDM670_SLAVE_SERVICE_GNOC }, 266}; 267 268static struct qcom_icc_node llcc_mc = { 269 .name = "llcc_mc", 270 .id = SDM670_MASTER_LLCC, 271 .channels = 2, 272 .buswidth = 4, 273 .num_links = 1, 274 .links = { SDM670_SLAVE_EBI_CH0 }, 275}; 276 277static struct qcom_icc_node acm_tcu = { 278 .name = "acm_tcu", 279 .id = SDM670_MASTER_TCU_0, 280 .channels = 1, 281 .buswidth = 8, 282 .num_links = 3, 283 .links = { SDM670_SLAVE_MEM_NOC_GNOC, 284 SDM670_SLAVE_LLCC, 285 SDM670_SLAVE_MEM_NOC_SNOC 286 }, 287}; 288 289static struct qcom_icc_node qhm_memnoc_cfg = { 290 .name = "qhm_memnoc_cfg", 291 .id = SDM670_MASTER_MEM_NOC_CFG, 292 .channels = 1, 293 .buswidth = 4, 294 .num_links = 2, 295 .links = { SDM670_SLAVE_SERVICE_MEM_NOC, 296 SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 297 }, 298}; 299 300static struct qcom_icc_node qnm_apps = { 301 .name = "qnm_apps", 302 .id = SDM670_MASTER_GNOC_MEM_NOC, 303 .channels = 2, 304 .buswidth = 32, 305 .num_links = 1, 306 .links = { SDM670_SLAVE_LLCC }, 307}; 308 309static struct qcom_icc_node qnm_mnoc_hf = { 310 .name = "qnm_mnoc_hf", 311 .id = SDM670_MASTER_MNOC_HF_MEM_NOC, 312 .channels = 2, 313 .buswidth = 32, 314 .num_links = 1, 315 .links = { SDM670_SLAVE_LLCC }, 316}; 317 318static struct qcom_icc_node qnm_mnoc_sf = { 319 .name = "qnm_mnoc_sf", 320 .id = SDM670_MASTER_MNOC_SF_MEM_NOC, 321 .channels = 1, 322 .buswidth = 32, 323 .num_links = 3, 324 .links = { SDM670_SLAVE_MEM_NOC_GNOC, 325 SDM670_SLAVE_LLCC, 326 SDM670_SLAVE_MEM_NOC_SNOC 327 }, 328}; 329 330static struct qcom_icc_node qnm_snoc_gc = { 331 .name = "qnm_snoc_gc", 332 .id = SDM670_MASTER_SNOC_GC_MEM_NOC, 333 .channels = 1, 334 .buswidth = 8, 335 .num_links = 1, 336 .links = { SDM670_SLAVE_LLCC }, 337}; 338 339static struct qcom_icc_node qnm_snoc_sf = { 340 .name = "qnm_snoc_sf", 341 .id = SDM670_MASTER_SNOC_SF_MEM_NOC, 342 .channels = 1, 343 .buswidth = 16, 344 .num_links = 2, 345 .links = { SDM670_SLAVE_MEM_NOC_GNOC, 346 SDM670_SLAVE_LLCC 347 }, 348}; 349 350static struct qcom_icc_node qxm_gpu = { 351 .name = "qxm_gpu", 352 .id = SDM670_MASTER_GRAPHICS_3D, 353 .channels = 2, 354 .buswidth = 32, 355 .num_links = 3, 356 .links = { SDM670_SLAVE_MEM_NOC_GNOC, 357 SDM670_SLAVE_LLCC, 358 SDM670_SLAVE_MEM_NOC_SNOC 359 }, 360}; 361 362static struct qcom_icc_node qhm_mnoc_cfg = { 363 .name = "qhm_mnoc_cfg", 364 .id = SDM670_MASTER_CNOC_MNOC_CFG, 365 .channels = 1, 366 .buswidth = 4, 367 .num_links = 1, 368 .links = { SDM670_SLAVE_SERVICE_MNOC }, 369}; 370 371static struct qcom_icc_node qxm_camnoc_hf0 = { 372 .name = "qxm_camnoc_hf0", 373 .id = SDM670_MASTER_CAMNOC_HF0, 374 .channels = 1, 375 .buswidth = 32, 376 .num_links = 1, 377 .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, 378}; 379 380static struct qcom_icc_node qxm_camnoc_hf1 = { 381 .name = "qxm_camnoc_hf1", 382 .id = SDM670_MASTER_CAMNOC_HF1, 383 .channels = 1, 384 .buswidth = 32, 385 .num_links = 1, 386 .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, 387}; 388 389static struct qcom_icc_node qxm_camnoc_sf = { 390 .name = "qxm_camnoc_sf", 391 .id = SDM670_MASTER_CAMNOC_SF, 392 .channels = 1, 393 .buswidth = 32, 394 .num_links = 1, 395 .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, 396}; 397 398static struct qcom_icc_node qxm_mdp0 = { 399 .name = "qxm_mdp0", 400 .id = SDM670_MASTER_MDP_PORT0, 401 .channels = 1, 402 .buswidth = 32, 403 .num_links = 1, 404 .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, 405}; 406 407static struct qcom_icc_node qxm_mdp1 = { 408 .name = "qxm_mdp1", 409 .id = SDM670_MASTER_MDP_PORT1, 410 .channels = 1, 411 .buswidth = 32, 412 .num_links = 1, 413 .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, 414}; 415 416static struct qcom_icc_node qxm_rot = { 417 .name = "qxm_rot", 418 .id = SDM670_MASTER_ROTATOR, 419 .channels = 1, 420 .buswidth = 32, 421 .num_links = 1, 422 .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, 423}; 424 425static struct qcom_icc_node qxm_venus0 = { 426 .name = "qxm_venus0", 427 .id = SDM670_MASTER_VIDEO_P0, 428 .channels = 1, 429 .buswidth = 32, 430 .num_links = 1, 431 .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, 432}; 433 434static struct qcom_icc_node qxm_venus1 = { 435 .name = "qxm_venus1", 436 .id = SDM670_MASTER_VIDEO_P1, 437 .channels = 1, 438 .buswidth = 32, 439 .num_links = 1, 440 .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, 441}; 442 443static struct qcom_icc_node qxm_venus_arm9 = { 444 .name = "qxm_venus_arm9", 445 .id = SDM670_MASTER_VIDEO_PROC, 446 .channels = 1, 447 .buswidth = 8, 448 .num_links = 1, 449 .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, 450}; 451 452static struct qcom_icc_node qhm_snoc_cfg = { 453 .name = "qhm_snoc_cfg", 454 .id = SDM670_MASTER_SNOC_CFG, 455 .channels = 1, 456 .buswidth = 4, 457 .num_links = 1, 458 .links = { SDM670_SLAVE_SERVICE_SNOC }, 459}; 460 461static struct qcom_icc_node qnm_aggre1_noc = { 462 .name = "qnm_aggre1_noc", 463 .id = SDM670_MASTER_A1NOC_SNOC, 464 .channels = 1, 465 .buswidth = 16, 466 .num_links = 6, 467 .links = { SDM670_SLAVE_PIMEM, 468 SDM670_SLAVE_SNOC_MEM_NOC_SF, 469 SDM670_SLAVE_OCIMEM, 470 SDM670_SLAVE_APPSS, 471 SDM670_SLAVE_SNOC_CNOC, 472 SDM670_SLAVE_QDSS_STM 473 }, 474}; 475 476static struct qcom_icc_node qnm_aggre2_noc = { 477 .name = "qnm_aggre2_noc", 478 .id = SDM670_MASTER_A2NOC_SNOC, 479 .channels = 1, 480 .buswidth = 16, 481 .num_links = 7, 482 .links = { SDM670_SLAVE_PIMEM, 483 SDM670_SLAVE_SNOC_MEM_NOC_SF, 484 SDM670_SLAVE_OCIMEM, 485 SDM670_SLAVE_APPSS, 486 SDM670_SLAVE_SNOC_CNOC, 487 SDM670_SLAVE_TCU, 488 SDM670_SLAVE_QDSS_STM 489 }, 490}; 491 492static struct qcom_icc_node qnm_gladiator_sodv = { 493 .name = "qnm_gladiator_sodv", 494 .id = SDM670_MASTER_GNOC_SNOC, 495 .channels = 1, 496 .buswidth = 8, 497 .num_links = 6, 498 .links = { SDM670_SLAVE_PIMEM, 499 SDM670_SLAVE_OCIMEM, 500 SDM670_SLAVE_APPSS, 501 SDM670_SLAVE_SNOC_CNOC, 502 SDM670_SLAVE_TCU, 503 SDM670_SLAVE_QDSS_STM 504 }, 505}; 506 507static struct qcom_icc_node qnm_memnoc = { 508 .name = "qnm_memnoc", 509 .id = SDM670_MASTER_MEM_NOC_SNOC, 510 .channels = 1, 511 .buswidth = 8, 512 .num_links = 5, 513 .links = { SDM670_SLAVE_OCIMEM, 514 SDM670_SLAVE_APPSS, 515 SDM670_SLAVE_PIMEM, 516 SDM670_SLAVE_SNOC_CNOC, 517 SDM670_SLAVE_QDSS_STM 518 }, 519}; 520 521static struct qcom_icc_node qxm_pimem = { 522 .name = "qxm_pimem", 523 .id = SDM670_MASTER_PIMEM, 524 .channels = 1, 525 .buswidth = 8, 526 .num_links = 2, 527 .links = { SDM670_SLAVE_OCIMEM, 528 SDM670_SLAVE_SNOC_MEM_NOC_GC 529 }, 530}; 531 532static struct qcom_icc_node xm_gic = { 533 .name = "xm_gic", 534 .id = SDM670_MASTER_GIC, 535 .channels = 1, 536 .buswidth = 8, 537 .num_links = 2, 538 .links = { SDM670_SLAVE_OCIMEM, 539 SDM670_SLAVE_SNOC_MEM_NOC_GC 540 }, 541}; 542 543static struct qcom_icc_node qns_a1noc_snoc = { 544 .name = "qns_a1noc_snoc", 545 .id = SDM670_SLAVE_A1NOC_SNOC, 546 .channels = 1, 547 .buswidth = 16, 548 .num_links = 1, 549 .links = { SDM670_MASTER_A1NOC_SNOC }, 550}; 551 552static struct qcom_icc_node srvc_aggre1_noc = { 553 .name = "srvc_aggre1_noc", 554 .id = SDM670_SLAVE_SERVICE_A1NOC, 555 .channels = 1, 556 .buswidth = 4, 557}; 558 559static struct qcom_icc_node qns_a2noc_snoc = { 560 .name = "qns_a2noc_snoc", 561 .id = SDM670_SLAVE_A2NOC_SNOC, 562 .channels = 1, 563 .buswidth = 16, 564 .num_links = 1, 565 .links = { SDM670_MASTER_A2NOC_SNOC }, 566}; 567 568static struct qcom_icc_node srvc_aggre2_noc = { 569 .name = "srvc_aggre2_noc", 570 .id = SDM670_SLAVE_SERVICE_A2NOC, 571 .channels = 1, 572 .buswidth = 4, 573}; 574 575static struct qcom_icc_node qns_camnoc_uncomp = { 576 .name = "qns_camnoc_uncomp", 577 .id = SDM670_SLAVE_CAMNOC_UNCOMP, 578 .channels = 1, 579 .buswidth = 32, 580}; 581 582static struct qcom_icc_node qhs_a1_noc_cfg = { 583 .name = "qhs_a1_noc_cfg", 584 .id = SDM670_SLAVE_A1NOC_CFG, 585 .channels = 1, 586 .buswidth = 4, 587 .num_links = 1, 588 .links = { SDM670_MASTER_A1NOC_CFG }, 589}; 590 591static struct qcom_icc_node qhs_a2_noc_cfg = { 592 .name = "qhs_a2_noc_cfg", 593 .id = SDM670_SLAVE_A2NOC_CFG, 594 .channels = 1, 595 .buswidth = 4, 596 .num_links = 1, 597 .links = { SDM670_MASTER_A2NOC_CFG }, 598}; 599 600static struct qcom_icc_node qhs_aop = { 601 .name = "qhs_aop", 602 .id = SDM670_SLAVE_AOP, 603 .channels = 1, 604 .buswidth = 4, 605}; 606 607static struct qcom_icc_node qhs_aoss = { 608 .name = "qhs_aoss", 609 .id = SDM670_SLAVE_AOSS, 610 .channels = 1, 611 .buswidth = 4, 612}; 613 614static struct qcom_icc_node qhs_camera_cfg = { 615 .name = "qhs_camera_cfg", 616 .id = SDM670_SLAVE_CAMERA_CFG, 617 .channels = 1, 618 .buswidth = 4, 619}; 620 621static struct qcom_icc_node qhs_clk_ctl = { 622 .name = "qhs_clk_ctl", 623 .id = SDM670_SLAVE_CLK_CTL, 624 .channels = 1, 625 .buswidth = 4, 626}; 627 628static struct qcom_icc_node qhs_compute_dsp_cfg = { 629 .name = "qhs_compute_dsp_cfg", 630 .id = SDM670_SLAVE_CDSP_CFG, 631 .channels = 1, 632 .buswidth = 4, 633}; 634 635static struct qcom_icc_node qhs_cpr_cx = { 636 .name = "qhs_cpr_cx", 637 .id = SDM670_SLAVE_RBCPR_CX_CFG, 638 .channels = 1, 639 .buswidth = 4, 640}; 641 642static struct qcom_icc_node qhs_crypto0_cfg = { 643 .name = "qhs_crypto0_cfg", 644 .id = SDM670_SLAVE_CRYPTO_0_CFG, 645 .channels = 1, 646 .buswidth = 4, 647}; 648 649static struct qcom_icc_node qhs_dcc_cfg = { 650 .name = "qhs_dcc_cfg", 651 .id = SDM670_SLAVE_DCC_CFG, 652 .channels = 1, 653 .buswidth = 4, 654 .num_links = 1, 655 .links = { SDM670_MASTER_CNOC_DC_NOC }, 656}; 657 658static struct qcom_icc_node qhs_ddrss_cfg = { 659 .name = "qhs_ddrss_cfg", 660 .id = SDM670_SLAVE_CNOC_DDRSS, 661 .channels = 1, 662 .buswidth = 4, 663}; 664 665static struct qcom_icc_node qhs_display_cfg = { 666 .name = "qhs_display_cfg", 667 .id = SDM670_SLAVE_DISPLAY_CFG, 668 .channels = 1, 669 .buswidth = 4, 670}; 671 672static struct qcom_icc_node qhs_emmc_cfg = { 673 .name = "qhs_emmc_cfg", 674 .id = SDM670_SLAVE_EMMC_CFG, 675 .channels = 1, 676 .buswidth = 4, 677}; 678 679static struct qcom_icc_node qhs_glm = { 680 .name = "qhs_glm", 681 .id = SDM670_SLAVE_GLM, 682 .channels = 1, 683 .buswidth = 4, 684}; 685 686static struct qcom_icc_node qhs_gpuss_cfg = { 687 .name = "qhs_gpuss_cfg", 688 .id = SDM670_SLAVE_GRAPHICS_3D_CFG, 689 .channels = 1, 690 .buswidth = 8, 691}; 692 693static struct qcom_icc_node qhs_imem_cfg = { 694 .name = "qhs_imem_cfg", 695 .id = SDM670_SLAVE_IMEM_CFG, 696 .channels = 1, 697 .buswidth = 4, 698}; 699 700static struct qcom_icc_node qhs_ipa = { 701 .name = "qhs_ipa", 702 .id = SDM670_SLAVE_IPA_CFG, 703 .channels = 1, 704 .buswidth = 4, 705}; 706 707static struct qcom_icc_node qhs_mnoc_cfg = { 708 .name = "qhs_mnoc_cfg", 709 .id = SDM670_SLAVE_CNOC_MNOC_CFG, 710 .channels = 1, 711 .buswidth = 4, 712 .num_links = 1, 713 .links = { SDM670_MASTER_CNOC_MNOC_CFG }, 714}; 715 716static struct qcom_icc_node qhs_pdm = { 717 .name = "qhs_pdm", 718 .id = SDM670_SLAVE_PDM, 719 .channels = 1, 720 .buswidth = 4, 721}; 722 723static struct qcom_icc_node qhs_phy_refgen_south = { 724 .name = "qhs_phy_refgen_south", 725 .id = SDM670_SLAVE_SOUTH_PHY_CFG, 726 .channels = 1, 727 .buswidth = 4, 728}; 729 730static struct qcom_icc_node qhs_pimem_cfg = { 731 .name = "qhs_pimem_cfg", 732 .id = SDM670_SLAVE_PIMEM_CFG, 733 .channels = 1, 734 .buswidth = 4, 735}; 736 737static struct qcom_icc_node qhs_prng = { 738 .name = "qhs_prng", 739 .id = SDM670_SLAVE_PRNG, 740 .channels = 1, 741 .buswidth = 4, 742}; 743 744static struct qcom_icc_node qhs_qdss_cfg = { 745 .name = "qhs_qdss_cfg", 746 .id = SDM670_SLAVE_QDSS_CFG, 747 .channels = 1, 748 .buswidth = 4, 749}; 750 751static struct qcom_icc_node qhs_qupv3_north = { 752 .name = "qhs_qupv3_north", 753 .id = SDM670_SLAVE_BLSP_2, 754 .channels = 1, 755 .buswidth = 4, 756}; 757 758static struct qcom_icc_node qhs_qupv3_south = { 759 .name = "qhs_qupv3_south", 760 .id = SDM670_SLAVE_BLSP_1, 761 .channels = 1, 762 .buswidth = 4, 763}; 764 765static struct qcom_icc_node qhs_sdc2 = { 766 .name = "qhs_sdc2", 767 .id = SDM670_SLAVE_SDCC_2, 768 .channels = 1, 769 .buswidth = 4, 770}; 771 772static struct qcom_icc_node qhs_sdc4 = { 773 .name = "qhs_sdc4", 774 .id = SDM670_SLAVE_SDCC_4, 775 .channels = 1, 776 .buswidth = 4, 777}; 778 779static struct qcom_icc_node qhs_snoc_cfg = { 780 .name = "qhs_snoc_cfg", 781 .id = SDM670_SLAVE_SNOC_CFG, 782 .channels = 1, 783 .buswidth = 4, 784 .num_links = 1, 785 .links = { SDM670_MASTER_SNOC_CFG }, 786}; 787 788static struct qcom_icc_node qhs_spdm = { 789 .name = "qhs_spdm", 790 .id = SDM670_SLAVE_SPDM_WRAPPER, 791 .channels = 1, 792 .buswidth = 4, 793}; 794 795static struct qcom_icc_node qhs_tcsr = { 796 .name = "qhs_tcsr", 797 .id = SDM670_SLAVE_TCSR, 798 .channels = 1, 799 .buswidth = 4, 800}; 801 802static struct qcom_icc_node qhs_tlmm_north = { 803 .name = "qhs_tlmm_north", 804 .id = SDM670_SLAVE_TLMM_NORTH, 805 .channels = 1, 806 .buswidth = 4, 807}; 808 809static struct qcom_icc_node qhs_tlmm_south = { 810 .name = "qhs_tlmm_south", 811 .id = SDM670_SLAVE_TLMM_SOUTH, 812 .channels = 1, 813 .buswidth = 4, 814}; 815 816static struct qcom_icc_node qhs_tsif = { 817 .name = "qhs_tsif", 818 .id = SDM670_SLAVE_TSIF, 819 .channels = 1, 820 .buswidth = 4, 821}; 822 823static struct qcom_icc_node qhs_ufs_mem_cfg = { 824 .name = "qhs_ufs_mem_cfg", 825 .id = SDM670_SLAVE_UFS_MEM_CFG, 826 .channels = 1, 827 .buswidth = 4, 828}; 829 830static struct qcom_icc_node qhs_usb3_0 = { 831 .name = "qhs_usb3_0", 832 .id = SDM670_SLAVE_USB3, 833 .channels = 1, 834 .buswidth = 4, 835}; 836 837static struct qcom_icc_node qhs_venus_cfg = { 838 .name = "qhs_venus_cfg", 839 .id = SDM670_SLAVE_VENUS_CFG, 840 .channels = 1, 841 .buswidth = 4, 842}; 843 844static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 845 .name = "qhs_vsense_ctrl_cfg", 846 .id = SDM670_SLAVE_VSENSE_CTRL_CFG, 847 .channels = 1, 848 .buswidth = 4, 849}; 850 851static struct qcom_icc_node qns_cnoc_a2noc = { 852 .name = "qns_cnoc_a2noc", 853 .id = SDM670_SLAVE_CNOC_A2NOC, 854 .channels = 1, 855 .buswidth = 8, 856 .num_links = 1, 857 .links = { SDM670_MASTER_CNOC_A2NOC }, 858}; 859 860static struct qcom_icc_node srvc_cnoc = { 861 .name = "srvc_cnoc", 862 .id = SDM670_SLAVE_SERVICE_CNOC, 863 .channels = 1, 864 .buswidth = 4, 865}; 866 867static struct qcom_icc_node qhs_llcc = { 868 .name = "qhs_llcc", 869 .id = SDM670_SLAVE_LLCC_CFG, 870 .channels = 1, 871 .buswidth = 4, 872}; 873 874static struct qcom_icc_node qhs_memnoc = { 875 .name = "qhs_memnoc", 876 .id = SDM670_SLAVE_MEM_NOC_CFG, 877 .channels = 1, 878 .buswidth = 4, 879 .num_links = 1, 880 .links = { SDM670_MASTER_MEM_NOC_CFG }, 881}; 882 883static struct qcom_icc_node qns_gladiator_sodv = { 884 .name = "qns_gladiator_sodv", 885 .id = SDM670_SLAVE_GNOC_SNOC, 886 .channels = 1, 887 .buswidth = 8, 888 .num_links = 1, 889 .links = { SDM670_MASTER_GNOC_SNOC }, 890}; 891 892static struct qcom_icc_node qns_gnoc_memnoc = { 893 .name = "qns_gnoc_memnoc", 894 .id = SDM670_SLAVE_GNOC_MEM_NOC, 895 .channels = 2, 896 .buswidth = 32, 897 .num_links = 1, 898 .links = { SDM670_MASTER_GNOC_MEM_NOC }, 899}; 900 901static struct qcom_icc_node srvc_gnoc = { 902 .name = "srvc_gnoc", 903 .id = SDM670_SLAVE_SERVICE_GNOC, 904 .channels = 1, 905 .buswidth = 4, 906}; 907 908static struct qcom_icc_node ebi = { 909 .name = "ebi", 910 .id = SDM670_SLAVE_EBI_CH0, 911 .channels = 2, 912 .buswidth = 4, 913}; 914 915static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 916 .name = "qhs_mdsp_ms_mpu_cfg", 917 .id = SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 918 .channels = 1, 919 .buswidth = 4, 920}; 921 922static struct qcom_icc_node qns_apps_io = { 923 .name = "qns_apps_io", 924 .id = SDM670_SLAVE_MEM_NOC_GNOC, 925 .channels = 1, 926 .buswidth = 32, 927}; 928 929static struct qcom_icc_node qns_llcc = { 930 .name = "qns_llcc", 931 .id = SDM670_SLAVE_LLCC, 932 .channels = 2, 933 .buswidth = 16, 934 .num_links = 1, 935 .links = { SDM670_MASTER_LLCC }, 936}; 937 938static struct qcom_icc_node qns_memnoc_snoc = { 939 .name = "qns_memnoc_snoc", 940 .id = SDM670_SLAVE_MEM_NOC_SNOC, 941 .channels = 1, 942 .buswidth = 8, 943 .num_links = 1, 944 .links = { SDM670_MASTER_MEM_NOC_SNOC }, 945}; 946 947static struct qcom_icc_node srvc_memnoc = { 948 .name = "srvc_memnoc", 949 .id = SDM670_SLAVE_SERVICE_MEM_NOC, 950 .channels = 1, 951 .buswidth = 4, 952}; 953 954static struct qcom_icc_node qns2_mem_noc = { 955 .name = "qns2_mem_noc", 956 .id = SDM670_SLAVE_MNOC_SF_MEM_NOC, 957 .channels = 1, 958 .buswidth = 32, 959 .num_links = 1, 960 .links = { SDM670_MASTER_MNOC_SF_MEM_NOC }, 961}; 962 963static struct qcom_icc_node qns_mem_noc_hf = { 964 .name = "qns_mem_noc_hf", 965 .id = SDM670_SLAVE_MNOC_HF_MEM_NOC, 966 .channels = 2, 967 .buswidth = 32, 968 .num_links = 1, 969 .links = { SDM670_MASTER_MNOC_HF_MEM_NOC }, 970}; 971 972static struct qcom_icc_node srvc_mnoc = { 973 .name = "srvc_mnoc", 974 .id = SDM670_SLAVE_SERVICE_MNOC, 975 .channels = 1, 976 .buswidth = 4, 977}; 978 979static struct qcom_icc_node qhs_apss = { 980 .name = "qhs_apss", 981 .id = SDM670_SLAVE_APPSS, 982 .channels = 1, 983 .buswidth = 8, 984}; 985 986static struct qcom_icc_node qns_cnoc = { 987 .name = "qns_cnoc", 988 .id = SDM670_SLAVE_SNOC_CNOC, 989 .channels = 1, 990 .buswidth = 8, 991 .num_links = 1, 992 .links = { SDM670_MASTER_SNOC_CNOC }, 993}; 994 995static struct qcom_icc_node qns_memnoc_gc = { 996 .name = "qns_memnoc_gc", 997 .id = SDM670_SLAVE_SNOC_MEM_NOC_GC, 998 .channels = 1, 999 .buswidth = 8, 1000 .num_links = 1, 1001 .links = { SDM670_MASTER_SNOC_GC_MEM_NOC }, 1002}; 1003 1004static struct qcom_icc_node qns_memnoc_sf = { 1005 .name = "qns_memnoc_sf", 1006 .id = SDM670_SLAVE_SNOC_MEM_NOC_SF, 1007 .channels = 1, 1008 .buswidth = 16, 1009 .num_links = 1, 1010 .links = { SDM670_MASTER_SNOC_SF_MEM_NOC }, 1011}; 1012 1013static struct qcom_icc_node qxs_imem = { 1014 .name = "qxs_imem", 1015 .id = SDM670_SLAVE_OCIMEM, 1016 .channels = 1, 1017 .buswidth = 8, 1018}; 1019 1020static struct qcom_icc_node qxs_pimem = { 1021 .name = "qxs_pimem", 1022 .id = SDM670_SLAVE_PIMEM, 1023 .channels = 1, 1024 .buswidth = 8, 1025}; 1026 1027static struct qcom_icc_node srvc_snoc = { 1028 .name = "srvc_snoc", 1029 .id = SDM670_SLAVE_SERVICE_SNOC, 1030 .channels = 1, 1031 .buswidth = 4, 1032}; 1033 1034static struct qcom_icc_node xs_qdss_stm = { 1035 .name = "xs_qdss_stm", 1036 .id = SDM670_SLAVE_QDSS_STM, 1037 .channels = 1, 1038 .buswidth = 4, 1039}; 1040 1041static struct qcom_icc_node xs_sys_tcu_cfg = { 1042 .name = "xs_sys_tcu_cfg", 1043 .id = SDM670_SLAVE_TCU, 1044 .channels = 1, 1045 .buswidth = 8, 1046}; 1047 1048static struct qcom_icc_bcm bcm_acv = { 1049 .name = "ACV", 1050 .enable_mask = BIT(3), 1051 .keepalive = false, 1052 .num_nodes = 1, 1053 .nodes = { &ebi }, 1054}; 1055 1056static struct qcom_icc_bcm bcm_mc0 = { 1057 .name = "MC0", 1058 .keepalive = true, 1059 .num_nodes = 1, 1060 .nodes = { &ebi }, 1061}; 1062 1063static struct qcom_icc_bcm bcm_sh0 = { 1064 .name = "SH0", 1065 .keepalive = true, 1066 .num_nodes = 1, 1067 .nodes = { &qns_llcc }, 1068}; 1069 1070static struct qcom_icc_bcm bcm_mm0 = { 1071 .name = "MM0", 1072 .keepalive = true, 1073 .num_nodes = 1, 1074 .nodes = { &qns_mem_noc_hf }, 1075}; 1076 1077static struct qcom_icc_bcm bcm_sh1 = { 1078 .name = "SH1", 1079 .keepalive = false, 1080 .num_nodes = 1, 1081 .nodes = { &qns_apps_io }, 1082}; 1083 1084static struct qcom_icc_bcm bcm_mm1 = { 1085 .name = "MM1", 1086 .keepalive = true, 1087 .num_nodes = 7, 1088 .nodes = { &qxm_camnoc_hf0_uncomp, 1089 &qxm_camnoc_hf1_uncomp, 1090 &qxm_camnoc_sf_uncomp, 1091 &qxm_camnoc_hf0, 1092 &qxm_camnoc_hf1, 1093 &qxm_mdp0, 1094 &qxm_mdp1 1095 }, 1096}; 1097 1098static struct qcom_icc_bcm bcm_sh2 = { 1099 .name = "SH2", 1100 .keepalive = false, 1101 .num_nodes = 1, 1102 .nodes = { &qns_memnoc_snoc }, 1103}; 1104 1105static struct qcom_icc_bcm bcm_mm2 = { 1106 .name = "MM2", 1107 .keepalive = false, 1108 .num_nodes = 1, 1109 .nodes = { &qns2_mem_noc }, 1110}; 1111 1112static struct qcom_icc_bcm bcm_sh3 = { 1113 .name = "SH3", 1114 .keepalive = false, 1115 .num_nodes = 1, 1116 .nodes = { &acm_tcu }, 1117}; 1118 1119static struct qcom_icc_bcm bcm_mm3 = { 1120 .name = "MM3", 1121 .keepalive = false, 1122 .num_nodes = 5, 1123 .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1124}; 1125 1126static struct qcom_icc_bcm bcm_sh5 = { 1127 .name = "SH5", 1128 .keepalive = false, 1129 .num_nodes = 1, 1130 .nodes = { &qnm_apps }, 1131}; 1132 1133static struct qcom_icc_bcm bcm_sn0 = { 1134 .name = "SN0", 1135 .keepalive = true, 1136 .num_nodes = 1, 1137 .nodes = { &qns_memnoc_sf }, 1138}; 1139 1140static struct qcom_icc_bcm bcm_ce0 = { 1141 .name = "CE0", 1142 .keepalive = false, 1143 .num_nodes = 1, 1144 .nodes = { &qxm_crypto }, 1145}; 1146 1147static struct qcom_icc_bcm bcm_cn0 = { 1148 .name = "CN0", 1149 .keepalive = true, 1150 .num_nodes = 41, 1151 .nodes = { &qhm_spdm, 1152 &qnm_snoc, 1153 &qhs_a1_noc_cfg, 1154 &qhs_a2_noc_cfg, 1155 &qhs_aop, 1156 &qhs_aoss, 1157 &qhs_camera_cfg, 1158 &qhs_clk_ctl, 1159 &qhs_compute_dsp_cfg, 1160 &qhs_cpr_cx, 1161 &qhs_crypto0_cfg, 1162 &qhs_dcc_cfg, 1163 &qhs_ddrss_cfg, 1164 &qhs_display_cfg, 1165 &qhs_emmc_cfg, 1166 &qhs_glm, 1167 &qhs_gpuss_cfg, 1168 &qhs_imem_cfg, 1169 &qhs_ipa, 1170 &qhs_mnoc_cfg, 1171 &qhs_pdm, 1172 &qhs_phy_refgen_south, 1173 &qhs_pimem_cfg, 1174 &qhs_prng, 1175 &qhs_qdss_cfg, 1176 &qhs_qupv3_north, 1177 &qhs_qupv3_south, 1178 &qhs_sdc2, 1179 &qhs_sdc4, 1180 &qhs_snoc_cfg, 1181 &qhs_spdm, 1182 &qhs_tcsr, 1183 &qhs_tlmm_north, 1184 &qhs_tlmm_south, 1185 &qhs_tsif, 1186 &qhs_ufs_mem_cfg, 1187 &qhs_usb3_0, 1188 &qhs_venus_cfg, 1189 &qhs_vsense_ctrl_cfg, 1190 &qns_cnoc_a2noc, 1191 &srvc_cnoc 1192 }, 1193}; 1194 1195static struct qcom_icc_bcm bcm_qup0 = { 1196 .name = "QUP0", 1197 .keepalive = false, 1198 .num_nodes = 2, 1199 .nodes = { &qhm_qup1, &qhm_qup2 }, 1200}; 1201 1202static struct qcom_icc_bcm bcm_sn1 = { 1203 .name = "SN1", 1204 .keepalive = false, 1205 .num_nodes = 1, 1206 .nodes = { &qxs_imem }, 1207}; 1208 1209static struct qcom_icc_bcm bcm_sn2 = { 1210 .name = "SN2", 1211 .keepalive = false, 1212 .num_nodes = 1, 1213 .nodes = { &qns_memnoc_gc }, 1214}; 1215 1216static struct qcom_icc_bcm bcm_sn3 = { 1217 .name = "SN3", 1218 .keepalive = false, 1219 .num_nodes = 1, 1220 .nodes = { &qns_cnoc }, 1221}; 1222 1223static struct qcom_icc_bcm bcm_sn4 = { 1224 .name = "SN4", 1225 .keepalive = false, 1226 .num_nodes = 2, 1227 .nodes = { &qxm_pimem, &qxs_pimem }, 1228}; 1229 1230static struct qcom_icc_bcm bcm_sn5 = { 1231 .name = "SN5", 1232 .keepalive = false, 1233 .num_nodes = 1, 1234 .nodes = { &xs_qdss_stm }, 1235}; 1236 1237static struct qcom_icc_bcm bcm_sn8 = { 1238 .name = "SN8", 1239 .keepalive = false, 1240 .num_nodes = 2, 1241 .nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc }, 1242}; 1243 1244static struct qcom_icc_bcm bcm_sn10 = { 1245 .name = "SN10", 1246 .keepalive = false, 1247 .num_nodes = 2, 1248 .nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc }, 1249}; 1250 1251static struct qcom_icc_bcm bcm_sn11 = { 1252 .name = "SN11", 1253 .keepalive = false, 1254 .num_nodes = 2, 1255 .nodes = { &qnm_gladiator_sodv, &xm_gic }, 1256}; 1257 1258static struct qcom_icc_bcm bcm_sn13 = { 1259 .name = "SN13", 1260 .keepalive = false, 1261 .num_nodes = 1, 1262 .nodes = { &qnm_memnoc }, 1263}; 1264 1265static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1266 &bcm_qup0, 1267 &bcm_sn8, 1268}; 1269 1270static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1271 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1272 [MASTER_BLSP_1] = &qhm_qup1, 1273 [MASTER_TSIF] = &qhm_tsif, 1274 [MASTER_EMMC] = &xm_emmc, 1275 [MASTER_SDCC_2] = &xm_sdc2, 1276 [MASTER_SDCC_4] = &xm_sdc4, 1277 [MASTER_UFS_MEM] = &xm_ufs_mem, 1278 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1279 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1280}; 1281 1282static const struct qcom_icc_desc sdm670_aggre1_noc = { 1283 .nodes = aggre1_noc_nodes, 1284 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1285 .bcms = aggre1_noc_bcms, 1286 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1287}; 1288 1289static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1290 &bcm_ce0, 1291 &bcm_qup0, 1292 &bcm_sn10, 1293}; 1294 1295static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1296 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1297 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1298 [MASTER_BLSP_2] = &qhm_qup2, 1299 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1300 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1301 [MASTER_IPA] = &qxm_ipa, 1302 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1303 [MASTER_USB3] = &xm_usb3_0, 1304 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1305 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1306}; 1307 1308static const struct qcom_icc_desc sdm670_aggre2_noc = { 1309 .nodes = aggre2_noc_nodes, 1310 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1311 .bcms = aggre2_noc_bcms, 1312 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1313}; 1314 1315static struct qcom_icc_bcm * const config_noc_bcms[] = { 1316 &bcm_cn0, 1317}; 1318 1319static struct qcom_icc_node * const config_noc_nodes[] = { 1320 [MASTER_SPDM] = &qhm_spdm, 1321 [MASTER_SNOC_CNOC] = &qnm_snoc, 1322 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1323 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1324 [SLAVE_AOP] = &qhs_aop, 1325 [SLAVE_AOSS] = &qhs_aoss, 1326 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1327 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1328 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 1329 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1330 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1331 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1332 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1333 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1334 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1335 [SLAVE_GLM] = &qhs_glm, 1336 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1337 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1338 [SLAVE_IPA_CFG] = &qhs_ipa, 1339 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1340 [SLAVE_PDM] = &qhs_pdm, 1341 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, 1342 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1343 [SLAVE_PRNG] = &qhs_prng, 1344 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1345 [SLAVE_BLSP_2] = &qhs_qupv3_north, 1346 [SLAVE_BLSP_1] = &qhs_qupv3_south, 1347 [SLAVE_SDCC_2] = &qhs_sdc2, 1348 [SLAVE_SDCC_4] = &qhs_sdc4, 1349 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1350 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1351 [SLAVE_TCSR] = &qhs_tcsr, 1352 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1353 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1354 [SLAVE_TSIF] = &qhs_tsif, 1355 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1356 [SLAVE_USB3] = &qhs_usb3_0, 1357 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1358 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1359 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1360 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1361}; 1362 1363static const struct qcom_icc_desc sdm670_config_noc = { 1364 .nodes = config_noc_nodes, 1365 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1366 .bcms = config_noc_bcms, 1367 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1368}; 1369 1370static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1371}; 1372 1373static struct qcom_icc_node * const dc_noc_nodes[] = { 1374 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 1375 [SLAVE_LLCC_CFG] = &qhs_llcc, 1376 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, 1377}; 1378 1379static const struct qcom_icc_desc sdm670_dc_noc = { 1380 .nodes = dc_noc_nodes, 1381 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1382 .bcms = dc_noc_bcms, 1383 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1384}; 1385 1386static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { 1387}; 1388 1389static struct qcom_icc_node * const gladiator_noc_nodes[] = { 1390 [MASTER_AMPSS_M0] = &acm_l3, 1391 [MASTER_GNOC_CFG] = &pm_gnoc_cfg, 1392 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, 1393 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, 1394 [SLAVE_SERVICE_GNOC] = &srvc_gnoc, 1395}; 1396 1397static const struct qcom_icc_desc sdm670_gladiator_noc = { 1398 .nodes = gladiator_noc_nodes, 1399 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), 1400 .bcms = gladiator_noc_bcms, 1401 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), 1402}; 1403 1404static struct qcom_icc_bcm * const mem_noc_bcms[] = { 1405 &bcm_acv, 1406 &bcm_mc0, 1407 &bcm_sh0, 1408 &bcm_sh1, 1409 &bcm_sh2, 1410 &bcm_sh3, 1411 &bcm_sh5, 1412}; 1413 1414static struct qcom_icc_node * const mem_noc_nodes[] = { 1415 [MASTER_TCU_0] = &acm_tcu, 1416 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, 1417 [MASTER_GNOC_MEM_NOC] = &qnm_apps, 1418 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1419 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1420 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1421 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1422 [MASTER_GRAPHICS_3D] = &qxm_gpu, 1423 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1424 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, 1425 [SLAVE_LLCC] = &qns_llcc, 1426 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 1427 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, 1428 [MASTER_LLCC] = &llcc_mc, 1429 [SLAVE_EBI_CH0] = &ebi, 1430}; 1431 1432static const struct qcom_icc_desc sdm670_mem_noc = { 1433 .nodes = mem_noc_nodes, 1434 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 1435 .bcms = mem_noc_bcms, 1436 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 1437}; 1438 1439static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1440 &bcm_mm0, 1441 &bcm_mm1, 1442 &bcm_mm2, 1443 &bcm_mm3, 1444}; 1445 1446static struct qcom_icc_node * const mmss_noc_nodes[] = { 1447 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1448 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1449 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1450 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1451 [MASTER_MDP_PORT0] = &qxm_mdp0, 1452 [MASTER_MDP_PORT1] = &qxm_mdp1, 1453 [MASTER_ROTATOR] = &qxm_rot, 1454 [MASTER_VIDEO_P0] = &qxm_venus0, 1455 [MASTER_VIDEO_P1] = &qxm_venus1, 1456 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1457 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1458 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1459 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1460}; 1461 1462static const struct qcom_icc_desc sdm670_mmss_noc = { 1463 .nodes = mmss_noc_nodes, 1464 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1465 .bcms = mmss_noc_bcms, 1466 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1467}; 1468 1469static struct qcom_icc_bcm * const system_noc_bcms[] = { 1470 &bcm_mm1, 1471 &bcm_sn0, 1472 &bcm_sn1, 1473 &bcm_sn10, 1474 &bcm_sn11, 1475 &bcm_sn13, 1476 &bcm_sn2, 1477 &bcm_sn3, 1478 &bcm_sn4, 1479 &bcm_sn5, 1480 &bcm_sn8, 1481}; 1482 1483static struct qcom_icc_node * const system_noc_nodes[] = { 1484 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1485 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1486 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1487 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, 1488 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 1489 [MASTER_PIMEM] = &qxm_pimem, 1490 [MASTER_GIC] = &xm_gic, 1491 [SLAVE_APPSS] = &qhs_apss, 1492 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1493 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 1494 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, 1495 [SLAVE_OCIMEM] = &qxs_imem, 1496 [SLAVE_PIMEM] = &qxs_pimem, 1497 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1498 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1499 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1500 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1501 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1502 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1503 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1504}; 1505 1506static const struct qcom_icc_desc sdm670_system_noc = { 1507 .nodes = system_noc_nodes, 1508 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1509 .bcms = system_noc_bcms, 1510 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1511}; 1512 1513static const struct of_device_id qnoc_of_match[] = { 1514 { .compatible = "qcom,sdm670-aggre1-noc", 1515 .data = &sdm670_aggre1_noc}, 1516 { .compatible = "qcom,sdm670-aggre2-noc", 1517 .data = &sdm670_aggre2_noc}, 1518 { .compatible = "qcom,sdm670-config-noc", 1519 .data = &sdm670_config_noc}, 1520 { .compatible = "qcom,sdm670-dc-noc", 1521 .data = &sdm670_dc_noc}, 1522 { .compatible = "qcom,sdm670-gladiator-noc", 1523 .data = &sdm670_gladiator_noc}, 1524 { .compatible = "qcom,sdm670-mem-noc", 1525 .data = &sdm670_mem_noc}, 1526 { .compatible = "qcom,sdm670-mmss-noc", 1527 .data = &sdm670_mmss_noc}, 1528 { .compatible = "qcom,sdm670-system-noc", 1529 .data = &sdm670_system_noc}, 1530 { } 1531}; 1532MODULE_DEVICE_TABLE(of, qnoc_of_match); 1533 1534static struct platform_driver qnoc_driver = { 1535 .probe = qcom_icc_rpmh_probe, 1536 .remove_new = qcom_icc_rpmh_remove, 1537 .driver = { 1538 .name = "qnoc-sdm670", 1539 .of_match_table = qnoc_of_match, 1540 .sync_state = icc_sync_state, 1541 }, 1542}; 1543module_platform_driver(qnoc_driver); 1544 1545MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver"); 1546MODULE_LICENSE("GPL"); 1547