1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd 5 */ 6 7#include <linux/device.h> 8#include <linux/interconnect.h> 9#include <linux/interconnect-provider.h> 10#include <linux/mod_devicetable.h> 11#include <linux/module.h> 12#include <linux/platform_device.h> 13#include <dt-bindings/interconnect/qcom,sc8280xp.h> 14 15#include "bcm-voter.h" 16#include "icc-rpmh.h" 17#include "sc8280xp.h" 18 19static struct qcom_icc_node qhm_qspi = { 20 .name = "qhm_qspi", 21 .id = SC8280XP_MASTER_QSPI_0, 22 .channels = 1, 23 .buswidth = 4, 24 .num_links = 1, 25 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 26}; 27 28static struct qcom_icc_node qhm_qup1 = { 29 .name = "qhm_qup1", 30 .id = SC8280XP_MASTER_QUP_1, 31 .channels = 1, 32 .buswidth = 4, 33 .num_links = 1, 34 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 35}; 36 37static struct qcom_icc_node qhm_qup2 = { 38 .name = "qhm_qup2", 39 .id = SC8280XP_MASTER_QUP_2, 40 .channels = 1, 41 .buswidth = 4, 42 .num_links = 1, 43 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 44}; 45 46static struct qcom_icc_node qnm_a1noc_cfg = { 47 .name = "qnm_a1noc_cfg", 48 .id = SC8280XP_MASTER_A1NOC_CFG, 49 .channels = 1, 50 .buswidth = 4, 51 .links = { SC8280XP_SLAVE_SERVICE_A1NOC }, 52}; 53 54static struct qcom_icc_node qxm_ipa = { 55 .name = "qxm_ipa", 56 .id = SC8280XP_MASTER_IPA, 57 .channels = 1, 58 .buswidth = 8, 59 .num_links = 1, 60 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 61}; 62 63static struct qcom_icc_node xm_emac_1 = { 64 .name = "xm_emac_1", 65 .id = SC8280XP_MASTER_EMAC_1, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 70}; 71 72static struct qcom_icc_node xm_sdc4 = { 73 .name = "xm_sdc4", 74 .id = SC8280XP_MASTER_SDCC_4, 75 .channels = 1, 76 .buswidth = 8, 77 .num_links = 1, 78 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 79}; 80 81static struct qcom_icc_node xm_ufs_mem = { 82 .name = "xm_ufs_mem", 83 .id = SC8280XP_MASTER_UFS_MEM, 84 .channels = 1, 85 .buswidth = 8, 86 .num_links = 1, 87 .links = { SC8280XP_SLAVE_A1NOC_SNOC }, 88}; 89 90static struct qcom_icc_node xm_usb3_0 = { 91 .name = "xm_usb3_0", 92 .id = SC8280XP_MASTER_USB3_0, 93 .channels = 1, 94 .buswidth = 8, 95 .num_links = 1, 96 .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, 97}; 98 99static struct qcom_icc_node xm_usb3_1 = { 100 .name = "xm_usb3_1", 101 .id = SC8280XP_MASTER_USB3_1, 102 .channels = 1, 103 .buswidth = 8, 104 .num_links = 1, 105 .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, 106}; 107 108static struct qcom_icc_node xm_usb3_mp = { 109 .name = "xm_usb3_mp", 110 .id = SC8280XP_MASTER_USB3_MP, 111 .channels = 1, 112 .buswidth = 16, 113 .num_links = 1, 114 .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, 115}; 116 117static struct qcom_icc_node xm_usb4_host0 = { 118 .name = "xm_usb4_host0", 119 .id = SC8280XP_MASTER_USB4_0, 120 .channels = 1, 121 .buswidth = 16, 122 .num_links = 1, 123 .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, 124}; 125 126static struct qcom_icc_node xm_usb4_host1 = { 127 .name = "xm_usb4_host1", 128 .id = SC8280XP_MASTER_USB4_1, 129 .channels = 1, 130 .buswidth = 16, 131 .num_links = 1, 132 .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, 133}; 134 135static struct qcom_icc_node qhm_qdss_bam = { 136 .name = "qhm_qdss_bam", 137 .id = SC8280XP_MASTER_QDSS_BAM, 138 .channels = 1, 139 .buswidth = 4, 140 .num_links = 1, 141 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 142}; 143 144static struct qcom_icc_node qhm_qup0 = { 145 .name = "qhm_qup0", 146 .id = SC8280XP_MASTER_QUP_0, 147 .channels = 1, 148 .buswidth = 4, 149 .num_links = 1, 150 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 151}; 152 153static struct qcom_icc_node qnm_a2noc_cfg = { 154 .name = "qnm_a2noc_cfg", 155 .id = SC8280XP_MASTER_A2NOC_CFG, 156 .channels = 1, 157 .buswidth = 4, 158 .num_links = 1, 159 .links = { SC8280XP_SLAVE_SERVICE_A2NOC }, 160}; 161 162static struct qcom_icc_node qxm_crypto = { 163 .name = "qxm_crypto", 164 .id = SC8280XP_MASTER_CRYPTO, 165 .channels = 1, 166 .buswidth = 8, 167 .num_links = 1, 168 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 169}; 170 171static struct qcom_icc_node qxm_sensorss_q6 = { 172 .name = "qxm_sensorss_q6", 173 .id = SC8280XP_MASTER_SENSORS_PROC, 174 .channels = 1, 175 .buswidth = 8, 176 .num_links = 1, 177 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 178}; 179 180static struct qcom_icc_node qxm_sp = { 181 .name = "qxm_sp", 182 .id = SC8280XP_MASTER_SP, 183 .channels = 1, 184 .buswidth = 8, 185 .num_links = 1, 186 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 187}; 188 189static struct qcom_icc_node xm_emac_0 = { 190 .name = "xm_emac_0", 191 .id = SC8280XP_MASTER_EMAC, 192 .channels = 1, 193 .buswidth = 8, 194 .num_links = 1, 195 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 196}; 197 198static struct qcom_icc_node xm_pcie3_0 = { 199 .name = "xm_pcie3_0", 200 .id = SC8280XP_MASTER_PCIE_0, 201 .channels = 1, 202 .buswidth = 16, 203 .num_links = 1, 204 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 205}; 206 207static struct qcom_icc_node xm_pcie3_1 = { 208 .name = "xm_pcie3_1", 209 .id = SC8280XP_MASTER_PCIE_1, 210 .channels = 1, 211 .buswidth = 16, 212 .num_links = 1, 213 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 214}; 215 216static struct qcom_icc_node xm_pcie3_2a = { 217 .name = "xm_pcie3_2a", 218 .id = SC8280XP_MASTER_PCIE_2A, 219 .channels = 1, 220 .buswidth = 16, 221 .num_links = 1, 222 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 223}; 224 225static struct qcom_icc_node xm_pcie3_2b = { 226 .name = "xm_pcie3_2b", 227 .id = SC8280XP_MASTER_PCIE_2B, 228 .channels = 1, 229 .buswidth = 8, 230 .num_links = 1, 231 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 232}; 233 234static struct qcom_icc_node xm_pcie3_3a = { 235 .name = "xm_pcie3_3a", 236 .id = SC8280XP_MASTER_PCIE_3A, 237 .channels = 1, 238 .buswidth = 16, 239 .num_links = 1, 240 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 241}; 242 243static struct qcom_icc_node xm_pcie3_3b = { 244 .name = "xm_pcie3_3b", 245 .id = SC8280XP_MASTER_PCIE_3B, 246 .channels = 1, 247 .buswidth = 8, 248 .num_links = 1, 249 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 250}; 251 252static struct qcom_icc_node xm_pcie3_4 = { 253 .name = "xm_pcie3_4", 254 .id = SC8280XP_MASTER_PCIE_4, 255 .channels = 1, 256 .buswidth = 8, 257 .num_links = 1, 258 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, 259}; 260 261static struct qcom_icc_node xm_qdss_etr = { 262 .name = "xm_qdss_etr", 263 .id = SC8280XP_MASTER_QDSS_ETR, 264 .channels = 1, 265 .buswidth = 8, 266 .num_links = 1, 267 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 268}; 269 270static struct qcom_icc_node xm_sdc2 = { 271 .name = "xm_sdc2", 272 .id = SC8280XP_MASTER_SDCC_2, 273 .channels = 1, 274 .buswidth = 8, 275 .num_links = 1, 276 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 277}; 278 279static struct qcom_icc_node xm_ufs_card = { 280 .name = "xm_ufs_card", 281 .id = SC8280XP_MASTER_UFS_CARD, 282 .channels = 1, 283 .buswidth = 8, 284 .num_links = 1, 285 .links = { SC8280XP_SLAVE_A2NOC_SNOC }, 286}; 287 288static struct qcom_icc_node qup0_core_master = { 289 .name = "qup0_core_master", 290 .id = SC8280XP_MASTER_QUP_CORE_0, 291 .channels = 1, 292 .buswidth = 4, 293 .num_links = 1, 294 .links = { SC8280XP_SLAVE_QUP_CORE_0 }, 295}; 296 297static struct qcom_icc_node qup1_core_master = { 298 .name = "qup1_core_master", 299 .id = SC8280XP_MASTER_QUP_CORE_1, 300 .channels = 1, 301 .buswidth = 4, 302 .num_links = 1, 303 .links = { SC8280XP_SLAVE_QUP_CORE_1 }, 304}; 305 306static struct qcom_icc_node qup2_core_master = { 307 .name = "qup2_core_master", 308 .id = SC8280XP_MASTER_QUP_CORE_2, 309 .channels = 1, 310 .buswidth = 4, 311 .num_links = 1, 312 .links = { SC8280XP_SLAVE_QUP_CORE_2 }, 313}; 314 315static struct qcom_icc_node qnm_gemnoc_cnoc = { 316 .name = "qnm_gemnoc_cnoc", 317 .id = SC8280XP_MASTER_GEM_NOC_CNOC, 318 .channels = 1, 319 .buswidth = 16, 320 .num_links = 76, 321 .links = { SC8280XP_SLAVE_AHB2PHY_0, 322 SC8280XP_SLAVE_AHB2PHY_1, 323 SC8280XP_SLAVE_AHB2PHY_2, 324 SC8280XP_SLAVE_AOSS, 325 SC8280XP_SLAVE_APPSS, 326 SC8280XP_SLAVE_CAMERA_CFG, 327 SC8280XP_SLAVE_CLK_CTL, 328 SC8280XP_SLAVE_CDSP_CFG, 329 SC8280XP_SLAVE_CDSP1_CFG, 330 SC8280XP_SLAVE_RBCPR_CX_CFG, 331 SC8280XP_SLAVE_RBCPR_MMCX_CFG, 332 SC8280XP_SLAVE_RBCPR_MX_CFG, 333 SC8280XP_SLAVE_CPR_NSPCX, 334 SC8280XP_SLAVE_CRYPTO_0_CFG, 335 SC8280XP_SLAVE_CX_RDPM, 336 SC8280XP_SLAVE_DCC_CFG, 337 SC8280XP_SLAVE_DISPLAY_CFG, 338 SC8280XP_SLAVE_DISPLAY1_CFG, 339 SC8280XP_SLAVE_EMAC_CFG, 340 SC8280XP_SLAVE_EMAC1_CFG, 341 SC8280XP_SLAVE_GFX3D_CFG, 342 SC8280XP_SLAVE_HWKM, 343 SC8280XP_SLAVE_IMEM_CFG, 344 SC8280XP_SLAVE_IPA_CFG, 345 SC8280XP_SLAVE_IPC_ROUTER_CFG, 346 SC8280XP_SLAVE_LPASS, 347 SC8280XP_SLAVE_MX_RDPM, 348 SC8280XP_SLAVE_MXC_RDPM, 349 SC8280XP_SLAVE_PCIE_0_CFG, 350 SC8280XP_SLAVE_PCIE_1_CFG, 351 SC8280XP_SLAVE_PCIE_2A_CFG, 352 SC8280XP_SLAVE_PCIE_2B_CFG, 353 SC8280XP_SLAVE_PCIE_3A_CFG, 354 SC8280XP_SLAVE_PCIE_3B_CFG, 355 SC8280XP_SLAVE_PCIE_4_CFG, 356 SC8280XP_SLAVE_PCIE_RSC_CFG, 357 SC8280XP_SLAVE_PDM, 358 SC8280XP_SLAVE_PIMEM_CFG, 359 SC8280XP_SLAVE_PKA_WRAPPER_CFG, 360 SC8280XP_SLAVE_PMU_WRAPPER_CFG, 361 SC8280XP_SLAVE_QDSS_CFG, 362 SC8280XP_SLAVE_QSPI_0, 363 SC8280XP_SLAVE_QUP_0, 364 SC8280XP_SLAVE_QUP_1, 365 SC8280XP_SLAVE_QUP_2, 366 SC8280XP_SLAVE_SDCC_2, 367 SC8280XP_SLAVE_SDCC_4, 368 SC8280XP_SLAVE_SECURITY, 369 SC8280XP_SLAVE_SMMUV3_CFG, 370 SC8280XP_SLAVE_SMSS_CFG, 371 SC8280XP_SLAVE_SPSS_CFG, 372 SC8280XP_SLAVE_TCSR, 373 SC8280XP_SLAVE_TLMM, 374 SC8280XP_SLAVE_UFS_CARD_CFG, 375 SC8280XP_SLAVE_UFS_MEM_CFG, 376 SC8280XP_SLAVE_USB3_0, 377 SC8280XP_SLAVE_USB3_1, 378 SC8280XP_SLAVE_USB3_MP, 379 SC8280XP_SLAVE_USB4_0, 380 SC8280XP_SLAVE_USB4_1, 381 SC8280XP_SLAVE_VENUS_CFG, 382 SC8280XP_SLAVE_VSENSE_CTRL_CFG, 383 SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, 384 SC8280XP_SLAVE_A1NOC_CFG, 385 SC8280XP_SLAVE_A2NOC_CFG, 386 SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, 387 SC8280XP_SLAVE_DDRSS_CFG, 388 SC8280XP_SLAVE_CNOC_MNOC_CFG, 389 SC8280XP_SLAVE_SNOC_CFG, 390 SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, 391 SC8280XP_SLAVE_IMEM, 392 SC8280XP_SLAVE_PIMEM, 393 SC8280XP_SLAVE_SERVICE_CNOC, 394 SC8280XP_SLAVE_QDSS_STM, 395 SC8280XP_SLAVE_SMSS, 396 SC8280XP_SLAVE_TCU 397 }, 398}; 399 400static struct qcom_icc_node qnm_gemnoc_pcie = { 401 .name = "qnm_gemnoc_pcie", 402 .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC, 403 .channels = 1, 404 .buswidth = 16, 405 .num_links = 7, 406 .links = { SC8280XP_SLAVE_PCIE_0, 407 SC8280XP_SLAVE_PCIE_1, 408 SC8280XP_SLAVE_PCIE_2A, 409 SC8280XP_SLAVE_PCIE_2B, 410 SC8280XP_SLAVE_PCIE_3A, 411 SC8280XP_SLAVE_PCIE_3B, 412 SC8280XP_SLAVE_PCIE_4 413 }, 414}; 415 416static struct qcom_icc_node qnm_cnoc_dc_noc = { 417 .name = "qnm_cnoc_dc_noc", 418 .id = SC8280XP_MASTER_CNOC_DC_NOC, 419 .channels = 1, 420 .buswidth = 4, 421 .num_links = 2, 422 .links = { SC8280XP_SLAVE_LLCC_CFG, 423 SC8280XP_SLAVE_GEM_NOC_CFG 424 }, 425}; 426 427static struct qcom_icc_node alm_gpu_tcu = { 428 .name = "alm_gpu_tcu", 429 .id = SC8280XP_MASTER_GPU_TCU, 430 .channels = 1, 431 .buswidth = 8, 432 .num_links = 2, 433 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 434 SC8280XP_SLAVE_LLCC 435 }, 436}; 437 438static struct qcom_icc_node alm_pcie_tcu = { 439 .name = "alm_pcie_tcu", 440 .id = SC8280XP_MASTER_PCIE_TCU, 441 .channels = 1, 442 .buswidth = 8, 443 .num_links = 2, 444 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 445 SC8280XP_SLAVE_LLCC 446 }, 447}; 448 449static struct qcom_icc_node alm_sys_tcu = { 450 .name = "alm_sys_tcu", 451 .id = SC8280XP_MASTER_SYS_TCU, 452 .channels = 1, 453 .buswidth = 8, 454 .num_links = 2, 455 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 456 SC8280XP_SLAVE_LLCC 457 }, 458}; 459 460static struct qcom_icc_node chm_apps = { 461 .name = "chm_apps", 462 .id = SC8280XP_MASTER_APPSS_PROC, 463 .channels = 2, 464 .buswidth = 32, 465 .num_links = 3, 466 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 467 SC8280XP_SLAVE_LLCC, 468 SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 469 }, 470}; 471 472static struct qcom_icc_node qnm_cmpnoc0 = { 473 .name = "qnm_cmpnoc0", 474 .id = SC8280XP_MASTER_COMPUTE_NOC, 475 .channels = 2, 476 .buswidth = 32, 477 .num_links = 2, 478 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 479 SC8280XP_SLAVE_LLCC 480 }, 481}; 482 483static struct qcom_icc_node qnm_cmpnoc1 = { 484 .name = "qnm_cmpnoc1", 485 .id = SC8280XP_MASTER_COMPUTE_NOC_1, 486 .channels = 2, 487 .buswidth = 32, 488 .num_links = 2, 489 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 490 SC8280XP_SLAVE_LLCC 491 }, 492}; 493 494static struct qcom_icc_node qnm_gemnoc_cfg = { 495 .name = "qnm_gemnoc_cfg", 496 .id = SC8280XP_MASTER_GEM_NOC_CFG, 497 .channels = 1, 498 .buswidth = 4, 499 .num_links = 3, 500 .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1, 501 SC8280XP_SLAVE_SERVICE_GEM_NOC_2, 502 SC8280XP_SLAVE_SERVICE_GEM_NOC 503 }, 504}; 505 506static struct qcom_icc_node qnm_gpu = { 507 .name = "qnm_gpu", 508 .id = SC8280XP_MASTER_GFX3D, 509 .channels = 4, 510 .buswidth = 32, 511 .num_links = 2, 512 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 513 SC8280XP_SLAVE_LLCC 514 }, 515}; 516 517static struct qcom_icc_node qnm_mnoc_hf = { 518 .name = "qnm_mnoc_hf", 519 .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC, 520 .channels = 2, 521 .buswidth = 32, 522 .num_links = 2, 523 .links = { SC8280XP_SLAVE_LLCC, 524 SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 525 }, 526}; 527 528static struct qcom_icc_node qnm_mnoc_sf = { 529 .name = "qnm_mnoc_sf", 530 .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC, 531 .channels = 2, 532 .buswidth = 32, 533 .num_links = 2, 534 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 535 SC8280XP_SLAVE_LLCC 536 }, 537}; 538 539static struct qcom_icc_node qnm_pcie = { 540 .name = "qnm_pcie", 541 .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC, 542 .channels = 1, 543 .buswidth = 32, 544 .num_links = 2, 545 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 546 SC8280XP_SLAVE_LLCC 547 }, 548}; 549 550static struct qcom_icc_node qnm_snoc_gc = { 551 .name = "qnm_snoc_gc", 552 .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC, 553 .channels = 1, 554 .buswidth = 8, 555 .num_links = 1, 556 .links = { SC8280XP_SLAVE_LLCC }, 557}; 558 559static struct qcom_icc_node qnm_snoc_sf = { 560 .name = "qnm_snoc_sf", 561 .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC, 562 .channels = 1, 563 .buswidth = 16, 564 .num_links = 3, 565 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, 566 SC8280XP_SLAVE_LLCC, 567 SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC }, 568}; 569 570static struct qcom_icc_node qhm_config_noc = { 571 .name = "qhm_config_noc", 572 .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC, 573 .channels = 1, 574 .buswidth = 4, 575 .num_links = 6, 576 .links = { SC8280XP_SLAVE_LPASS_CORE_CFG, 577 SC8280XP_SLAVE_LPASS_LPI_CFG, 578 SC8280XP_SLAVE_LPASS_MPU_CFG, 579 SC8280XP_SLAVE_LPASS_TOP_CFG, 580 SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, 581 SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 582 }, 583}; 584 585static struct qcom_icc_node qxm_lpass_dsp = { 586 .name = "qxm_lpass_dsp", 587 .id = SC8280XP_MASTER_LPASS_PROC, 588 .channels = 1, 589 .buswidth = 8, 590 .num_links = 4, 591 .links = { SC8280XP_SLAVE_LPASS_TOP_CFG, 592 SC8280XP_SLAVE_LPASS_SNOC, 593 SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, 594 SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 595 }, 596}; 597 598static struct qcom_icc_node llcc_mc = { 599 .name = "llcc_mc", 600 .id = SC8280XP_MASTER_LLCC, 601 .channels = 8, 602 .buswidth = 4, 603 .num_links = 1, 604 .links = { SC8280XP_SLAVE_EBI1 }, 605}; 606 607static struct qcom_icc_node qnm_camnoc_hf = { 608 .name = "qnm_camnoc_hf", 609 .id = SC8280XP_MASTER_CAMNOC_HF, 610 .channels = 2, 611 .buswidth = 32, 612 .num_links = 1, 613 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, 614}; 615 616static struct qcom_icc_node qnm_mdp0_0 = { 617 .name = "qnm_mdp0_0", 618 .id = SC8280XP_MASTER_MDP0, 619 .channels = 1, 620 .buswidth = 32, 621 .num_links = 1, 622 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, 623}; 624 625static struct qcom_icc_node qnm_mdp0_1 = { 626 .name = "qnm_mdp0_1", 627 .id = SC8280XP_MASTER_MDP1, 628 .channels = 1, 629 .buswidth = 32, 630 .num_links = 1, 631 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, 632}; 633 634static struct qcom_icc_node qnm_mdp1_0 = { 635 .name = "qnm_mdp1_0", 636 .id = SC8280XP_MASTER_MDP_CORE1_0, 637 .channels = 1, 638 .buswidth = 32, 639 .num_links = 1, 640 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, 641}; 642 643static struct qcom_icc_node qnm_mdp1_1 = { 644 .name = "qnm_mdp1_1", 645 .id = SC8280XP_MASTER_MDP_CORE1_1, 646 .channels = 1, 647 .buswidth = 32, 648 .num_links = 1, 649 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, 650}; 651 652static struct qcom_icc_node qnm_mnoc_cfg = { 653 .name = "qnm_mnoc_cfg", 654 .id = SC8280XP_MASTER_CNOC_MNOC_CFG, 655 .channels = 1, 656 .buswidth = 4, 657 .num_links = 1, 658 .links = { SC8280XP_SLAVE_SERVICE_MNOC }, 659}; 660 661static struct qcom_icc_node qnm_rot_0 = { 662 .name = "qnm_rot_0", 663 .id = SC8280XP_MASTER_ROTATOR, 664 .channels = 1, 665 .buswidth = 32, 666 .num_links = 1, 667 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 668}; 669 670static struct qcom_icc_node qnm_rot_1 = { 671 .name = "qnm_rot_1", 672 .id = SC8280XP_MASTER_ROTATOR_1, 673 .channels = 1, 674 .buswidth = 32, 675 .num_links = 1, 676 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 677}; 678 679static struct qcom_icc_node qnm_video0 = { 680 .name = "qnm_video0", 681 .id = SC8280XP_MASTER_VIDEO_P0, 682 .channels = 1, 683 .buswidth = 32, 684 .num_links = 1, 685 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 686}; 687 688static struct qcom_icc_node qnm_video1 = { 689 .name = "qnm_video1", 690 .id = SC8280XP_MASTER_VIDEO_P1, 691 .channels = 1, 692 .buswidth = 32, 693 .num_links = 1, 694 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 695}; 696 697static struct qcom_icc_node qnm_video_cvp = { 698 .name = "qnm_video_cvp", 699 .id = SC8280XP_MASTER_VIDEO_PROC, 700 .channels = 1, 701 .buswidth = 32, 702 .num_links = 1, 703 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 704}; 705 706static struct qcom_icc_node qxm_camnoc_icp = { 707 .name = "qxm_camnoc_icp", 708 .id = SC8280XP_MASTER_CAMNOC_ICP, 709 .channels = 1, 710 .buswidth = 8, 711 .num_links = 1, 712 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 713}; 714 715static struct qcom_icc_node qxm_camnoc_sf = { 716 .name = "qxm_camnoc_sf", 717 .id = SC8280XP_MASTER_CAMNOC_SF, 718 .channels = 1, 719 .buswidth = 32, 720 .num_links = 1, 721 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, 722}; 723 724static struct qcom_icc_node qhm_nsp_noc_config = { 725 .name = "qhm_nsp_noc_config", 726 .id = SC8280XP_MASTER_CDSP_NOC_CFG, 727 .channels = 1, 728 .buswidth = 4, 729 .num_links = 1, 730 .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC }, 731}; 732 733static struct qcom_icc_node qxm_nsp = { 734 .name = "qxm_nsp", 735 .id = SC8280XP_MASTER_CDSP_PROC, 736 .channels = 2, 737 .buswidth = 32, 738 .num_links = 2, 739 .links = { SC8280XP_SLAVE_CDSP_MEM_NOC, 740 SC8280XP_SLAVE_NSP_XFR 741 }, 742}; 743 744static struct qcom_icc_node qhm_nspb_noc_config = { 745 .name = "qhm_nspb_noc_config", 746 .id = SC8280XP_MASTER_CDSPB_NOC_CFG, 747 .channels = 1, 748 .buswidth = 4, 749 .num_links = 1, 750 .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC }, 751}; 752 753static struct qcom_icc_node qxm_nspb = { 754 .name = "qxm_nspb", 755 .id = SC8280XP_MASTER_CDSP_PROC_B, 756 .channels = 2, 757 .buswidth = 32, 758 .num_links = 2, 759 .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC, 760 SC8280XP_SLAVE_NSPB_XFR 761 }, 762}; 763 764static struct qcom_icc_node qnm_aggre1_noc = { 765 .name = "qnm_aggre1_noc", 766 .id = SC8280XP_MASTER_A1NOC_SNOC, 767 .channels = 1, 768 .buswidth = 16, 769 .num_links = 1, 770 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, 771}; 772 773static struct qcom_icc_node qnm_aggre2_noc = { 774 .name = "qnm_aggre2_noc", 775 .id = SC8280XP_MASTER_A2NOC_SNOC, 776 .channels = 1, 777 .buswidth = 16, 778 .num_links = 1, 779 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, 780}; 781 782static struct qcom_icc_node qnm_aggre_usb_noc = { 783 .name = "qnm_aggre_usb_noc", 784 .id = SC8280XP_MASTER_USB_NOC_SNOC, 785 .channels = 1, 786 .buswidth = 16, 787 .num_links = 1, 788 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, 789}; 790 791static struct qcom_icc_node qnm_lpass_noc = { 792 .name = "qnm_lpass_noc", 793 .id = SC8280XP_MASTER_LPASS_ANOC, 794 .channels = 1, 795 .buswidth = 16, 796 .num_links = 1, 797 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, 798}; 799 800static struct qcom_icc_node qnm_snoc_cfg = { 801 .name = "qnm_snoc_cfg", 802 .id = SC8280XP_MASTER_SNOC_CFG, 803 .channels = 1, 804 .buswidth = 4, 805 .num_links = 1, 806 .links = { SC8280XP_SLAVE_SERVICE_SNOC }, 807}; 808 809static struct qcom_icc_node qxm_pimem = { 810 .name = "qxm_pimem", 811 .id = SC8280XP_MASTER_PIMEM, 812 .channels = 1, 813 .buswidth = 8, 814 .num_links = 1, 815 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, 816}; 817 818static struct qcom_icc_node xm_gic = { 819 .name = "xm_gic", 820 .id = SC8280XP_MASTER_GIC, 821 .channels = 1, 822 .buswidth = 8, 823 .num_links = 1, 824 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, 825}; 826 827static struct qcom_icc_node qns_a1noc_snoc = { 828 .name = "qns_a1noc_snoc", 829 .id = SC8280XP_SLAVE_A1NOC_SNOC, 830 .channels = 1, 831 .buswidth = 16, 832 .num_links = 1, 833 .links = { SC8280XP_MASTER_A1NOC_SNOC }, 834}; 835 836static struct qcom_icc_node qns_aggre_usb_snoc = { 837 .name = "qns_aggre_usb_snoc", 838 .id = SC8280XP_SLAVE_USB_NOC_SNOC, 839 .channels = 1, 840 .buswidth = 16, 841 .num_links = 1, 842 .links = { SC8280XP_MASTER_USB_NOC_SNOC }, 843}; 844 845static struct qcom_icc_node srvc_aggre1_noc = { 846 .name = "srvc_aggre1_noc", 847 .id = SC8280XP_SLAVE_SERVICE_A1NOC, 848 .channels = 1, 849 .buswidth = 4, 850}; 851 852static struct qcom_icc_node qns_a2noc_snoc = { 853 .name = "qns_a2noc_snoc", 854 .id = SC8280XP_SLAVE_A2NOC_SNOC, 855 .channels = 1, 856 .buswidth = 16, 857 .num_links = 1, 858 .links = { SC8280XP_MASTER_A2NOC_SNOC }, 859}; 860 861static struct qcom_icc_node qns_pcie_gem_noc = { 862 .name = "qns_pcie_gem_noc", 863 .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC, 864 .channels = 1, 865 .buswidth = 32, 866 .num_links = 1, 867 .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC }, 868}; 869 870static struct qcom_icc_node srvc_aggre2_noc = { 871 .name = "srvc_aggre2_noc", 872 .id = SC8280XP_SLAVE_SERVICE_A2NOC, 873 .channels = 1, 874 .buswidth = 4, 875}; 876 877static struct qcom_icc_node qup0_core_slave = { 878 .name = "qup0_core_slave", 879 .id = SC8280XP_SLAVE_QUP_CORE_0, 880 .channels = 1, 881 .buswidth = 4, 882}; 883 884static struct qcom_icc_node qup1_core_slave = { 885 .name = "qup1_core_slave", 886 .id = SC8280XP_SLAVE_QUP_CORE_1, 887 .channels = 1, 888 .buswidth = 4, 889}; 890 891static struct qcom_icc_node qup2_core_slave = { 892 .name = "qup2_core_slave", 893 .id = SC8280XP_SLAVE_QUP_CORE_2, 894 .channels = 1, 895 .buswidth = 4, 896}; 897 898static struct qcom_icc_node qhs_ahb2phy0 = { 899 .name = "qhs_ahb2phy0", 900 .id = SC8280XP_SLAVE_AHB2PHY_0, 901 .channels = 1, 902 .buswidth = 4, 903}; 904 905static struct qcom_icc_node qhs_ahb2phy1 = { 906 .name = "qhs_ahb2phy1", 907 .id = SC8280XP_SLAVE_AHB2PHY_1, 908 .channels = 1, 909 .buswidth = 4, 910}; 911 912static struct qcom_icc_node qhs_ahb2phy2 = { 913 .name = "qhs_ahb2phy2", 914 .id = SC8280XP_SLAVE_AHB2PHY_2, 915 .channels = 1, 916 .buswidth = 4, 917}; 918 919static struct qcom_icc_node qhs_aoss = { 920 .name = "qhs_aoss", 921 .id = SC8280XP_SLAVE_AOSS, 922 .channels = 1, 923 .buswidth = 4, 924}; 925 926static struct qcom_icc_node qhs_apss = { 927 .name = "qhs_apss", 928 .id = SC8280XP_SLAVE_APPSS, 929 .channels = 1, 930 .buswidth = 8, 931}; 932 933static struct qcom_icc_node qhs_camera_cfg = { 934 .name = "qhs_camera_cfg", 935 .id = SC8280XP_SLAVE_CAMERA_CFG, 936 .channels = 1, 937 .buswidth = 4, 938}; 939 940static struct qcom_icc_node qhs_clk_ctl = { 941 .name = "qhs_clk_ctl", 942 .id = SC8280XP_SLAVE_CLK_CTL, 943 .channels = 1, 944 .buswidth = 4, 945}; 946 947static struct qcom_icc_node qhs_compute0_cfg = { 948 .name = "qhs_compute0_cfg", 949 .id = SC8280XP_SLAVE_CDSP_CFG, 950 .channels = 1, 951 .buswidth = 4, 952 .num_links = 1, 953 .links = { SC8280XP_MASTER_CDSP_NOC_CFG }, 954}; 955 956static struct qcom_icc_node qhs_compute1_cfg = { 957 .name = "qhs_compute1_cfg", 958 .id = SC8280XP_SLAVE_CDSP1_CFG, 959 .channels = 1, 960 .buswidth = 4, 961 .num_links = 1, 962 .links = { SC8280XP_MASTER_CDSPB_NOC_CFG }, 963}; 964 965static struct qcom_icc_node qhs_cpr_cx = { 966 .name = "qhs_cpr_cx", 967 .id = SC8280XP_SLAVE_RBCPR_CX_CFG, 968 .channels = 1, 969 .buswidth = 4, 970}; 971 972static struct qcom_icc_node qhs_cpr_mmcx = { 973 .name = "qhs_cpr_mmcx", 974 .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG, 975 .channels = 1, 976 .buswidth = 4, 977}; 978 979static struct qcom_icc_node qhs_cpr_mx = { 980 .name = "qhs_cpr_mx", 981 .id = SC8280XP_SLAVE_RBCPR_MX_CFG, 982 .channels = 1, 983 .buswidth = 4, 984}; 985 986static struct qcom_icc_node qhs_cpr_nspcx = { 987 .name = "qhs_cpr_nspcx", 988 .id = SC8280XP_SLAVE_CPR_NSPCX, 989 .channels = 1, 990 .buswidth = 4, 991}; 992 993static struct qcom_icc_node qhs_crypto0_cfg = { 994 .name = "qhs_crypto0_cfg", 995 .id = SC8280XP_SLAVE_CRYPTO_0_CFG, 996 .channels = 1, 997 .buswidth = 4, 998}; 999 1000static struct qcom_icc_node qhs_cx_rdpm = { 1001 .name = "qhs_cx_rdpm", 1002 .id = SC8280XP_SLAVE_CX_RDPM, 1003 .channels = 1, 1004 .buswidth = 4, 1005}; 1006 1007static struct qcom_icc_node qhs_dcc_cfg = { 1008 .name = "qhs_dcc_cfg", 1009 .id = SC8280XP_SLAVE_DCC_CFG, 1010 .channels = 1, 1011 .buswidth = 4, 1012}; 1013 1014static struct qcom_icc_node qhs_display0_cfg = { 1015 .name = "qhs_display0_cfg", 1016 .id = SC8280XP_SLAVE_DISPLAY_CFG, 1017 .channels = 1, 1018 .buswidth = 4, 1019}; 1020 1021static struct qcom_icc_node qhs_display1_cfg = { 1022 .name = "qhs_display1_cfg", 1023 .id = SC8280XP_SLAVE_DISPLAY1_CFG, 1024 .channels = 1, 1025 .buswidth = 4, 1026}; 1027 1028static struct qcom_icc_node qhs_emac0_cfg = { 1029 .name = "qhs_emac0_cfg", 1030 .id = SC8280XP_SLAVE_EMAC_CFG, 1031 .channels = 1, 1032 .buswidth = 4, 1033}; 1034 1035static struct qcom_icc_node qhs_emac1_cfg = { 1036 .name = "qhs_emac1_cfg", 1037 .id = SC8280XP_SLAVE_EMAC1_CFG, 1038 .channels = 1, 1039 .buswidth = 4, 1040}; 1041 1042static struct qcom_icc_node qhs_gpuss_cfg = { 1043 .name = "qhs_gpuss_cfg", 1044 .id = SC8280XP_SLAVE_GFX3D_CFG, 1045 .channels = 1, 1046 .buswidth = 8, 1047}; 1048 1049static struct qcom_icc_node qhs_hwkm = { 1050 .name = "qhs_hwkm", 1051 .id = SC8280XP_SLAVE_HWKM, 1052 .channels = 1, 1053 .buswidth = 4, 1054}; 1055 1056static struct qcom_icc_node qhs_imem_cfg = { 1057 .name = "qhs_imem_cfg", 1058 .id = SC8280XP_SLAVE_IMEM_CFG, 1059 .channels = 1, 1060 .buswidth = 4, 1061}; 1062 1063static struct qcom_icc_node qhs_ipa = { 1064 .name = "qhs_ipa", 1065 .id = SC8280XP_SLAVE_IPA_CFG, 1066 .channels = 1, 1067 .buswidth = 4, 1068}; 1069 1070static struct qcom_icc_node qhs_ipc_router = { 1071 .name = "qhs_ipc_router", 1072 .id = SC8280XP_SLAVE_IPC_ROUTER_CFG, 1073 .channels = 1, 1074 .buswidth = 4, 1075}; 1076 1077static struct qcom_icc_node qhs_lpass_cfg = { 1078 .name = "qhs_lpass_cfg", 1079 .id = SC8280XP_SLAVE_LPASS, 1080 .channels = 1, 1081 .buswidth = 4, 1082 .num_links = 1, 1083 .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC }, 1084}; 1085 1086static struct qcom_icc_node qhs_mx_rdpm = { 1087 .name = "qhs_mx_rdpm", 1088 .id = SC8280XP_SLAVE_MX_RDPM, 1089 .channels = 1, 1090 .buswidth = 4, 1091}; 1092 1093static struct qcom_icc_node qhs_mxc_rdpm = { 1094 .name = "qhs_mxc_rdpm", 1095 .id = SC8280XP_SLAVE_MXC_RDPM, 1096 .channels = 1, 1097 .buswidth = 4, 1098}; 1099 1100static struct qcom_icc_node qhs_pcie0_cfg = { 1101 .name = "qhs_pcie0_cfg", 1102 .id = SC8280XP_SLAVE_PCIE_0_CFG, 1103 .channels = 1, 1104 .buswidth = 4, 1105}; 1106 1107static struct qcom_icc_node qhs_pcie1_cfg = { 1108 .name = "qhs_pcie1_cfg", 1109 .id = SC8280XP_SLAVE_PCIE_1_CFG, 1110 .channels = 1, 1111 .buswidth = 4, 1112}; 1113 1114static struct qcom_icc_node qhs_pcie2a_cfg = { 1115 .name = "qhs_pcie2a_cfg", 1116 .id = SC8280XP_SLAVE_PCIE_2A_CFG, 1117 .channels = 1, 1118 .buswidth = 4, 1119}; 1120 1121static struct qcom_icc_node qhs_pcie2b_cfg = { 1122 .name = "qhs_pcie2b_cfg", 1123 .id = SC8280XP_SLAVE_PCIE_2B_CFG, 1124 .channels = 1, 1125 .buswidth = 4, 1126}; 1127 1128static struct qcom_icc_node qhs_pcie3a_cfg = { 1129 .name = "qhs_pcie3a_cfg", 1130 .id = SC8280XP_SLAVE_PCIE_3A_CFG, 1131 .channels = 1, 1132 .buswidth = 4, 1133}; 1134 1135static struct qcom_icc_node qhs_pcie3b_cfg = { 1136 .name = "qhs_pcie3b_cfg", 1137 .id = SC8280XP_SLAVE_PCIE_3B_CFG, 1138 .channels = 1, 1139 .buswidth = 4, 1140}; 1141 1142static struct qcom_icc_node qhs_pcie4_cfg = { 1143 .name = "qhs_pcie4_cfg", 1144 .id = SC8280XP_SLAVE_PCIE_4_CFG, 1145 .channels = 1, 1146 .buswidth = 4, 1147}; 1148 1149static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1150 .name = "qhs_pcie_rsc_cfg", 1151 .id = SC8280XP_SLAVE_PCIE_RSC_CFG, 1152 .channels = 1, 1153 .buswidth = 4, 1154}; 1155 1156static struct qcom_icc_node qhs_pdm = { 1157 .name = "qhs_pdm", 1158 .id = SC8280XP_SLAVE_PDM, 1159 .channels = 1, 1160 .buswidth = 4, 1161}; 1162 1163static struct qcom_icc_node qhs_pimem_cfg = { 1164 .name = "qhs_pimem_cfg", 1165 .id = SC8280XP_SLAVE_PIMEM_CFG, 1166 .channels = 1, 1167 .buswidth = 4, 1168}; 1169 1170static struct qcom_icc_node qhs_pka_wrapper_cfg = { 1171 .name = "qhs_pka_wrapper_cfg", 1172 .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG, 1173 .channels = 1, 1174 .buswidth = 4, 1175}; 1176 1177static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 1178 .name = "qhs_pmu_wrapper_cfg", 1179 .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG, 1180 .channels = 1, 1181 .buswidth = 4, 1182}; 1183 1184static struct qcom_icc_node qhs_qdss_cfg = { 1185 .name = "qhs_qdss_cfg", 1186 .id = SC8280XP_SLAVE_QDSS_CFG, 1187 .channels = 1, 1188 .buswidth = 4, 1189}; 1190 1191static struct qcom_icc_node qhs_qspi = { 1192 .name = "qhs_qspi", 1193 .id = SC8280XP_SLAVE_QSPI_0, 1194 .channels = 1, 1195 .buswidth = 4, 1196}; 1197 1198static struct qcom_icc_node qhs_qup0 = { 1199 .name = "qhs_qup0", 1200 .id = SC8280XP_SLAVE_QUP_0, 1201 .channels = 1, 1202 .buswidth = 4, 1203}; 1204 1205static struct qcom_icc_node qhs_qup1 = { 1206 .name = "qhs_qup1", 1207 .id = SC8280XP_SLAVE_QUP_1, 1208 .channels = 1, 1209 .buswidth = 4, 1210}; 1211 1212static struct qcom_icc_node qhs_qup2 = { 1213 .name = "qhs_qup2", 1214 .id = SC8280XP_SLAVE_QUP_2, 1215 .channels = 1, 1216 .buswidth = 4, 1217}; 1218 1219static struct qcom_icc_node qhs_sdc2 = { 1220 .name = "qhs_sdc2", 1221 .id = SC8280XP_SLAVE_SDCC_2, 1222 .channels = 1, 1223 .buswidth = 4, 1224}; 1225 1226static struct qcom_icc_node qhs_sdc4 = { 1227 .name = "qhs_sdc4", 1228 .id = SC8280XP_SLAVE_SDCC_4, 1229 .channels = 1, 1230 .buswidth = 4, 1231}; 1232 1233static struct qcom_icc_node qhs_security = { 1234 .name = "qhs_security", 1235 .id = SC8280XP_SLAVE_SECURITY, 1236 .channels = 1, 1237 .buswidth = 4, 1238}; 1239 1240static struct qcom_icc_node qhs_smmuv3_cfg = { 1241 .name = "qhs_smmuv3_cfg", 1242 .id = SC8280XP_SLAVE_SMMUV3_CFG, 1243 .channels = 1, 1244 .buswidth = 8, 1245}; 1246 1247static struct qcom_icc_node qhs_smss_cfg = { 1248 .name = "qhs_smss_cfg", 1249 .id = SC8280XP_SLAVE_SMSS_CFG, 1250 .channels = 1, 1251 .buswidth = 4, 1252}; 1253 1254static struct qcom_icc_node qhs_spss_cfg = { 1255 .name = "qhs_spss_cfg", 1256 .id = SC8280XP_SLAVE_SPSS_CFG, 1257 .channels = 1, 1258 .buswidth = 4, 1259}; 1260 1261static struct qcom_icc_node qhs_tcsr = { 1262 .name = "qhs_tcsr", 1263 .id = SC8280XP_SLAVE_TCSR, 1264 .channels = 1, 1265 .buswidth = 4, 1266}; 1267 1268static struct qcom_icc_node qhs_tlmm = { 1269 .name = "qhs_tlmm", 1270 .id = SC8280XP_SLAVE_TLMM, 1271 .channels = 1, 1272 .buswidth = 4, 1273}; 1274 1275static struct qcom_icc_node qhs_ufs_card_cfg = { 1276 .name = "qhs_ufs_card_cfg", 1277 .id = SC8280XP_SLAVE_UFS_CARD_CFG, 1278 .channels = 1, 1279 .buswidth = 4, 1280}; 1281 1282static struct qcom_icc_node qhs_ufs_mem_cfg = { 1283 .name = "qhs_ufs_mem_cfg", 1284 .id = SC8280XP_SLAVE_UFS_MEM_CFG, 1285 .channels = 1, 1286 .buswidth = 4, 1287}; 1288 1289static struct qcom_icc_node qhs_usb3_0 = { 1290 .name = "qhs_usb3_0", 1291 .id = SC8280XP_SLAVE_USB3_0, 1292 .channels = 1, 1293 .buswidth = 4, 1294}; 1295 1296static struct qcom_icc_node qhs_usb3_1 = { 1297 .name = "qhs_usb3_1", 1298 .id = SC8280XP_SLAVE_USB3_1, 1299 .channels = 1, 1300 .buswidth = 4, 1301}; 1302 1303static struct qcom_icc_node qhs_usb3_mp = { 1304 .name = "qhs_usb3_mp", 1305 .id = SC8280XP_SLAVE_USB3_MP, 1306 .channels = 1, 1307 .buswidth = 4, 1308}; 1309 1310static struct qcom_icc_node qhs_usb4_host_0 = { 1311 .name = "qhs_usb4_host_0", 1312 .id = SC8280XP_SLAVE_USB4_0, 1313 .channels = 1, 1314 .buswidth = 4, 1315}; 1316 1317static struct qcom_icc_node qhs_usb4_host_1 = { 1318 .name = "qhs_usb4_host_1", 1319 .id = SC8280XP_SLAVE_USB4_1, 1320 .channels = 1, 1321 .buswidth = 4, 1322}; 1323 1324static struct qcom_icc_node qhs_venus_cfg = { 1325 .name = "qhs_venus_cfg", 1326 .id = SC8280XP_SLAVE_VENUS_CFG, 1327 .channels = 1, 1328 .buswidth = 4, 1329}; 1330 1331static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1332 .name = "qhs_vsense_ctrl_cfg", 1333 .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG, 1334 .channels = 1, 1335 .buswidth = 4, 1336}; 1337 1338static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { 1339 .name = "qhs_vsense_ctrl_r_cfg", 1340 .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, 1341 .channels = 1, 1342 .buswidth = 4, 1343}; 1344 1345static struct qcom_icc_node qns_a1_noc_cfg = { 1346 .name = "qns_a1_noc_cfg", 1347 .id = SC8280XP_SLAVE_A1NOC_CFG, 1348 .channels = 1, 1349 .buswidth = 4, 1350 .num_links = 1, 1351 .links = { SC8280XP_MASTER_A1NOC_CFG }, 1352}; 1353 1354static struct qcom_icc_node qns_a2_noc_cfg = { 1355 .name = "qns_a2_noc_cfg", 1356 .id = SC8280XP_SLAVE_A2NOC_CFG, 1357 .channels = 1, 1358 .buswidth = 4, 1359 .num_links = 1, 1360 .links = { SC8280XP_MASTER_A2NOC_CFG }, 1361}; 1362 1363static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { 1364 .name = "qns_anoc_pcie_bridge_cfg", 1365 .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, 1366 .channels = 1, 1367 .buswidth = 4, 1368}; 1369 1370static struct qcom_icc_node qns_ddrss_cfg = { 1371 .name = "qns_ddrss_cfg", 1372 .id = SC8280XP_SLAVE_DDRSS_CFG, 1373 .channels = 1, 1374 .buswidth = 4, 1375 .num_links = 1, 1376 .links = { SC8280XP_MASTER_CNOC_DC_NOC }, 1377}; 1378 1379static struct qcom_icc_node qns_mnoc_cfg = { 1380 .name = "qns_mnoc_cfg", 1381 .id = SC8280XP_SLAVE_CNOC_MNOC_CFG, 1382 .channels = 1, 1383 .buswidth = 4, 1384 .num_links = 1, 1385 .links = { SC8280XP_MASTER_CNOC_MNOC_CFG }, 1386}; 1387 1388static struct qcom_icc_node qns_snoc_cfg = { 1389 .name = "qns_snoc_cfg", 1390 .id = SC8280XP_SLAVE_SNOC_CFG, 1391 .channels = 1, 1392 .buswidth = 4, 1393 .num_links = 1, 1394 .links = { SC8280XP_MASTER_SNOC_CFG }, 1395}; 1396 1397static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { 1398 .name = "qns_snoc_sf_bridge_cfg", 1399 .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, 1400 .channels = 1, 1401 .buswidth = 4, 1402}; 1403 1404static struct qcom_icc_node qxs_imem = { 1405 .name = "qxs_imem", 1406 .id = SC8280XP_SLAVE_IMEM, 1407 .channels = 1, 1408 .buswidth = 8, 1409}; 1410 1411static struct qcom_icc_node qxs_pimem = { 1412 .name = "qxs_pimem", 1413 .id = SC8280XP_SLAVE_PIMEM, 1414 .channels = 1, 1415 .buswidth = 8, 1416}; 1417 1418static struct qcom_icc_node srvc_cnoc = { 1419 .name = "srvc_cnoc", 1420 .id = SC8280XP_SLAVE_SERVICE_CNOC, 1421 .channels = 1, 1422 .buswidth = 4, 1423}; 1424 1425static struct qcom_icc_node xs_pcie_0 = { 1426 .name = "xs_pcie_0", 1427 .id = SC8280XP_SLAVE_PCIE_0, 1428 .channels = 1, 1429 .buswidth = 16, 1430}; 1431 1432static struct qcom_icc_node xs_pcie_1 = { 1433 .name = "xs_pcie_1", 1434 .id = SC8280XP_SLAVE_PCIE_1, 1435 .channels = 1, 1436 .buswidth = 16, 1437}; 1438 1439static struct qcom_icc_node xs_pcie_2a = { 1440 .name = "xs_pcie_2a", 1441 .id = SC8280XP_SLAVE_PCIE_2A, 1442 .channels = 1, 1443 .buswidth = 16, 1444}; 1445 1446static struct qcom_icc_node xs_pcie_2b = { 1447 .name = "xs_pcie_2b", 1448 .id = SC8280XP_SLAVE_PCIE_2B, 1449 .channels = 1, 1450 .buswidth = 8, 1451}; 1452 1453static struct qcom_icc_node xs_pcie_3a = { 1454 .name = "xs_pcie_3a", 1455 .id = SC8280XP_SLAVE_PCIE_3A, 1456 .channels = 1, 1457 .buswidth = 16, 1458}; 1459 1460static struct qcom_icc_node xs_pcie_3b = { 1461 .name = "xs_pcie_3b", 1462 .id = SC8280XP_SLAVE_PCIE_3B, 1463 .channels = 1, 1464 .buswidth = 8, 1465}; 1466 1467static struct qcom_icc_node xs_pcie_4 = { 1468 .name = "xs_pcie_4", 1469 .id = SC8280XP_SLAVE_PCIE_4, 1470 .channels = 1, 1471 .buswidth = 8, 1472}; 1473 1474static struct qcom_icc_node xs_qdss_stm = { 1475 .name = "xs_qdss_stm", 1476 .id = SC8280XP_SLAVE_QDSS_STM, 1477 .channels = 1, 1478 .buswidth = 4, 1479}; 1480 1481static struct qcom_icc_node xs_smss = { 1482 .name = "xs_smss", 1483 .id = SC8280XP_SLAVE_SMSS, 1484 .channels = 1, 1485 .buswidth = 8, 1486}; 1487 1488static struct qcom_icc_node xs_sys_tcu_cfg = { 1489 .name = "xs_sys_tcu_cfg", 1490 .id = SC8280XP_SLAVE_TCU, 1491 .channels = 1, 1492 .buswidth = 8, 1493}; 1494 1495static struct qcom_icc_node qhs_llcc = { 1496 .name = "qhs_llcc", 1497 .id = SC8280XP_SLAVE_LLCC_CFG, 1498 .channels = 1, 1499 .buswidth = 4, 1500}; 1501 1502static struct qcom_icc_node qns_gemnoc = { 1503 .name = "qns_gemnoc", 1504 .id = SC8280XP_SLAVE_GEM_NOC_CFG, 1505 .channels = 1, 1506 .buswidth = 4, 1507 .num_links = 1, 1508 .links = { SC8280XP_MASTER_GEM_NOC_CFG }, 1509}; 1510 1511static struct qcom_icc_node qns_gem_noc_cnoc = { 1512 .name = "qns_gem_noc_cnoc", 1513 .id = SC8280XP_SLAVE_GEM_NOC_CNOC, 1514 .channels = 1, 1515 .buswidth = 16, 1516 .num_links = 1, 1517 .links = { SC8280XP_MASTER_GEM_NOC_CNOC }, 1518}; 1519 1520static struct qcom_icc_node qns_llcc = { 1521 .name = "qns_llcc", 1522 .id = SC8280XP_SLAVE_LLCC, 1523 .channels = 8, 1524 .buswidth = 16, 1525 .num_links = 1, 1526 .links = { SC8280XP_MASTER_LLCC }, 1527}; 1528 1529static struct qcom_icc_node qns_pcie = { 1530 .name = "qns_pcie", 1531 .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC, 1532 .channels = 1, 1533 .buswidth = 16, 1534 .num_links = 1, 1535 .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC }, 1536}; 1537 1538static struct qcom_icc_node srvc_even_gemnoc = { 1539 .name = "srvc_even_gemnoc", 1540 .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1, 1541 .channels = 1, 1542 .buswidth = 4, 1543}; 1544 1545static struct qcom_icc_node srvc_odd_gemnoc = { 1546 .name = "srvc_odd_gemnoc", 1547 .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2, 1548 .channels = 1, 1549 .buswidth = 4, 1550}; 1551 1552static struct qcom_icc_node srvc_sys_gemnoc = { 1553 .name = "srvc_sys_gemnoc", 1554 .id = SC8280XP_SLAVE_SERVICE_GEM_NOC, 1555 .channels = 1, 1556 .buswidth = 4, 1557}; 1558 1559static struct qcom_icc_node qhs_lpass_core = { 1560 .name = "qhs_lpass_core", 1561 .id = SC8280XP_SLAVE_LPASS_CORE_CFG, 1562 .channels = 1, 1563 .buswidth = 4, 1564}; 1565 1566static struct qcom_icc_node qhs_lpass_lpi = { 1567 .name = "qhs_lpass_lpi", 1568 .id = SC8280XP_SLAVE_LPASS_LPI_CFG, 1569 .channels = 1, 1570 .buswidth = 4, 1571}; 1572 1573static struct qcom_icc_node qhs_lpass_mpu = { 1574 .name = "qhs_lpass_mpu", 1575 .id = SC8280XP_SLAVE_LPASS_MPU_CFG, 1576 .channels = 1, 1577 .buswidth = 4, 1578}; 1579 1580static struct qcom_icc_node qhs_lpass_top = { 1581 .name = "qhs_lpass_top", 1582 .id = SC8280XP_SLAVE_LPASS_TOP_CFG, 1583 .channels = 1, 1584 .buswidth = 4, 1585}; 1586 1587static struct qcom_icc_node qns_sysnoc = { 1588 .name = "qns_sysnoc", 1589 .id = SC8280XP_SLAVE_LPASS_SNOC, 1590 .channels = 1, 1591 .buswidth = 16, 1592 .num_links = 1, 1593 .links = { SC8280XP_MASTER_LPASS_ANOC }, 1594}; 1595 1596static struct qcom_icc_node srvc_niu_aml_noc = { 1597 .name = "srvc_niu_aml_noc", 1598 .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, 1599 .channels = 1, 1600 .buswidth = 4, 1601}; 1602 1603static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1604 .name = "srvc_niu_lpass_agnoc", 1605 .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC, 1606 .channels = 1, 1607 .buswidth = 4, 1608}; 1609 1610static struct qcom_icc_node ebi = { 1611 .name = "ebi", 1612 .id = SC8280XP_SLAVE_EBI1, 1613 .channels = 8, 1614 .buswidth = 4, 1615}; 1616 1617static struct qcom_icc_node qns_mem_noc_hf = { 1618 .name = "qns_mem_noc_hf", 1619 .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC, 1620 .channels = 2, 1621 .buswidth = 32, 1622 .num_links = 1, 1623 .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC }, 1624}; 1625 1626static struct qcom_icc_node qns_mem_noc_sf = { 1627 .name = "qns_mem_noc_sf", 1628 .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC, 1629 .channels = 2, 1630 .buswidth = 32, 1631 .num_links = 1, 1632 .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC }, 1633}; 1634 1635static struct qcom_icc_node srvc_mnoc = { 1636 .name = "srvc_mnoc", 1637 .id = SC8280XP_SLAVE_SERVICE_MNOC, 1638 .channels = 1, 1639 .buswidth = 4, 1640}; 1641 1642static struct qcom_icc_node qns_nsp_gemnoc = { 1643 .name = "qns_nsp_gemnoc", 1644 .id = SC8280XP_SLAVE_CDSP_MEM_NOC, 1645 .channels = 2, 1646 .buswidth = 32, 1647 .num_links = 1, 1648 .links = { SC8280XP_MASTER_COMPUTE_NOC }, 1649}; 1650 1651static struct qcom_icc_node qxs_nsp_xfr = { 1652 .name = "qxs_nsp_xfr", 1653 .id = SC8280XP_SLAVE_NSP_XFR, 1654 .channels = 1, 1655 .buswidth = 32, 1656}; 1657 1658static struct qcom_icc_node service_nsp_noc = { 1659 .name = "service_nsp_noc", 1660 .id = SC8280XP_SLAVE_SERVICE_NSP_NOC, 1661 .channels = 1, 1662 .buswidth = 4, 1663}; 1664 1665static struct qcom_icc_node qns_nspb_gemnoc = { 1666 .name = "qns_nspb_gemnoc", 1667 .id = SC8280XP_SLAVE_CDSPB_MEM_NOC, 1668 .channels = 2, 1669 .buswidth = 32, 1670 .num_links = 1, 1671 .links = { SC8280XP_MASTER_COMPUTE_NOC_1 }, 1672}; 1673 1674static struct qcom_icc_node qxs_nspb_xfr = { 1675 .name = "qxs_nspb_xfr", 1676 .id = SC8280XP_SLAVE_NSPB_XFR, 1677 .channels = 1, 1678 .buswidth = 32, 1679}; 1680 1681static struct qcom_icc_node service_nspb_noc = { 1682 .name = "service_nspb_noc", 1683 .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC, 1684 .channels = 1, 1685 .buswidth = 4, 1686}; 1687 1688static struct qcom_icc_node qns_gemnoc_gc = { 1689 .name = "qns_gemnoc_gc", 1690 .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC, 1691 .channels = 1, 1692 .buswidth = 8, 1693 .num_links = 1, 1694 .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC }, 1695}; 1696 1697static struct qcom_icc_node qns_gemnoc_sf = { 1698 .name = "qns_gemnoc_sf", 1699 .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF, 1700 .channels = 1, 1701 .buswidth = 16, 1702 .num_links = 1, 1703 .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC }, 1704}; 1705 1706static struct qcom_icc_node srvc_snoc = { 1707 .name = "srvc_snoc", 1708 .id = SC8280XP_SLAVE_SERVICE_SNOC, 1709 .channels = 1, 1710 .buswidth = 4, 1711}; 1712 1713static struct qcom_icc_bcm bcm_acv = { 1714 .name = "ACV", 1715 .enable_mask = BIT(3), 1716 .num_nodes = 1, 1717 .nodes = { &ebi }, 1718}; 1719 1720static struct qcom_icc_bcm bcm_ce0 = { 1721 .name = "CE0", 1722 .num_nodes = 1, 1723 .nodes = { &qxm_crypto }, 1724}; 1725 1726static struct qcom_icc_bcm bcm_cn0 = { 1727 .name = "CN0", 1728 .keepalive = true, 1729 .num_nodes = 9, 1730 .nodes = { &qnm_gemnoc_cnoc, 1731 &qnm_gemnoc_pcie, 1732 &xs_pcie_0, 1733 &xs_pcie_1, 1734 &xs_pcie_2a, 1735 &xs_pcie_2b, 1736 &xs_pcie_3a, 1737 &xs_pcie_3b, 1738 &xs_pcie_4 1739 }, 1740}; 1741 1742static struct qcom_icc_bcm bcm_cn1 = { 1743 .name = "CN1", 1744 .num_nodes = 67, 1745 .nodes = { &qhs_ahb2phy0, 1746 &qhs_ahb2phy1, 1747 &qhs_ahb2phy2, 1748 &qhs_aoss, 1749 &qhs_apss, 1750 &qhs_camera_cfg, 1751 &qhs_clk_ctl, 1752 &qhs_compute0_cfg, 1753 &qhs_compute1_cfg, 1754 &qhs_cpr_cx, 1755 &qhs_cpr_mmcx, 1756 &qhs_cpr_mx, 1757 &qhs_cpr_nspcx, 1758 &qhs_crypto0_cfg, 1759 &qhs_cx_rdpm, 1760 &qhs_dcc_cfg, 1761 &qhs_display0_cfg, 1762 &qhs_display1_cfg, 1763 &qhs_emac0_cfg, 1764 &qhs_emac1_cfg, 1765 &qhs_gpuss_cfg, 1766 &qhs_hwkm, 1767 &qhs_imem_cfg, 1768 &qhs_ipa, 1769 &qhs_ipc_router, 1770 &qhs_lpass_cfg, 1771 &qhs_mx_rdpm, 1772 &qhs_mxc_rdpm, 1773 &qhs_pcie0_cfg, 1774 &qhs_pcie1_cfg, 1775 &qhs_pcie2a_cfg, 1776 &qhs_pcie2b_cfg, 1777 &qhs_pcie3a_cfg, 1778 &qhs_pcie3b_cfg, 1779 &qhs_pcie4_cfg, 1780 &qhs_pcie_rsc_cfg, 1781 &qhs_pdm, 1782 &qhs_pimem_cfg, 1783 &qhs_pka_wrapper_cfg, 1784 &qhs_pmu_wrapper_cfg, 1785 &qhs_qdss_cfg, 1786 &qhs_sdc2, 1787 &qhs_sdc4, 1788 &qhs_security, 1789 &qhs_smmuv3_cfg, 1790 &qhs_smss_cfg, 1791 &qhs_spss_cfg, 1792 &qhs_tcsr, 1793 &qhs_tlmm, 1794 &qhs_ufs_card_cfg, 1795 &qhs_ufs_mem_cfg, 1796 &qhs_usb3_0, 1797 &qhs_usb3_1, 1798 &qhs_usb3_mp, 1799 &qhs_usb4_host_0, 1800 &qhs_usb4_host_1, 1801 &qhs_venus_cfg, 1802 &qhs_vsense_ctrl_cfg, 1803 &qhs_vsense_ctrl_r_cfg, 1804 &qns_a1_noc_cfg, 1805 &qns_a2_noc_cfg, 1806 &qns_anoc_pcie_bridge_cfg, 1807 &qns_ddrss_cfg, 1808 &qns_mnoc_cfg, 1809 &qns_snoc_cfg, 1810 &qns_snoc_sf_bridge_cfg, 1811 &srvc_cnoc 1812 }, 1813}; 1814 1815static struct qcom_icc_bcm bcm_cn2 = { 1816 .name = "CN2", 1817 .num_nodes = 4, 1818 .nodes = { &qhs_qspi, 1819 &qhs_qup0, 1820 &qhs_qup1, 1821 &qhs_qup2 1822 }, 1823}; 1824 1825static struct qcom_icc_bcm bcm_cn3 = { 1826 .name = "CN3", 1827 .num_nodes = 3, 1828 .nodes = { &qxs_imem, 1829 &xs_smss, 1830 &xs_sys_tcu_cfg 1831 }, 1832}; 1833 1834static struct qcom_icc_bcm bcm_mc0 = { 1835 .name = "MC0", 1836 .keepalive = true, 1837 .num_nodes = 1, 1838 .nodes = { &ebi }, 1839}; 1840 1841static struct qcom_icc_bcm bcm_mm0 = { 1842 .name = "MM0", 1843 .keepalive = true, 1844 .num_nodes = 5, 1845 .nodes = { &qnm_camnoc_hf, 1846 &qnm_mdp0_0, 1847 &qnm_mdp0_1, 1848 &qnm_mdp1_0, 1849 &qns_mem_noc_hf 1850 }, 1851}; 1852 1853static struct qcom_icc_bcm bcm_mm1 = { 1854 .name = "MM1", 1855 .num_nodes = 8, 1856 .nodes = { &qnm_rot_0, 1857 &qnm_rot_1, 1858 &qnm_video0, 1859 &qnm_video1, 1860 &qnm_video_cvp, 1861 &qxm_camnoc_icp, 1862 &qxm_camnoc_sf, 1863 &qns_mem_noc_sf 1864 }, 1865}; 1866 1867static struct qcom_icc_bcm bcm_nsa0 = { 1868 .name = "NSA0", 1869 .num_nodes = 2, 1870 .nodes = { &qns_nsp_gemnoc, 1871 &qxs_nsp_xfr 1872 }, 1873}; 1874 1875static struct qcom_icc_bcm bcm_nsa1 = { 1876 .name = "NSA1", 1877 .num_nodes = 1, 1878 .nodes = { &qxm_nsp }, 1879}; 1880 1881static struct qcom_icc_bcm bcm_nsb0 = { 1882 .name = "NSB0", 1883 .num_nodes = 2, 1884 .nodes = { &qns_nspb_gemnoc, 1885 &qxs_nspb_xfr 1886 }, 1887}; 1888 1889static struct qcom_icc_bcm bcm_nsb1 = { 1890 .name = "NSB1", 1891 .num_nodes = 1, 1892 .nodes = { &qxm_nspb }, 1893}; 1894 1895static struct qcom_icc_bcm bcm_pci0 = { 1896 .name = "PCI0", 1897 .num_nodes = 1, 1898 .nodes = { &qns_pcie_gem_noc }, 1899}; 1900 1901static struct qcom_icc_bcm bcm_qup0 = { 1902 .name = "QUP0", 1903 .vote_scale = 1, 1904 .num_nodes = 1, 1905 .nodes = { &qup0_core_slave }, 1906}; 1907 1908static struct qcom_icc_bcm bcm_qup1 = { 1909 .name = "QUP1", 1910 .vote_scale = 1, 1911 .num_nodes = 1, 1912 .nodes = { &qup1_core_slave }, 1913}; 1914 1915static struct qcom_icc_bcm bcm_qup2 = { 1916 .name = "QUP2", 1917 .vote_scale = 1, 1918 .num_nodes = 1, 1919 .nodes = { &qup2_core_slave }, 1920}; 1921 1922static struct qcom_icc_bcm bcm_sh0 = { 1923 .name = "SH0", 1924 .keepalive = true, 1925 .num_nodes = 1, 1926 .nodes = { &qns_llcc }, 1927}; 1928 1929static struct qcom_icc_bcm bcm_sh2 = { 1930 .name = "SH2", 1931 .num_nodes = 1, 1932 .nodes = { &chm_apps }, 1933}; 1934 1935static struct qcom_icc_bcm bcm_sn0 = { 1936 .name = "SN0", 1937 .keepalive = true, 1938 .num_nodes = 1, 1939 .nodes = { &qns_gemnoc_sf }, 1940}; 1941 1942static struct qcom_icc_bcm bcm_sn1 = { 1943 .name = "SN1", 1944 .num_nodes = 1, 1945 .nodes = { &qns_gemnoc_gc }, 1946}; 1947 1948static struct qcom_icc_bcm bcm_sn2 = { 1949 .name = "SN2", 1950 .num_nodes = 1, 1951 .nodes = { &qxs_pimem }, 1952}; 1953 1954static struct qcom_icc_bcm bcm_sn3 = { 1955 .name = "SN3", 1956 .num_nodes = 2, 1957 .nodes = { &qns_a1noc_snoc, 1958 &qnm_aggre1_noc 1959 }, 1960}; 1961 1962static struct qcom_icc_bcm bcm_sn4 = { 1963 .name = "SN4", 1964 .num_nodes = 2, 1965 .nodes = { &qns_a2noc_snoc, 1966 &qnm_aggre2_noc 1967 }, 1968}; 1969 1970static struct qcom_icc_bcm bcm_sn5 = { 1971 .name = "SN5", 1972 .num_nodes = 2, 1973 .nodes = { &qns_aggre_usb_snoc, 1974 &qnm_aggre_usb_noc 1975 }, 1976}; 1977 1978static struct qcom_icc_bcm bcm_sn9 = { 1979 .name = "SN9", 1980 .num_nodes = 2, 1981 .nodes = { &qns_sysnoc, 1982 &qnm_lpass_noc 1983 }, 1984}; 1985 1986static struct qcom_icc_bcm bcm_sn10 = { 1987 .name = "SN10", 1988 .num_nodes = 1, 1989 .nodes = { &xs_qdss_stm }, 1990}; 1991 1992static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1993 &bcm_sn3, 1994 &bcm_sn5, 1995}; 1996 1997static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1998 [MASTER_QSPI_0] = &qhm_qspi, 1999 [MASTER_QUP_1] = &qhm_qup1, 2000 [MASTER_QUP_2] = &qhm_qup2, 2001 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 2002 [MASTER_IPA] = &qxm_ipa, 2003 [MASTER_EMAC_1] = &xm_emac_1, 2004 [MASTER_SDCC_4] = &xm_sdc4, 2005 [MASTER_UFS_MEM] = &xm_ufs_mem, 2006 [MASTER_USB3_0] = &xm_usb3_0, 2007 [MASTER_USB3_1] = &xm_usb3_1, 2008 [MASTER_USB3_MP] = &xm_usb3_mp, 2009 [MASTER_USB4_0] = &xm_usb4_host0, 2010 [MASTER_USB4_1] = &xm_usb4_host1, 2011 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 2012 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, 2013 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 2014}; 2015 2016static const struct qcom_icc_desc sc8280xp_aggre1_noc = { 2017 .nodes = aggre1_noc_nodes, 2018 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2019 .bcms = aggre1_noc_bcms, 2020 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2021}; 2022 2023static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 2024 &bcm_ce0, 2025 &bcm_pci0, 2026 &bcm_sn4, 2027}; 2028 2029static struct qcom_icc_node * const aggre2_noc_nodes[] = { 2030 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 2031 [MASTER_QUP_0] = &qhm_qup0, 2032 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 2033 [MASTER_CRYPTO] = &qxm_crypto, 2034 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, 2035 [MASTER_SP] = &qxm_sp, 2036 [MASTER_EMAC] = &xm_emac_0, 2037 [MASTER_PCIE_0] = &xm_pcie3_0, 2038 [MASTER_PCIE_1] = &xm_pcie3_1, 2039 [MASTER_PCIE_2A] = &xm_pcie3_2a, 2040 [MASTER_PCIE_2B] = &xm_pcie3_2b, 2041 [MASTER_PCIE_3A] = &xm_pcie3_3a, 2042 [MASTER_PCIE_3B] = &xm_pcie3_3b, 2043 [MASTER_PCIE_4] = &xm_pcie3_4, 2044 [MASTER_QDSS_ETR] = &xm_qdss_etr, 2045 [MASTER_SDCC_2] = &xm_sdc2, 2046 [MASTER_UFS_CARD] = &xm_ufs_card, 2047 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2048 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc, 2049 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 2050}; 2051 2052static const struct qcom_icc_desc sc8280xp_aggre2_noc = { 2053 .nodes = aggre2_noc_nodes, 2054 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2055 .bcms = aggre2_noc_bcms, 2056 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2057}; 2058 2059static struct qcom_icc_bcm * const clk_virt_bcms[] = { 2060 &bcm_qup0, 2061 &bcm_qup1, 2062 &bcm_qup2, 2063}; 2064 2065static struct qcom_icc_node * const clk_virt_nodes[] = { 2066 [MASTER_QUP_CORE_0] = &qup0_core_master, 2067 [MASTER_QUP_CORE_1] = &qup1_core_master, 2068 [MASTER_QUP_CORE_2] = &qup2_core_master, 2069 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2070 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2071 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2072}; 2073 2074static const struct qcom_icc_desc sc8280xp_clk_virt = { 2075 .nodes = clk_virt_nodes, 2076 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2077 .bcms = clk_virt_bcms, 2078 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2079}; 2080 2081static struct qcom_icc_bcm * const config_noc_bcms[] = { 2082 &bcm_cn0, 2083 &bcm_cn1, 2084 &bcm_cn2, 2085 &bcm_cn3, 2086 &bcm_sn2, 2087 &bcm_sn10, 2088}; 2089 2090static struct qcom_icc_node * const config_noc_nodes[] = { 2091 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 2092 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 2093 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2094 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2095 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2096 [SLAVE_AOSS] = &qhs_aoss, 2097 [SLAVE_APPSS] = &qhs_apss, 2098 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2099 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2100 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 2101 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, 2102 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 2103 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 2104 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 2105 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 2106 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2107 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 2108 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 2109 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 2110 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, 2111 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 2112 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 2113 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2114 [SLAVE_HWKM] = &qhs_hwkm, 2115 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2116 [SLAVE_IPA_CFG] = &qhs_ipa, 2117 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2118 [SLAVE_LPASS] = &qhs_lpass_cfg, 2119 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 2120 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 2121 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2122 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2123 [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg, 2124 [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg, 2125 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, 2126 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, 2127 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 2128 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 2129 [SLAVE_PDM] = &qhs_pdm, 2130 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 2131 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 2132 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 2133 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2134 [SLAVE_QSPI_0] = &qhs_qspi, 2135 [SLAVE_QUP_0] = &qhs_qup0, 2136 [SLAVE_QUP_1] = &qhs_qup1, 2137 [SLAVE_QUP_2] = &qhs_qup2, 2138 [SLAVE_SDCC_2] = &qhs_sdc2, 2139 [SLAVE_SDCC_4] = &qhs_sdc4, 2140 [SLAVE_SECURITY] = &qhs_security, 2141 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 2142 [SLAVE_SMSS_CFG] = &qhs_smss_cfg, 2143 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 2144 [SLAVE_TCSR] = &qhs_tcsr, 2145 [SLAVE_TLMM] = &qhs_tlmm, 2146 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 2147 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2148 [SLAVE_USB3_0] = &qhs_usb3_0, 2149 [SLAVE_USB3_1] = &qhs_usb3_1, 2150 [SLAVE_USB3_MP] = &qhs_usb3_mp, 2151 [SLAVE_USB4_0] = &qhs_usb4_host_0, 2152 [SLAVE_USB4_1] = &qhs_usb4_host_1, 2153 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2154 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 2155 [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg, 2156 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 2157 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 2158 [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg, 2159 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 2160 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 2161 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 2162 [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg, 2163 [SLAVE_IMEM] = &qxs_imem, 2164 [SLAVE_PIMEM] = &qxs_pimem, 2165 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 2166 [SLAVE_PCIE_0] = &xs_pcie_0, 2167 [SLAVE_PCIE_1] = &xs_pcie_1, 2168 [SLAVE_PCIE_2A] = &xs_pcie_2a, 2169 [SLAVE_PCIE_2B] = &xs_pcie_2b, 2170 [SLAVE_PCIE_3A] = &xs_pcie_3a, 2171 [SLAVE_PCIE_3B] = &xs_pcie_3b, 2172 [SLAVE_PCIE_4] = &xs_pcie_4, 2173 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2174 [SLAVE_SMSS] = &xs_smss, 2175 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2176}; 2177 2178static const struct qcom_icc_desc sc8280xp_config_noc = { 2179 .nodes = config_noc_nodes, 2180 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2181 .bcms = config_noc_bcms, 2182 .num_bcms = ARRAY_SIZE(config_noc_bcms), 2183}; 2184 2185static struct qcom_icc_bcm * const dc_noc_bcms[] = { 2186}; 2187 2188static struct qcom_icc_node * const dc_noc_nodes[] = { 2189 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 2190 [SLAVE_LLCC_CFG] = &qhs_llcc, 2191 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2192}; 2193 2194static const struct qcom_icc_desc sc8280xp_dc_noc = { 2195 .nodes = dc_noc_nodes, 2196 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2197 .bcms = dc_noc_bcms, 2198 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 2199}; 2200 2201static struct qcom_icc_bcm * const gem_noc_bcms[] = { 2202 &bcm_sh0, 2203 &bcm_sh2, 2204}; 2205 2206static struct qcom_icc_node * const gem_noc_nodes[] = { 2207 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2208 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 2209 [MASTER_SYS_TCU] = &alm_sys_tcu, 2210 [MASTER_APPSS_PROC] = &chm_apps, 2211 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 2212 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, 2213 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 2214 [MASTER_GFX3D] = &qnm_gpu, 2215 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2216 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2217 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2218 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 2219 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2220 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2221 [SLAVE_LLCC] = &qns_llcc, 2222 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 2223 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 2224 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 2225 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 2226}; 2227 2228static const struct qcom_icc_desc sc8280xp_gem_noc = { 2229 .nodes = gem_noc_nodes, 2230 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2231 .bcms = gem_noc_bcms, 2232 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2233}; 2234 2235static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 2236 &bcm_sn9, 2237}; 2238 2239static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2240 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 2241 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 2242 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 2243 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 2244 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 2245 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 2246 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 2247 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 2248 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2249}; 2250 2251static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { 2252 .nodes = lpass_ag_noc_nodes, 2253 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2254 .bcms = lpass_ag_noc_bcms, 2255 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2256}; 2257 2258static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2259 &bcm_acv, 2260 &bcm_mc0, 2261}; 2262 2263static struct qcom_icc_node * const mc_virt_nodes[] = { 2264 [MASTER_LLCC] = &llcc_mc, 2265 [SLAVE_EBI1] = &ebi, 2266}; 2267 2268static const struct qcom_icc_desc sc8280xp_mc_virt = { 2269 .nodes = mc_virt_nodes, 2270 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2271 .bcms = mc_virt_bcms, 2272 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2273}; 2274 2275static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2276 &bcm_mm0, 2277 &bcm_mm1, 2278}; 2279 2280static struct qcom_icc_node * const mmss_noc_nodes[] = { 2281 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2282 [MASTER_MDP0] = &qnm_mdp0_0, 2283 [MASTER_MDP1] = &qnm_mdp0_1, 2284 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, 2285 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, 2286 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 2287 [MASTER_ROTATOR] = &qnm_rot_0, 2288 [MASTER_ROTATOR_1] = &qnm_rot_1, 2289 [MASTER_VIDEO_P0] = &qnm_video0, 2290 [MASTER_VIDEO_P1] = &qnm_video1, 2291 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 2292 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 2293 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 2294 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2295 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2296 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2297}; 2298 2299static const struct qcom_icc_desc sc8280xp_mmss_noc = { 2300 .nodes = mmss_noc_nodes, 2301 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2302 .bcms = mmss_noc_bcms, 2303 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2304}; 2305 2306static struct qcom_icc_bcm * const nspa_noc_bcms[] = { 2307 &bcm_nsa0, 2308 &bcm_nsa1, 2309}; 2310 2311static struct qcom_icc_node * const nspa_noc_nodes[] = { 2312 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 2313 [MASTER_CDSP_PROC] = &qxm_nsp, 2314 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2315 [SLAVE_NSP_XFR] = &qxs_nsp_xfr, 2316 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2317}; 2318 2319static const struct qcom_icc_desc sc8280xp_nspa_noc = { 2320 .nodes = nspa_noc_nodes, 2321 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2322 .bcms = nspa_noc_bcms, 2323 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 2324}; 2325 2326static struct qcom_icc_bcm * const nspb_noc_bcms[] = { 2327 &bcm_nsb0, 2328 &bcm_nsb1, 2329}; 2330 2331static struct qcom_icc_node * const nspb_noc_nodes[] = { 2332 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2333 [MASTER_CDSP_PROC_B] = &qxm_nspb, 2334 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, 2335 [SLAVE_NSPB_XFR] = &qxs_nspb_xfr, 2336 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, 2337}; 2338 2339static const struct qcom_icc_desc sc8280xp_nspb_noc = { 2340 .nodes = nspb_noc_nodes, 2341 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2342 .bcms = nspb_noc_bcms, 2343 .num_bcms = ARRAY_SIZE(nspb_noc_bcms), 2344}; 2345 2346static struct qcom_icc_bcm * const system_noc_main_bcms[] = { 2347 &bcm_sn0, 2348 &bcm_sn1, 2349 &bcm_sn3, 2350 &bcm_sn4, 2351 &bcm_sn5, 2352 &bcm_sn9, 2353}; 2354 2355static struct qcom_icc_node * const system_noc_main_nodes[] = { 2356 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2357 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2358 [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc, 2359 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 2360 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 2361 [MASTER_PIMEM] = &qxm_pimem, 2362 [MASTER_GIC] = &xm_gic, 2363 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 2364 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2365 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2366}; 2367 2368static const struct qcom_icc_desc sc8280xp_system_noc_main = { 2369 .nodes = system_noc_main_nodes, 2370 .num_nodes = ARRAY_SIZE(system_noc_main_nodes), 2371 .bcms = system_noc_main_bcms, 2372 .num_bcms = ARRAY_SIZE(system_noc_main_bcms), 2373}; 2374 2375static const struct of_device_id qnoc_of_match[] = { 2376 { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, }, 2377 { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, }, 2378 { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, }, 2379 { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, }, 2380 { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, }, 2381 { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, }, 2382 { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, }, 2383 { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, }, 2384 { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, }, 2385 { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, }, 2386 { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, }, 2387 { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, }, 2388 { } 2389}; 2390MODULE_DEVICE_TABLE(of, qnoc_of_match); 2391 2392static struct platform_driver qnoc_driver = { 2393 .probe = qcom_icc_rpmh_probe, 2394 .remove_new = qcom_icc_rpmh_remove, 2395 .driver = { 2396 .name = "qnoc-sc8280xp", 2397 .of_match_table = qnoc_of_match, 2398 .sync_state = icc_sync_state, 2399 }, 2400}; 2401 2402static int __init qnoc_driver_init(void) 2403{ 2404 return platform_driver_register(&qnoc_driver); 2405} 2406core_initcall(qnoc_driver_init); 2407 2408static void __exit qnoc_driver_exit(void) 2409{ 2410 platform_driver_unregister(&qnoc_driver); 2411} 2412module_exit(qnoc_driver_exit); 2413 2414MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver"); 2415MODULE_LICENSE("GPL"); 2416