1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver 4 * 5 * Copyright (c) 2021, Linaro Ltd. 6 * 7 */ 8 9#include <dt-bindings/interconnect/qcom,qcm2290.h> 10#include <linux/device.h> 11#include <linux/interconnect-provider.h> 12#include <linux/io.h> 13#include <linux/mod_devicetable.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/regmap.h> 17#include <linux/slab.h> 18 19#include "icc-rpm.h" 20 21enum { 22 QCM2290_MASTER_APPSS_PROC = 1, 23 QCM2290_MASTER_SNOC_BIMC_RT, 24 QCM2290_MASTER_SNOC_BIMC_NRT, 25 QCM2290_MASTER_SNOC_BIMC, 26 QCM2290_MASTER_TCU_0, 27 QCM2290_MASTER_GFX3D, 28 QCM2290_MASTER_SNOC_CNOC, 29 QCM2290_MASTER_QDSS_DAP, 30 QCM2290_MASTER_CRYPTO_CORE0, 31 QCM2290_MASTER_SNOC_CFG, 32 QCM2290_MASTER_TIC, 33 QCM2290_MASTER_ANOC_SNOC, 34 QCM2290_MASTER_BIMC_SNOC, 35 QCM2290_MASTER_PIMEM, 36 QCM2290_MASTER_QDSS_BAM, 37 QCM2290_MASTER_QUP_0, 38 QCM2290_MASTER_IPA, 39 QCM2290_MASTER_QDSS_ETR, 40 QCM2290_MASTER_SDCC_1, 41 QCM2290_MASTER_SDCC_2, 42 QCM2290_MASTER_QPIC, 43 QCM2290_MASTER_USB3_0, 44 QCM2290_MASTER_QUP_CORE_0, 45 QCM2290_MASTER_CAMNOC_SF, 46 QCM2290_MASTER_VIDEO_P0, 47 QCM2290_MASTER_VIDEO_PROC, 48 QCM2290_MASTER_CAMNOC_HF, 49 QCM2290_MASTER_MDP0, 50 51 QCM2290_SLAVE_EBI1, 52 QCM2290_SLAVE_BIMC_SNOC, 53 QCM2290_SLAVE_BIMC_CFG, 54 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 55 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 56 QCM2290_SLAVE_CAMERA_CFG, 57 QCM2290_SLAVE_CLK_CTL, 58 QCM2290_SLAVE_CRYPTO_0_CFG, 59 QCM2290_SLAVE_DISPLAY_CFG, 60 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 61 QCM2290_SLAVE_GPU_CFG, 62 QCM2290_SLAVE_HWKM, 63 QCM2290_SLAVE_IMEM_CFG, 64 QCM2290_SLAVE_IPA_CFG, 65 QCM2290_SLAVE_LPASS, 66 QCM2290_SLAVE_MESSAGE_RAM, 67 QCM2290_SLAVE_PDM, 68 QCM2290_SLAVE_PIMEM_CFG, 69 QCM2290_SLAVE_PKA_WRAPPER, 70 QCM2290_SLAVE_PMIC_ARB, 71 QCM2290_SLAVE_PRNG, 72 QCM2290_SLAVE_QDSS_CFG, 73 QCM2290_SLAVE_QM_CFG, 74 QCM2290_SLAVE_QM_MPU_CFG, 75 QCM2290_SLAVE_QPIC, 76 QCM2290_SLAVE_QUP_0, 77 QCM2290_SLAVE_SDCC_1, 78 QCM2290_SLAVE_SDCC_2, 79 QCM2290_SLAVE_SNOC_CFG, 80 QCM2290_SLAVE_TCSR, 81 QCM2290_SLAVE_USB3, 82 QCM2290_SLAVE_VENUS_CFG, 83 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 84 QCM2290_SLAVE_VSENSE_CTRL_CFG, 85 QCM2290_SLAVE_SERVICE_CNOC, 86 QCM2290_SLAVE_APPSS, 87 QCM2290_SLAVE_SNOC_CNOC, 88 QCM2290_SLAVE_IMEM, 89 QCM2290_SLAVE_PIMEM, 90 QCM2290_SLAVE_SNOC_BIMC, 91 QCM2290_SLAVE_SERVICE_SNOC, 92 QCM2290_SLAVE_QDSS_STM, 93 QCM2290_SLAVE_TCU, 94 QCM2290_SLAVE_ANOC_SNOC, 95 QCM2290_SLAVE_QUP_CORE_0, 96 QCM2290_SLAVE_SNOC_BIMC_NRT, 97 QCM2290_SLAVE_SNOC_BIMC_RT, 98}; 99 100/* Master nodes */ 101static const u16 mas_appss_proc_links[] = { 102 QCM2290_SLAVE_EBI1, 103 QCM2290_SLAVE_BIMC_SNOC, 104}; 105 106static struct qcom_icc_node mas_appss_proc = { 107 .id = QCM2290_MASTER_APPSS_PROC, 108 .name = "mas_apps_proc", 109 .buswidth = 16, 110 .qos.ap_owned = true, 111 .qos.qos_port = 0, 112 .qos.qos_mode = NOC_QOS_MODE_FIXED, 113 .qos.prio_level = 0, 114 .qos.areq_prio = 0, 115 .bus_clk_desc = &mem_1_clk, 116 .ab_coeff = 159, 117 .ib_coeff = 96, 118 .mas_rpm_id = 0, 119 .slv_rpm_id = -1, 120 .num_links = ARRAY_SIZE(mas_appss_proc_links), 121 .links = mas_appss_proc_links, 122}; 123 124static const u16 mas_snoc_bimc_rt_links[] = { 125 QCM2290_SLAVE_EBI1, 126}; 127 128static struct qcom_icc_node mas_snoc_bimc_rt = { 129 .id = QCM2290_MASTER_SNOC_BIMC_RT, 130 .name = "mas_snoc_bimc_rt", 131 .buswidth = 16, 132 .qos.ap_owned = true, 133 .qos.qos_port = 2, 134 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 135 .mas_rpm_id = 163, 136 .slv_rpm_id = -1, 137 .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links), 138 .links = mas_snoc_bimc_rt_links, 139}; 140 141static const u16 mas_snoc_bimc_nrt_links[] = { 142 QCM2290_SLAVE_EBI1, 143}; 144 145static struct qcom_icc_node mas_snoc_bimc_nrt = { 146 .id = QCM2290_MASTER_SNOC_BIMC_NRT, 147 .name = "mas_snoc_bimc_nrt", 148 .buswidth = 16, 149 .qos.ap_owned = true, 150 .qos.qos_port = 3, 151 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 152 .mas_rpm_id = 164, 153 .slv_rpm_id = -1, 154 .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links), 155 .links = mas_snoc_bimc_nrt_links, 156}; 157 158static const u16 mas_snoc_bimc_links[] = { 159 QCM2290_SLAVE_EBI1, 160}; 161 162static struct qcom_icc_node mas_snoc_bimc = { 163 .id = QCM2290_MASTER_SNOC_BIMC, 164 .name = "mas_snoc_bimc", 165 .buswidth = 16, 166 .qos.ap_owned = true, 167 .qos.qos_port = 2, 168 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 169 .mas_rpm_id = 164, 170 .slv_rpm_id = -1, 171 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 172 .links = mas_snoc_bimc_links, 173}; 174 175static const u16 mas_tcu_0_links[] = { 176 QCM2290_SLAVE_EBI1, 177 QCM2290_SLAVE_BIMC_SNOC, 178}; 179 180static struct qcom_icc_node mas_tcu_0 = { 181 .id = QCM2290_MASTER_TCU_0, 182 .name = "mas_tcu_0", 183 .buswidth = 8, 184 .qos.ap_owned = true, 185 .qos.qos_port = 4, 186 .qos.qos_mode = NOC_QOS_MODE_FIXED, 187 .qos.prio_level = 6, 188 .qos.areq_prio = 6, 189 .mas_rpm_id = 102, 190 .slv_rpm_id = -1, 191 .num_links = ARRAY_SIZE(mas_tcu_0_links), 192 .links = mas_tcu_0_links, 193}; 194 195static const u16 mas_snoc_cnoc_links[] = { 196 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 197 QCM2290_SLAVE_SDCC_2, 198 QCM2290_SLAVE_SDCC_1, 199 QCM2290_SLAVE_QM_CFG, 200 QCM2290_SLAVE_BIMC_CFG, 201 QCM2290_SLAVE_USB3, 202 QCM2290_SLAVE_QM_MPU_CFG, 203 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 204 QCM2290_SLAVE_QDSS_CFG, 205 QCM2290_SLAVE_PDM, 206 QCM2290_SLAVE_IPA_CFG, 207 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 208 QCM2290_SLAVE_TCSR, 209 QCM2290_SLAVE_MESSAGE_RAM, 210 QCM2290_SLAVE_PMIC_ARB, 211 QCM2290_SLAVE_LPASS, 212 QCM2290_SLAVE_DISPLAY_CFG, 213 QCM2290_SLAVE_VENUS_CFG, 214 QCM2290_SLAVE_GPU_CFG, 215 QCM2290_SLAVE_IMEM_CFG, 216 QCM2290_SLAVE_SNOC_CFG, 217 QCM2290_SLAVE_SERVICE_CNOC, 218 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 219 QCM2290_SLAVE_PKA_WRAPPER, 220 QCM2290_SLAVE_HWKM, 221 QCM2290_SLAVE_PRNG, 222 QCM2290_SLAVE_VSENSE_CTRL_CFG, 223 QCM2290_SLAVE_CRYPTO_0_CFG, 224 QCM2290_SLAVE_PIMEM_CFG, 225 QCM2290_SLAVE_QUP_0, 226 QCM2290_SLAVE_CAMERA_CFG, 227 QCM2290_SLAVE_CLK_CTL, 228 QCM2290_SLAVE_QPIC, 229}; 230 231static struct qcom_icc_node mas_snoc_cnoc = { 232 .id = QCM2290_MASTER_SNOC_CNOC, 233 .name = "mas_snoc_cnoc", 234 .buswidth = 8, 235 .qos.ap_owned = true, 236 .qos.qos_mode = NOC_QOS_MODE_INVALID, 237 .mas_rpm_id = 52, 238 .slv_rpm_id = -1, 239 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 240 .links = mas_snoc_cnoc_links, 241}; 242 243static const u16 mas_qdss_dap_links[] = { 244 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 245 QCM2290_SLAVE_SDCC_2, 246 QCM2290_SLAVE_SDCC_1, 247 QCM2290_SLAVE_QM_CFG, 248 QCM2290_SLAVE_BIMC_CFG, 249 QCM2290_SLAVE_USB3, 250 QCM2290_SLAVE_QM_MPU_CFG, 251 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 252 QCM2290_SLAVE_QDSS_CFG, 253 QCM2290_SLAVE_PDM, 254 QCM2290_SLAVE_IPA_CFG, 255 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 256 QCM2290_SLAVE_TCSR, 257 QCM2290_SLAVE_MESSAGE_RAM, 258 QCM2290_SLAVE_PMIC_ARB, 259 QCM2290_SLAVE_LPASS, 260 QCM2290_SLAVE_DISPLAY_CFG, 261 QCM2290_SLAVE_VENUS_CFG, 262 QCM2290_SLAVE_GPU_CFG, 263 QCM2290_SLAVE_IMEM_CFG, 264 QCM2290_SLAVE_SNOC_CFG, 265 QCM2290_SLAVE_SERVICE_CNOC, 266 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 267 QCM2290_SLAVE_PKA_WRAPPER, 268 QCM2290_SLAVE_HWKM, 269 QCM2290_SLAVE_PRNG, 270 QCM2290_SLAVE_VSENSE_CTRL_CFG, 271 QCM2290_SLAVE_CRYPTO_0_CFG, 272 QCM2290_SLAVE_PIMEM_CFG, 273 QCM2290_SLAVE_QUP_0, 274 QCM2290_SLAVE_CAMERA_CFG, 275 QCM2290_SLAVE_CLK_CTL, 276 QCM2290_SLAVE_QPIC, 277}; 278 279static struct qcom_icc_node mas_qdss_dap = { 280 .id = QCM2290_MASTER_QDSS_DAP, 281 .name = "mas_qdss_dap", 282 .buswidth = 8, 283 .qos.ap_owned = true, 284 .qos.qos_mode = NOC_QOS_MODE_INVALID, 285 .mas_rpm_id = 49, 286 .slv_rpm_id = -1, 287 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 288 .links = mas_qdss_dap_links, 289}; 290 291static const u16 mas_crypto_core0_links[] = { 292 QCM2290_SLAVE_ANOC_SNOC 293}; 294 295static struct qcom_icc_node mas_crypto_core0 = { 296 .id = QCM2290_MASTER_CRYPTO_CORE0, 297 .name = "mas_crypto_core0", 298 .buswidth = 8, 299 .qos.ap_owned = true, 300 .qos.qos_port = 22, 301 .qos.qos_mode = NOC_QOS_MODE_FIXED, 302 .qos.areq_prio = 2, 303 .mas_rpm_id = 23, 304 .slv_rpm_id = -1, 305 .num_links = ARRAY_SIZE(mas_crypto_core0_links), 306 .links = mas_crypto_core0_links, 307}; 308 309static const u16 mas_qup_core_0_links[] = { 310 QCM2290_SLAVE_QUP_CORE_0, 311}; 312 313static struct qcom_icc_node mas_qup_core_0 = { 314 .id = QCM2290_MASTER_QUP_CORE_0, 315 .name = "mas_qup_core_0", 316 .buswidth = 4, 317 .mas_rpm_id = 170, 318 .slv_rpm_id = -1, 319 .num_links = ARRAY_SIZE(mas_qup_core_0_links), 320 .links = mas_qup_core_0_links, 321}; 322 323static const u16 mas_camnoc_sf_links[] = { 324 QCM2290_SLAVE_SNOC_BIMC_NRT, 325}; 326 327static struct qcom_icc_node mas_camnoc_sf = { 328 .id = QCM2290_MASTER_CAMNOC_SF, 329 .name = "mas_camnoc_sf", 330 .buswidth = 32, 331 .qos.ap_owned = true, 332 .qos.qos_port = 4, 333 .qos.qos_mode = NOC_QOS_MODE_FIXED, 334 .qos.areq_prio = 3, 335 .mas_rpm_id = 172, 336 .slv_rpm_id = -1, 337 .num_links = ARRAY_SIZE(mas_camnoc_sf_links), 338 .links = mas_camnoc_sf_links, 339}; 340 341static const u16 mas_camnoc_hf_links[] = { 342 QCM2290_SLAVE_SNOC_BIMC_RT, 343}; 344 345static struct qcom_icc_node mas_camnoc_hf = { 346 .id = QCM2290_MASTER_CAMNOC_HF, 347 .name = "mas_camnoc_hf", 348 .buswidth = 32, 349 .qos.ap_owned = true, 350 .qos.qos_port = 10, 351 .qos.qos_mode = NOC_QOS_MODE_FIXED, 352 .qos.areq_prio = 3, 353 .qos.urg_fwd_en = true, 354 .mas_rpm_id = 173, 355 .slv_rpm_id = -1, 356 .num_links = ARRAY_SIZE(mas_camnoc_hf_links), 357 .links = mas_camnoc_hf_links, 358}; 359 360static const u16 mas_mdp0_links[] = { 361 QCM2290_SLAVE_SNOC_BIMC_RT, 362}; 363 364static struct qcom_icc_node mas_mdp0 = { 365 .id = QCM2290_MASTER_MDP0, 366 .name = "mas_mdp0", 367 .buswidth = 16, 368 .qos.ap_owned = true, 369 .qos.qos_port = 5, 370 .qos.qos_mode = NOC_QOS_MODE_FIXED, 371 .qos.areq_prio = 3, 372 .qos.urg_fwd_en = true, 373 .mas_rpm_id = 8, 374 .slv_rpm_id = -1, 375 .num_links = ARRAY_SIZE(mas_mdp0_links), 376 .links = mas_mdp0_links, 377}; 378 379static const u16 mas_video_p0_links[] = { 380 QCM2290_SLAVE_SNOC_BIMC_NRT, 381}; 382 383static struct qcom_icc_node mas_video_p0 = { 384 .id = QCM2290_MASTER_VIDEO_P0, 385 .name = "mas_video_p0", 386 .buswidth = 16, 387 .qos.ap_owned = true, 388 .qos.qos_port = 9, 389 .qos.qos_mode = NOC_QOS_MODE_FIXED, 390 .qos.areq_prio = 3, 391 .qos.urg_fwd_en = true, 392 .mas_rpm_id = 9, 393 .slv_rpm_id = -1, 394 .num_links = ARRAY_SIZE(mas_video_p0_links), 395 .links = mas_video_p0_links, 396}; 397 398static const u16 mas_video_proc_links[] = { 399 QCM2290_SLAVE_SNOC_BIMC_NRT, 400}; 401 402static struct qcom_icc_node mas_video_proc = { 403 .id = QCM2290_MASTER_VIDEO_PROC, 404 .name = "mas_video_proc", 405 .buswidth = 8, 406 .qos.ap_owned = true, 407 .qos.qos_port = 13, 408 .qos.qos_mode = NOC_QOS_MODE_FIXED, 409 .qos.areq_prio = 4, 410 .mas_rpm_id = 168, 411 .slv_rpm_id = -1, 412 .num_links = ARRAY_SIZE(mas_video_proc_links), 413 .links = mas_video_proc_links, 414}; 415 416static const u16 mas_snoc_cfg_links[] = { 417 QCM2290_SLAVE_SERVICE_SNOC, 418}; 419 420static struct qcom_icc_node mas_snoc_cfg = { 421 .id = QCM2290_MASTER_SNOC_CFG, 422 .name = "mas_snoc_cfg", 423 .buswidth = 4, 424 .qos.ap_owned = true, 425 .qos.qos_mode = NOC_QOS_MODE_INVALID, 426 .mas_rpm_id = 20, 427 .slv_rpm_id = -1, 428 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 429 .links = mas_snoc_cfg_links, 430}; 431 432static const u16 mas_tic_links[] = { 433 QCM2290_SLAVE_PIMEM, 434 QCM2290_SLAVE_IMEM, 435 QCM2290_SLAVE_APPSS, 436 QCM2290_SLAVE_SNOC_BIMC, 437 QCM2290_SLAVE_SNOC_CNOC, 438 QCM2290_SLAVE_TCU, 439 QCM2290_SLAVE_QDSS_STM, 440}; 441 442static struct qcom_icc_node mas_tic = { 443 .id = QCM2290_MASTER_TIC, 444 .name = "mas_tic", 445 .buswidth = 4, 446 .qos.ap_owned = true, 447 .qos.qos_port = 8, 448 .qos.qos_mode = NOC_QOS_MODE_FIXED, 449 .qos.areq_prio = 2, 450 .mas_rpm_id = 51, 451 .slv_rpm_id = -1, 452 .num_links = ARRAY_SIZE(mas_tic_links), 453 .links = mas_tic_links, 454}; 455 456static const u16 mas_anoc_snoc_links[] = { 457 QCM2290_SLAVE_PIMEM, 458 QCM2290_SLAVE_IMEM, 459 QCM2290_SLAVE_APPSS, 460 QCM2290_SLAVE_SNOC_BIMC, 461 QCM2290_SLAVE_SNOC_CNOC, 462 QCM2290_SLAVE_TCU, 463 QCM2290_SLAVE_QDSS_STM, 464}; 465 466static struct qcom_icc_node mas_anoc_snoc = { 467 .id = QCM2290_MASTER_ANOC_SNOC, 468 .name = "mas_anoc_snoc", 469 .buswidth = 16, 470 .mas_rpm_id = 110, 471 .slv_rpm_id = -1, 472 .num_links = ARRAY_SIZE(mas_anoc_snoc_links), 473 .links = mas_anoc_snoc_links, 474}; 475 476static const u16 mas_bimc_snoc_links[] = { 477 QCM2290_SLAVE_PIMEM, 478 QCM2290_SLAVE_IMEM, 479 QCM2290_SLAVE_APPSS, 480 QCM2290_SLAVE_SNOC_CNOC, 481 QCM2290_SLAVE_TCU, 482 QCM2290_SLAVE_QDSS_STM, 483}; 484 485static struct qcom_icc_node mas_bimc_snoc = { 486 .id = QCM2290_MASTER_BIMC_SNOC, 487 .name = "mas_bimc_snoc", 488 .buswidth = 8, 489 .mas_rpm_id = 21, 490 .slv_rpm_id = -1, 491 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 492 .links = mas_bimc_snoc_links, 493}; 494 495static const u16 mas_pimem_links[] = { 496 QCM2290_SLAVE_IMEM, 497 QCM2290_SLAVE_SNOC_BIMC, 498}; 499 500static struct qcom_icc_node mas_pimem = { 501 .id = QCM2290_MASTER_PIMEM, 502 .name = "mas_pimem", 503 .buswidth = 8, 504 .qos.ap_owned = true, 505 .qos.qos_port = 20, 506 .qos.qos_mode = NOC_QOS_MODE_FIXED, 507 .qos.areq_prio = 2, 508 .mas_rpm_id = 113, 509 .slv_rpm_id = -1, 510 .num_links = ARRAY_SIZE(mas_pimem_links), 511 .links = mas_pimem_links, 512}; 513 514static const u16 mas_qdss_bam_links[] = { 515 QCM2290_SLAVE_ANOC_SNOC, 516}; 517 518static struct qcom_icc_node mas_qdss_bam = { 519 .id = QCM2290_MASTER_QDSS_BAM, 520 .name = "mas_qdss_bam", 521 .buswidth = 4, 522 .qos.ap_owned = true, 523 .qos.qos_port = 2, 524 .qos.qos_mode = NOC_QOS_MODE_FIXED, 525 .qos.areq_prio = 2, 526 .mas_rpm_id = 19, 527 .slv_rpm_id = -1, 528 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 529 .links = mas_qdss_bam_links, 530}; 531 532static const u16 mas_qup_0_links[] = { 533 QCM2290_SLAVE_ANOC_SNOC, 534}; 535 536static struct qcom_icc_node mas_qup_0 = { 537 .id = QCM2290_MASTER_QUP_0, 538 .name = "mas_qup_0", 539 .buswidth = 4, 540 .qos.ap_owned = true, 541 .qos.qos_port = 0, 542 .qos.qos_mode = NOC_QOS_MODE_FIXED, 543 .qos.areq_prio = 2, 544 .mas_rpm_id = 166, 545 .slv_rpm_id = -1, 546 .num_links = ARRAY_SIZE(mas_qup_0_links), 547 .links = mas_qup_0_links, 548}; 549 550static const u16 mas_ipa_links[] = { 551 QCM2290_SLAVE_ANOC_SNOC, 552}; 553 554static struct qcom_icc_node mas_ipa = { 555 .id = QCM2290_MASTER_IPA, 556 .name = "mas_ipa", 557 .buswidth = 8, 558 .qos.ap_owned = true, 559 .qos.qos_port = 3, 560 .qos.qos_mode = NOC_QOS_MODE_FIXED, 561 .qos.areq_prio = 2, 562 .mas_rpm_id = 59, 563 .slv_rpm_id = -1, 564 .num_links = ARRAY_SIZE(mas_ipa_links), 565 .links = mas_ipa_links, 566}; 567 568static const u16 mas_qdss_etr_links[] = { 569 QCM2290_SLAVE_ANOC_SNOC, 570}; 571 572static struct qcom_icc_node mas_qdss_etr = { 573 .id = QCM2290_MASTER_QDSS_ETR, 574 .name = "mas_qdss_etr", 575 .buswidth = 8, 576 .qos.ap_owned = true, 577 .qos.qos_port = 12, 578 .qos.qos_mode = NOC_QOS_MODE_FIXED, 579 .qos.areq_prio = 2, 580 .mas_rpm_id = 31, 581 .slv_rpm_id = -1, 582 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 583 .links = mas_qdss_etr_links, 584}; 585 586static const u16 mas_sdcc_1_links[] = { 587 QCM2290_SLAVE_ANOC_SNOC, 588}; 589 590static struct qcom_icc_node mas_sdcc_1 = { 591 .id = QCM2290_MASTER_SDCC_1, 592 .name = "mas_sdcc_1", 593 .buswidth = 8, 594 .qos.ap_owned = true, 595 .qos.qos_port = 17, 596 .qos.qos_mode = NOC_QOS_MODE_FIXED, 597 .qos.areq_prio = 2, 598 .mas_rpm_id = 33, 599 .slv_rpm_id = -1, 600 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 601 .links = mas_sdcc_1_links, 602}; 603 604static const u16 mas_sdcc_2_links[] = { 605 QCM2290_SLAVE_ANOC_SNOC, 606}; 607 608static struct qcom_icc_node mas_sdcc_2 = { 609 .id = QCM2290_MASTER_SDCC_2, 610 .name = "mas_sdcc_2", 611 .buswidth = 8, 612 .qos.ap_owned = true, 613 .qos.qos_port = 23, 614 .qos.qos_mode = NOC_QOS_MODE_FIXED, 615 .qos.areq_prio = 2, 616 .mas_rpm_id = 35, 617 .slv_rpm_id = -1, 618 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 619 .links = mas_sdcc_2_links, 620}; 621 622static const u16 mas_qpic_links[] = { 623 QCM2290_SLAVE_ANOC_SNOC, 624}; 625 626static struct qcom_icc_node mas_qpic = { 627 .id = QCM2290_MASTER_QPIC, 628 .name = "mas_qpic", 629 .buswidth = 4, 630 .qos.ap_owned = true, 631 .qos.qos_port = 1, 632 .qos.qos_mode = NOC_QOS_MODE_FIXED, 633 .qos.areq_prio = 2, 634 .mas_rpm_id = 58, 635 .slv_rpm_id = -1, 636 .num_links = ARRAY_SIZE(mas_qpic_links), 637 .links = mas_qpic_links, 638}; 639 640static const u16 mas_usb3_0_links[] = { 641 QCM2290_SLAVE_ANOC_SNOC, 642}; 643 644static struct qcom_icc_node mas_usb3_0 = { 645 .id = QCM2290_MASTER_USB3_0, 646 .name = "mas_usb3_0", 647 .buswidth = 8, 648 .qos.ap_owned = true, 649 .qos.qos_port = 24, 650 .qos.qos_mode = NOC_QOS_MODE_FIXED, 651 .qos.areq_prio = 2, 652 .mas_rpm_id = 32, 653 .slv_rpm_id = -1, 654 .num_links = ARRAY_SIZE(mas_usb3_0_links), 655 .links = mas_usb3_0_links, 656}; 657 658static const u16 mas_gfx3d_links[] = { 659 QCM2290_SLAVE_EBI1, 660}; 661 662static struct qcom_icc_node mas_gfx3d = { 663 .id = QCM2290_MASTER_GFX3D, 664 .name = "mas_gfx3d", 665 .buswidth = 32, 666 .qos.ap_owned = true, 667 .qos.qos_port = 1, 668 .qos.qos_mode = NOC_QOS_MODE_FIXED, 669 .qos.prio_level = 0, 670 .qos.areq_prio = 0, 671 .mas_rpm_id = 6, 672 .slv_rpm_id = -1, 673 .num_links = ARRAY_SIZE(mas_gfx3d_links), 674 .links = mas_gfx3d_links, 675}; 676 677/* Slave nodes */ 678static struct qcom_icc_node slv_ebi1 = { 679 .name = "slv_ebi1", 680 .id = QCM2290_SLAVE_EBI1, 681 .buswidth = 4, 682 .channels = 2, 683 .mas_rpm_id = -1, 684 .slv_rpm_id = 0, 685}; 686 687static const u16 slv_bimc_snoc_links[] = { 688 QCM2290_MASTER_BIMC_SNOC, 689}; 690 691static struct qcom_icc_node slv_bimc_snoc = { 692 .name = "slv_bimc_snoc", 693 .id = QCM2290_SLAVE_BIMC_SNOC, 694 .buswidth = 8, 695 .mas_rpm_id = -1, 696 .slv_rpm_id = 2, 697 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 698 .links = slv_bimc_snoc_links, 699}; 700 701static struct qcom_icc_node slv_bimc_cfg = { 702 .name = "slv_bimc_cfg", 703 .id = QCM2290_SLAVE_BIMC_CFG, 704 .buswidth = 4, 705 .qos.ap_owned = true, 706 .qos.qos_mode = NOC_QOS_MODE_INVALID, 707 .mas_rpm_id = -1, 708 .slv_rpm_id = 56, 709}; 710 711static struct qcom_icc_node slv_camera_nrt_throttle_cfg = { 712 .name = "slv_camera_nrt_throttle_cfg", 713 .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 714 .buswidth = 4, 715 .qos.ap_owned = true, 716 .qos.qos_mode = NOC_QOS_MODE_INVALID, 717 .mas_rpm_id = -1, 718 .slv_rpm_id = 271, 719}; 720 721static struct qcom_icc_node slv_camera_rt_throttle_cfg = { 722 .name = "slv_camera_rt_throttle_cfg", 723 .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 724 .buswidth = 4, 725 .qos.ap_owned = true, 726 .qos.qos_mode = NOC_QOS_MODE_INVALID, 727 .mas_rpm_id = -1, 728 .slv_rpm_id = 279, 729}; 730 731static struct qcom_icc_node slv_camera_cfg = { 732 .name = "slv_camera_cfg", 733 .id = QCM2290_SLAVE_CAMERA_CFG, 734 .buswidth = 4, 735 .qos.ap_owned = true, 736 .qos.qos_mode = NOC_QOS_MODE_INVALID, 737 .mas_rpm_id = -1, 738 .slv_rpm_id = 3, 739}; 740 741static struct qcom_icc_node slv_clk_ctl = { 742 .name = "slv_clk_ctl", 743 .id = QCM2290_SLAVE_CLK_CTL, 744 .buswidth = 4, 745 .qos.ap_owned = true, 746 .qos.qos_mode = NOC_QOS_MODE_INVALID, 747 .mas_rpm_id = -1, 748 .slv_rpm_id = 47, 749}; 750 751static struct qcom_icc_node slv_crypto_0_cfg = { 752 .name = "slv_crypto_0_cfg", 753 .id = QCM2290_SLAVE_CRYPTO_0_CFG, 754 .buswidth = 4, 755 .qos.ap_owned = true, 756 .qos.qos_mode = NOC_QOS_MODE_INVALID, 757 .mas_rpm_id = -1, 758 .slv_rpm_id = 52, 759}; 760 761static struct qcom_icc_node slv_display_cfg = { 762 .name = "slv_display_cfg", 763 .id = QCM2290_SLAVE_DISPLAY_CFG, 764 .buswidth = 4, 765 .qos.ap_owned = true, 766 .qos.qos_mode = NOC_QOS_MODE_INVALID, 767 .mas_rpm_id = -1, 768 .slv_rpm_id = 4, 769}; 770 771static struct qcom_icc_node slv_display_throttle_cfg = { 772 .name = "slv_display_throttle_cfg", 773 .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 774 .buswidth = 4, 775 .qos.ap_owned = true, 776 .qos.qos_mode = NOC_QOS_MODE_INVALID, 777 .mas_rpm_id = -1, 778 .slv_rpm_id = 156, 779}; 780 781static struct qcom_icc_node slv_gpu_cfg = { 782 .name = "slv_gpu_cfg", 783 .id = QCM2290_SLAVE_GPU_CFG, 784 .buswidth = 8, 785 .qos.ap_owned = true, 786 .qos.qos_mode = NOC_QOS_MODE_INVALID, 787 .mas_rpm_id = -1, 788 .slv_rpm_id = 275, 789}; 790 791static struct qcom_icc_node slv_hwkm = { 792 .name = "slv_hwkm", 793 .id = QCM2290_SLAVE_HWKM, 794 .buswidth = 4, 795 .qos.ap_owned = true, 796 .qos.qos_mode = NOC_QOS_MODE_INVALID, 797 .mas_rpm_id = -1, 798 .slv_rpm_id = 280, 799}; 800 801static struct qcom_icc_node slv_imem_cfg = { 802 .name = "slv_imem_cfg", 803 .id = QCM2290_SLAVE_IMEM_CFG, 804 .buswidth = 4, 805 .qos.ap_owned = true, 806 .qos.qos_mode = NOC_QOS_MODE_INVALID, 807 .mas_rpm_id = -1, 808 .slv_rpm_id = 54, 809}; 810 811static struct qcom_icc_node slv_ipa_cfg = { 812 .name = "slv_ipa_cfg", 813 .id = QCM2290_SLAVE_IPA_CFG, 814 .buswidth = 4, 815 .qos.ap_owned = true, 816 .qos.qos_mode = NOC_QOS_MODE_INVALID, 817 .mas_rpm_id = -1, 818 .slv_rpm_id = 183, 819}; 820 821static struct qcom_icc_node slv_lpass = { 822 .name = "slv_lpass", 823 .id = QCM2290_SLAVE_LPASS, 824 .buswidth = 4, 825 .qos.ap_owned = true, 826 .qos.qos_mode = NOC_QOS_MODE_INVALID, 827 .mas_rpm_id = -1, 828 .slv_rpm_id = 21, 829}; 830 831static struct qcom_icc_node slv_message_ram = { 832 .name = "slv_message_ram", 833 .id = QCM2290_SLAVE_MESSAGE_RAM, 834 .buswidth = 4, 835 .qos.ap_owned = true, 836 .qos.qos_mode = NOC_QOS_MODE_INVALID, 837 .mas_rpm_id = -1, 838 .slv_rpm_id = 55, 839}; 840 841static struct qcom_icc_node slv_pdm = { 842 .name = "slv_pdm", 843 .id = QCM2290_SLAVE_PDM, 844 .buswidth = 4, 845 .qos.ap_owned = true, 846 .qos.qos_mode = NOC_QOS_MODE_INVALID, 847 .mas_rpm_id = -1, 848 .slv_rpm_id = 41, 849}; 850 851static struct qcom_icc_node slv_pimem_cfg = { 852 .name = "slv_pimem_cfg", 853 .id = QCM2290_SLAVE_PIMEM_CFG, 854 .buswidth = 4, 855 .qos.ap_owned = true, 856 .qos.qos_mode = NOC_QOS_MODE_INVALID, 857 .mas_rpm_id = -1, 858 .slv_rpm_id = 167, 859}; 860 861static struct qcom_icc_node slv_pka_wrapper = { 862 .name = "slv_pka_wrapper", 863 .id = QCM2290_SLAVE_PKA_WRAPPER, 864 .buswidth = 4, 865 .qos.ap_owned = true, 866 .qos.qos_mode = NOC_QOS_MODE_INVALID, 867 .mas_rpm_id = -1, 868 .slv_rpm_id = 281, 869}; 870 871static struct qcom_icc_node slv_pmic_arb = { 872 .name = "slv_pmic_arb", 873 .id = QCM2290_SLAVE_PMIC_ARB, 874 .buswidth = 4, 875 .qos.ap_owned = true, 876 .qos.qos_mode = NOC_QOS_MODE_INVALID, 877 .mas_rpm_id = -1, 878 .slv_rpm_id = 59, 879}; 880 881static struct qcom_icc_node slv_prng = { 882 .name = "slv_prng", 883 .id = QCM2290_SLAVE_PRNG, 884 .buswidth = 4, 885 .qos.ap_owned = true, 886 .qos.qos_mode = NOC_QOS_MODE_INVALID, 887 .mas_rpm_id = -1, 888 .slv_rpm_id = 44, 889}; 890 891static struct qcom_icc_node slv_qdss_cfg = { 892 .name = "slv_qdss_cfg", 893 .id = QCM2290_SLAVE_QDSS_CFG, 894 .buswidth = 4, 895 .qos.ap_owned = true, 896 .qos.qos_mode = NOC_QOS_MODE_INVALID, 897 .mas_rpm_id = -1, 898 .slv_rpm_id = 63, 899}; 900 901static struct qcom_icc_node slv_qm_cfg = { 902 .name = "slv_qm_cfg", 903 .id = QCM2290_SLAVE_QM_CFG, 904 .buswidth = 4, 905 .qos.ap_owned = true, 906 .qos.qos_mode = NOC_QOS_MODE_INVALID, 907 .mas_rpm_id = -1, 908 .slv_rpm_id = 212, 909}; 910 911static struct qcom_icc_node slv_qm_mpu_cfg = { 912 .name = "slv_qm_mpu_cfg", 913 .id = QCM2290_SLAVE_QM_MPU_CFG, 914 .buswidth = 4, 915 .qos.ap_owned = true, 916 .qos.qos_mode = NOC_QOS_MODE_INVALID, 917 .mas_rpm_id = -1, 918 .slv_rpm_id = 231, 919}; 920 921static struct qcom_icc_node slv_qpic = { 922 .name = "slv_qpic", 923 .id = QCM2290_SLAVE_QPIC, 924 .buswidth = 4, 925 .qos.ap_owned = true, 926 .qos.qos_mode = NOC_QOS_MODE_INVALID, 927 .mas_rpm_id = -1, 928 .slv_rpm_id = 80, 929}; 930 931static struct qcom_icc_node slv_qup_0 = { 932 .name = "slv_qup_0", 933 .id = QCM2290_SLAVE_QUP_0, 934 .buswidth = 4, 935 .qos.ap_owned = true, 936 .qos.qos_mode = NOC_QOS_MODE_INVALID, 937 .mas_rpm_id = -1, 938 .slv_rpm_id = 261, 939}; 940 941static struct qcom_icc_node slv_sdcc_1 = { 942 .name = "slv_sdcc_1", 943 .id = QCM2290_SLAVE_SDCC_1, 944 .buswidth = 4, 945 .qos.ap_owned = true, 946 .qos.qos_mode = NOC_QOS_MODE_INVALID, 947 .mas_rpm_id = -1, 948 .slv_rpm_id = 31, 949}; 950 951static struct qcom_icc_node slv_sdcc_2 = { 952 .name = "slv_sdcc_2", 953 .id = QCM2290_SLAVE_SDCC_2, 954 .buswidth = 4, 955 .qos.ap_owned = true, 956 .qos.qos_mode = NOC_QOS_MODE_INVALID, 957 .mas_rpm_id = -1, 958 .slv_rpm_id = 33, 959}; 960 961static const u16 slv_snoc_cfg_links[] = { 962 QCM2290_MASTER_SNOC_CFG, 963}; 964 965static struct qcom_icc_node slv_snoc_cfg = { 966 .name = "slv_snoc_cfg", 967 .id = QCM2290_SLAVE_SNOC_CFG, 968 .buswidth = 4, 969 .qos.ap_owned = true, 970 .qos.qos_mode = NOC_QOS_MODE_INVALID, 971 .mas_rpm_id = -1, 972 .slv_rpm_id = 70, 973 .num_links = ARRAY_SIZE(slv_snoc_cfg_links), 974 .links = slv_snoc_cfg_links, 975}; 976 977static struct qcom_icc_node slv_tcsr = { 978 .name = "slv_tcsr", 979 .id = QCM2290_SLAVE_TCSR, 980 .buswidth = 4, 981 .qos.ap_owned = true, 982 .qos.qos_mode = NOC_QOS_MODE_INVALID, 983 .mas_rpm_id = -1, 984 .slv_rpm_id = 50, 985}; 986 987static struct qcom_icc_node slv_usb3 = { 988 .name = "slv_usb3", 989 .id = QCM2290_SLAVE_USB3, 990 .buswidth = 4, 991 .qos.ap_owned = true, 992 .qos.qos_mode = NOC_QOS_MODE_INVALID, 993 .mas_rpm_id = -1, 994 .slv_rpm_id = 22, 995}; 996 997static struct qcom_icc_node slv_venus_cfg = { 998 .name = "slv_venus_cfg", 999 .id = QCM2290_SLAVE_VENUS_CFG, 1000 .buswidth = 4, 1001 .qos.ap_owned = true, 1002 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1003 .mas_rpm_id = -1, 1004 .slv_rpm_id = 10, 1005}; 1006 1007static struct qcom_icc_node slv_venus_throttle_cfg = { 1008 .name = "slv_venus_throttle_cfg", 1009 .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG, 1010 .buswidth = 4, 1011 .qos.ap_owned = true, 1012 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1013 .mas_rpm_id = -1, 1014 .slv_rpm_id = 178, 1015}; 1016 1017static struct qcom_icc_node slv_vsense_ctrl_cfg = { 1018 .name = "slv_vsense_ctrl_cfg", 1019 .id = QCM2290_SLAVE_VSENSE_CTRL_CFG, 1020 .buswidth = 4, 1021 .qos.ap_owned = true, 1022 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1023 .mas_rpm_id = -1, 1024 .slv_rpm_id = 263, 1025}; 1026 1027static struct qcom_icc_node slv_service_cnoc = { 1028 .name = "slv_service_cnoc", 1029 .id = QCM2290_SLAVE_SERVICE_CNOC, 1030 .buswidth = 4, 1031 .qos.ap_owned = true, 1032 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1033 .mas_rpm_id = -1, 1034 .slv_rpm_id = 76, 1035}; 1036 1037static struct qcom_icc_node slv_qup_core_0 = { 1038 .name = "slv_qup_core_0", 1039 .id = QCM2290_SLAVE_QUP_CORE_0, 1040 .buswidth = 4, 1041 .qos.ap_owned = true, 1042 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1043 .mas_rpm_id = -1, 1044 .slv_rpm_id = 264, 1045}; 1046 1047static const u16 slv_snoc_bimc_nrt_links[] = { 1048 QCM2290_MASTER_SNOC_BIMC_NRT, 1049}; 1050 1051static struct qcom_icc_node slv_snoc_bimc_nrt = { 1052 .name = "slv_snoc_bimc_nrt", 1053 .id = QCM2290_SLAVE_SNOC_BIMC_NRT, 1054 .buswidth = 16, 1055 .qos.ap_owned = true, 1056 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1057 .mas_rpm_id = -1, 1058 .slv_rpm_id = 259, 1059 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), 1060 .links = slv_snoc_bimc_nrt_links, 1061}; 1062 1063static const u16 slv_snoc_bimc_rt_links[] = { 1064 QCM2290_MASTER_SNOC_BIMC_RT, 1065}; 1066 1067static struct qcom_icc_node slv_snoc_bimc_rt = { 1068 .name = "slv_snoc_bimc_rt", 1069 .id = QCM2290_SLAVE_SNOC_BIMC_RT, 1070 .buswidth = 16, 1071 .qos.ap_owned = true, 1072 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1073 .mas_rpm_id = -1, 1074 .slv_rpm_id = 260, 1075 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), 1076 .links = slv_snoc_bimc_rt_links, 1077}; 1078 1079static struct qcom_icc_node slv_appss = { 1080 .name = "slv_appss", 1081 .id = QCM2290_SLAVE_APPSS, 1082 .buswidth = 8, 1083 .qos.ap_owned = true, 1084 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1085 .mas_rpm_id = -1, 1086 .slv_rpm_id = 20, 1087}; 1088 1089static const u16 slv_snoc_cnoc_links[] = { 1090 QCM2290_MASTER_SNOC_CNOC, 1091}; 1092 1093static struct qcom_icc_node slv_snoc_cnoc = { 1094 .name = "slv_snoc_cnoc", 1095 .id = QCM2290_SLAVE_SNOC_CNOC, 1096 .buswidth = 8, 1097 .mas_rpm_id = -1, 1098 .slv_rpm_id = 25, 1099 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1100 .links = slv_snoc_cnoc_links, 1101}; 1102 1103static struct qcom_icc_node slv_imem = { 1104 .name = "slv_imem", 1105 .id = QCM2290_SLAVE_IMEM, 1106 .buswidth = 8, 1107 .mas_rpm_id = -1, 1108 .slv_rpm_id = 26, 1109}; 1110 1111static struct qcom_icc_node slv_pimem = { 1112 .name = "slv_pimem", 1113 .id = QCM2290_SLAVE_PIMEM, 1114 .buswidth = 8, 1115 .qos.ap_owned = true, 1116 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1117 .mas_rpm_id = -1, 1118 .slv_rpm_id = 166, 1119}; 1120 1121static const u16 slv_snoc_bimc_links[] = { 1122 QCM2290_MASTER_SNOC_BIMC, 1123}; 1124 1125static struct qcom_icc_node slv_snoc_bimc = { 1126 .name = "slv_snoc_bimc", 1127 .id = QCM2290_SLAVE_SNOC_BIMC, 1128 .buswidth = 16, 1129 .mas_rpm_id = -1, 1130 .slv_rpm_id = 24, 1131 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1132 .links = slv_snoc_bimc_links, 1133}; 1134 1135static struct qcom_icc_node slv_service_snoc = { 1136 .name = "slv_service_snoc", 1137 .id = QCM2290_SLAVE_SERVICE_SNOC, 1138 .buswidth = 4, 1139 .qos.ap_owned = true, 1140 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1141 .mas_rpm_id = -1, 1142 .slv_rpm_id = 29, 1143}; 1144 1145static struct qcom_icc_node slv_qdss_stm = { 1146 .name = "slv_qdss_stm", 1147 .id = QCM2290_SLAVE_QDSS_STM, 1148 .buswidth = 4, 1149 .mas_rpm_id = -1, 1150 .slv_rpm_id = 30, 1151}; 1152 1153static struct qcom_icc_node slv_tcu = { 1154 .name = "slv_tcu", 1155 .id = QCM2290_SLAVE_TCU, 1156 .buswidth = 8, 1157 .qos.ap_owned = true, 1158 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1159 .mas_rpm_id = -1, 1160 .slv_rpm_id = 133, 1161}; 1162 1163static const u16 slv_anoc_snoc_links[] = { 1164 QCM2290_MASTER_ANOC_SNOC, 1165}; 1166 1167static struct qcom_icc_node slv_anoc_snoc = { 1168 .name = "slv_anoc_snoc", 1169 .id = QCM2290_SLAVE_ANOC_SNOC, 1170 .buswidth = 16, 1171 .mas_rpm_id = -1, 1172 .slv_rpm_id = 141, 1173 .num_links = ARRAY_SIZE(slv_anoc_snoc_links), 1174 .links = slv_anoc_snoc_links, 1175}; 1176 1177/* NoC descriptors */ 1178static struct qcom_icc_node * const qcm2290_bimc_nodes[] = { 1179 [MASTER_APPSS_PROC] = &mas_appss_proc, 1180 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, 1181 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, 1182 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1183 [MASTER_TCU_0] = &mas_tcu_0, 1184 [MASTER_GFX3D] = &mas_gfx3d, 1185 [SLAVE_EBI1] = &slv_ebi1, 1186 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1187}; 1188 1189static const struct regmap_config qcm2290_bimc_regmap_config = { 1190 .reg_bits = 32, 1191 .reg_stride = 4, 1192 .val_bits = 32, 1193 .max_register = 0x80000, 1194 .fast_io = true, 1195}; 1196 1197static const struct qcom_icc_desc qcm2290_bimc = { 1198 .type = QCOM_ICC_BIMC, 1199 .nodes = qcm2290_bimc_nodes, 1200 .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), 1201 .bus_clk_desc = &bimc_clk, 1202 .regmap_cfg = &qcm2290_bimc_regmap_config, 1203 .keep_alive = true, 1204 /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ 1205 .qos_offset = 0x8000, 1206 .ab_coeff = 153, 1207}; 1208 1209static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { 1210 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1211 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1212 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1213 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg, 1214 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg, 1215 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1216 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1217 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1218 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1219 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1220 [SLAVE_GPU_CFG] = &slv_gpu_cfg, 1221 [SLAVE_HWKM] = &slv_hwkm, 1222 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1223 [SLAVE_IPA_CFG] = &slv_ipa_cfg, 1224 [SLAVE_LPASS] = &slv_lpass, 1225 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1226 [SLAVE_PDM] = &slv_pdm, 1227 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1228 [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper, 1229 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1230 [SLAVE_PRNG] = &slv_prng, 1231 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1232 [SLAVE_QM_CFG] = &slv_qm_cfg, 1233 [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg, 1234 [SLAVE_QPIC] = &slv_qpic, 1235 [SLAVE_QUP_0] = &slv_qup_0, 1236 [SLAVE_SDCC_1] = &slv_sdcc_1, 1237 [SLAVE_SDCC_2] = &slv_sdcc_2, 1238 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1239 [SLAVE_TCSR] = &slv_tcsr, 1240 [SLAVE_USB3] = &slv_usb3, 1241 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1242 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1243 [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg, 1244 [SLAVE_SERVICE_CNOC] = &slv_service_cnoc, 1245}; 1246 1247static const struct regmap_config qcm2290_cnoc_regmap_config = { 1248 .reg_bits = 32, 1249 .reg_stride = 4, 1250 .val_bits = 32, 1251 .max_register = 0x8200, 1252 .fast_io = true, 1253}; 1254 1255static const struct qcom_icc_desc qcm2290_cnoc = { 1256 .type = QCOM_ICC_NOC, 1257 .nodes = qcm2290_cnoc_nodes, 1258 .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), 1259 .bus_clk_desc = &bus_1_clk, 1260 .regmap_cfg = &qcm2290_cnoc_regmap_config, 1261 .keep_alive = true, 1262}; 1263 1264static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { 1265 [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, 1266 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1267 [MASTER_TIC] = &mas_tic, 1268 [MASTER_ANOC_SNOC] = &mas_anoc_snoc, 1269 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1270 [MASTER_PIMEM] = &mas_pimem, 1271 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1272 [MASTER_QUP_0] = &mas_qup_0, 1273 [MASTER_IPA] = &mas_ipa, 1274 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1275 [MASTER_SDCC_1] = &mas_sdcc_1, 1276 [MASTER_SDCC_2] = &mas_sdcc_2, 1277 [MASTER_QPIC] = &mas_qpic, 1278 [MASTER_USB3_0] = &mas_usb3_0, 1279 [SLAVE_APPSS] = &slv_appss, 1280 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1281 [SLAVE_IMEM] = &slv_imem, 1282 [SLAVE_PIMEM] = &slv_pimem, 1283 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1284 [SLAVE_SERVICE_SNOC] = &slv_service_snoc, 1285 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1286 [SLAVE_TCU] = &slv_tcu, 1287 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, 1288}; 1289 1290static const struct regmap_config qcm2290_snoc_regmap_config = { 1291 .reg_bits = 32, 1292 .reg_stride = 4, 1293 .val_bits = 32, 1294 .max_register = 0x60200, 1295 .fast_io = true, 1296}; 1297 1298static const struct qcom_icc_desc qcm2290_snoc = { 1299 .type = QCOM_ICC_QNOC, 1300 .nodes = qcm2290_snoc_nodes, 1301 .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), 1302 .bus_clk_desc = &bus_2_clk, 1303 .regmap_cfg = &qcm2290_snoc_regmap_config, 1304 .keep_alive = true, 1305 /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ 1306 .qos_offset = 0x15000, 1307}; 1308 1309static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = { 1310 [MASTER_QUP_CORE_0] = &mas_qup_core_0, 1311 [SLAVE_QUP_CORE_0] = &slv_qup_core_0 1312}; 1313 1314static const struct qcom_icc_desc qcm2290_qup_virt = { 1315 .type = QCOM_ICC_QNOC, 1316 .nodes = qcm2290_qup_virt_nodes, 1317 .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), 1318 .bus_clk_desc = &qup_clk, 1319 .keep_alive = true, 1320}; 1321 1322static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { 1323 [MASTER_CAMNOC_SF] = &mas_camnoc_sf, 1324 [MASTER_VIDEO_P0] = &mas_video_p0, 1325 [MASTER_VIDEO_PROC] = &mas_video_proc, 1326 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, 1327}; 1328 1329static const struct qcom_icc_desc qcm2290_mmnrt_virt = { 1330 .type = QCOM_ICC_QNOC, 1331 .nodes = qcm2290_mmnrt_virt_nodes, 1332 .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), 1333 .bus_clk_desc = &mmaxi_0_clk, 1334 .regmap_cfg = &qcm2290_snoc_regmap_config, 1335 .keep_alive = true, 1336 .qos_offset = 0x15000, 1337 .ab_coeff = 142, 1338}; 1339 1340static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { 1341 [MASTER_CAMNOC_HF] = &mas_camnoc_hf, 1342 [MASTER_MDP0] = &mas_mdp0, 1343 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, 1344}; 1345 1346static const struct qcom_icc_desc qcm2290_mmrt_virt = { 1347 .type = QCOM_ICC_QNOC, 1348 .nodes = qcm2290_mmrt_virt_nodes, 1349 .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), 1350 .bus_clk_desc = &mmaxi_1_clk, 1351 .regmap_cfg = &qcm2290_snoc_regmap_config, 1352 .keep_alive = true, 1353 .qos_offset = 0x15000, 1354 .ab_coeff = 139, 1355}; 1356 1357static const struct of_device_id qcm2290_noc_of_match[] = { 1358 { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc }, 1359 { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc }, 1360 { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc }, 1361 { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt }, 1362 { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt }, 1363 { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt }, 1364 { }, 1365}; 1366MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match); 1367 1368static struct platform_driver qcm2290_noc_driver = { 1369 .probe = qnoc_probe, 1370 .remove_new = qnoc_remove, 1371 .driver = { 1372 .name = "qnoc-qcm2290", 1373 .of_match_table = qcm2290_noc_of_match, 1374 .sync_state = icc_sync_state, 1375 }, 1376}; 1377module_platform_driver(qcm2290_noc_driver); 1378 1379MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver"); 1380MODULE_LICENSE("GPL v2"); 1381