1// SPDX-License-Identifier: GPL-2.0 2/* TI ADS1298 chip family driver 3 * Copyright (C) 2023 - 2024 Topic Embedded Products 4 */ 5 6#include <linux/bitfield.h> 7#include <linux/cleanup.h> 8#include <linux/clk.h> 9#include <linux/err.h> 10#include <linux/delay.h> 11#include <linux/device.h> 12#include <linux/gpio/consumer.h> 13#include <linux/log2.h> 14#include <linux/math.h> 15#include <linux/module.h> 16#include <linux/regmap.h> 17#include <linux/regulator/consumer.h> 18#include <linux/slab.h> 19#include <linux/spi/spi.h> 20#include <linux/units.h> 21 22#include <linux/iio/iio.h> 23#include <linux/iio/buffer.h> 24#include <linux/iio/kfifo_buf.h> 25 26#include <asm/unaligned.h> 27 28/* Commands */ 29#define ADS1298_CMD_WAKEUP 0x02 30#define ADS1298_CMD_STANDBY 0x04 31#define ADS1298_CMD_RESET 0x06 32#define ADS1298_CMD_START 0x08 33#define ADS1298_CMD_STOP 0x0a 34#define ADS1298_CMD_RDATAC 0x10 35#define ADS1298_CMD_SDATAC 0x11 36#define ADS1298_CMD_RDATA 0x12 37#define ADS1298_CMD_RREG 0x20 38#define ADS1298_CMD_WREG 0x40 39 40/* Registers */ 41#define ADS1298_REG_ID 0x00 42#define ADS1298_MASK_ID_FAMILY GENMASK(7, 3) 43#define ADS1298_MASK_ID_CHANNELS GENMASK(2, 0) 44#define ADS1298_ID_FAMILY_ADS129X 0x90 45#define ADS1298_ID_FAMILY_ADS129XR 0xd0 46 47#define ADS1298_REG_CONFIG1 0x01 48#define ADS1298_MASK_CONFIG1_HR BIT(7) 49#define ADS1298_MASK_CONFIG1_DR GENMASK(2, 0) 50#define ADS1298_SHIFT_DR_HR 6 51#define ADS1298_SHIFT_DR_LP 7 52#define ADS1298_LOWEST_DR 0x06 53 54#define ADS1298_REG_CONFIG2 0x02 55#define ADS1298_MASK_CONFIG2_RESERVED BIT(6) 56#define ADS1298_MASK_CONFIG2_WCT_CHOP BIT(5) 57#define ADS1298_MASK_CONFIG2_INT_TEST BIT(4) 58#define ADS1298_MASK_CONFIG2_TEST_AMP BIT(2) 59#define ADS1298_MASK_CONFIG2_TEST_FREQ_DC GENMASK(1, 0) 60#define ADS1298_MASK_CONFIG2_TEST_FREQ_SLOW 0 61#define ADS1298_MASK_CONFIG2_TEST_FREQ_FAST BIT(0) 62 63#define ADS1298_REG_CONFIG3 0x03 64#define ADS1298_MASK_CONFIG3_PWR_REFBUF BIT(7) 65#define ADS1298_MASK_CONFIG3_RESERVED BIT(6) 66#define ADS1298_MASK_CONFIG3_VREF_4V BIT(5) 67 68#define ADS1298_REG_LOFF 0x04 69#define ADS1298_REG_CHnSET(n) (0x05 + n) 70#define ADS1298_MASK_CH_PD BIT(7) 71#define ADS1298_MASK_CH_PGA GENMASK(6, 4) 72#define ADS1298_MASK_CH_MUX GENMASK(2, 0) 73 74#define ADS1298_REG_LOFF_STATP 0x12 75#define ADS1298_REG_LOFF_STATN 0x13 76#define ADS1298_REG_CONFIG4 0x17 77#define ADS1298_MASK_CONFIG4_SINGLE_SHOT BIT(3) 78 79#define ADS1298_REG_WCT1 0x18 80#define ADS1298_REG_WCT2 0x19 81 82#define ADS1298_MAX_CHANNELS 8 83#define ADS1298_BITS_PER_SAMPLE 24 84#define ADS1298_CLK_RATE_HZ 2048000 85#define ADS1298_CLOCKS_TO_USECS(x) \ 86 (DIV_ROUND_UP((x) * MICROHZ_PER_HZ, ADS1298_CLK_RATE_HZ)) 87/* 88 * Read/write register commands require 4 clocks to decode, for speeds above 89 * 2x the clock rate, this would require extra time between the command byte and 90 * the data. Much simpler is to just limit the SPI transfer speed while doing 91 * register access. 92 */ 93#define ADS1298_SPI_BUS_SPEED_SLOW ADS1298_CLK_RATE_HZ 94/* For reading and writing registers, we need a 3-byte buffer */ 95#define ADS1298_SPI_CMD_BUFFER_SIZE 3 96/* Outputs status word and 'n' 24-bit samples, plus the command byte */ 97#define ADS1298_SPI_RDATA_BUFFER_SIZE(n) (((n) + 1) * 3 + 1) 98#define ADS1298_SPI_RDATA_BUFFER_SIZE_MAX \ 99 ADS1298_SPI_RDATA_BUFFER_SIZE(ADS1298_MAX_CHANNELS) 100 101struct ads1298_private { 102 const struct ads1298_chip_info *chip_info; 103 struct spi_device *spi; 104 struct regulator *reg_avdd; 105 struct regulator *reg_vref; 106 struct clk *clk; 107 struct regmap *regmap; 108 struct completion completion; 109 struct iio_trigger *trig; 110 struct spi_transfer rdata_xfer; 111 struct spi_message rdata_msg; 112 spinlock_t irq_busy_lock; /* Handshake between SPI and DRDY irqs */ 113 /* 114 * rdata_xfer_busy increments when a DRDY occurs and decrements when SPI 115 * completion is reported. Hence its meaning is: 116 * 0 = Waiting for DRDY interrupt 117 * 1 = SPI transfer in progress 118 * 2 = DRDY during SPI transfer, start another transfer on completion 119 * >2 = Multiple DRDY during transfer, lost rdata_xfer_busy - 2 samples 120 */ 121 unsigned int rdata_xfer_busy; 122 123 /* Temporary storage for demuxing data after SPI transfer */ 124 u32 bounce_buffer[ADS1298_MAX_CHANNELS]; 125 126 /* For synchronous SPI exchanges (read/write registers) */ 127 u8 cmd_buffer[ADS1298_SPI_CMD_BUFFER_SIZE] __aligned(IIO_DMA_MINALIGN); 128 129 /* Buffer used for incoming SPI data */ 130 u8 rx_buffer[ADS1298_SPI_RDATA_BUFFER_SIZE_MAX]; 131 /* Contains the RDATA command and zeroes to clock out */ 132 u8 tx_buffer[ADS1298_SPI_RDATA_BUFFER_SIZE_MAX]; 133}; 134 135/* Three bytes per sample in RX buffer, starting at offset 4 */ 136#define ADS1298_OFFSET_IN_RX_BUFFER(index) (3 * (index) + 4) 137 138#define ADS1298_CHAN(index) \ 139{ \ 140 .type = IIO_VOLTAGE, \ 141 .indexed = 1, \ 142 .channel = index, \ 143 .address = ADS1298_OFFSET_IN_RX_BUFFER(index), \ 144 .info_mask_separate = \ 145 BIT(IIO_CHAN_INFO_RAW) | \ 146 BIT(IIO_CHAN_INFO_SCALE), \ 147 .info_mask_shared_by_all = \ 148 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 149 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 150 .scan_index = index, \ 151 .scan_type = { \ 152 .sign = 's', \ 153 .realbits = ADS1298_BITS_PER_SAMPLE, \ 154 .storagebits = 32, \ 155 .endianness = IIO_CPU, \ 156 }, \ 157} 158 159static const struct iio_chan_spec ads1298_channels[] = { 160 ADS1298_CHAN(0), 161 ADS1298_CHAN(1), 162 ADS1298_CHAN(2), 163 ADS1298_CHAN(3), 164 ADS1298_CHAN(4), 165 ADS1298_CHAN(5), 166 ADS1298_CHAN(6), 167 ADS1298_CHAN(7), 168}; 169 170static int ads1298_write_cmd(struct ads1298_private *priv, u8 command) 171{ 172 struct spi_transfer xfer = { 173 .tx_buf = priv->cmd_buffer, 174 .rx_buf = priv->cmd_buffer, 175 .len = 1, 176 .speed_hz = ADS1298_SPI_BUS_SPEED_SLOW, 177 .delay = { 178 .value = 2, 179 .unit = SPI_DELAY_UNIT_USECS, 180 }, 181 }; 182 183 priv->cmd_buffer[0] = command; 184 185 return spi_sync_transfer(priv->spi, &xfer, 1); 186} 187 188static int ads1298_read_one(struct ads1298_private *priv, int chan_index) 189{ 190 int ret; 191 192 /* Enable the channel */ 193 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CHnSET(chan_index), 194 ADS1298_MASK_CH_PD, 0); 195 if (ret) 196 return ret; 197 198 /* Enable single-shot mode, so we don't need to send a STOP */ 199 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CONFIG4, 200 ADS1298_MASK_CONFIG4_SINGLE_SHOT, 201 ADS1298_MASK_CONFIG4_SINGLE_SHOT); 202 if (ret) 203 return ret; 204 205 reinit_completion(&priv->completion); 206 207 ret = ads1298_write_cmd(priv, ADS1298_CMD_START); 208 if (ret < 0) { 209 dev_err(&priv->spi->dev, "CMD_START error: %d\n", ret); 210 return ret; 211 } 212 213 /* Cannot take longer than 40ms (250Hz) */ 214 ret = wait_for_completion_timeout(&priv->completion, msecs_to_jiffies(50)); 215 if (!ret) 216 return -ETIMEDOUT; 217 218 return 0; 219} 220 221static int ads1298_get_samp_freq(struct ads1298_private *priv, int *val) 222{ 223 unsigned long rate; 224 unsigned int cfg; 225 int ret; 226 227 ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG1, &cfg); 228 if (ret) 229 return ret; 230 231 if (priv->clk) 232 rate = clk_get_rate(priv->clk); 233 else 234 rate = ADS1298_CLK_RATE_HZ; 235 if (!rate) 236 return -EINVAL; 237 238 /* Data rate shift depends on HR/LP mode */ 239 if (cfg & ADS1298_MASK_CONFIG1_HR) 240 rate >>= ADS1298_SHIFT_DR_HR; 241 else 242 rate >>= ADS1298_SHIFT_DR_LP; 243 244 *val = rate >> (cfg & ADS1298_MASK_CONFIG1_DR); 245 246 return IIO_VAL_INT; 247} 248 249static int ads1298_set_samp_freq(struct ads1298_private *priv, int val) 250{ 251 unsigned long rate; 252 unsigned int factor; 253 unsigned int cfg; 254 255 if (priv->clk) 256 rate = clk_get_rate(priv->clk); 257 else 258 rate = ADS1298_CLK_RATE_HZ; 259 if (!rate) 260 return -EINVAL; 261 if (val <= 0) 262 return -EINVAL; 263 264 factor = (rate >> ADS1298_SHIFT_DR_HR) / val; 265 if (factor >= BIT(ADS1298_SHIFT_DR_LP)) 266 cfg = ADS1298_LOWEST_DR; 267 else if (factor) 268 cfg = ADS1298_MASK_CONFIG1_HR | ilog2(factor); /* Use HR mode */ 269 else 270 cfg = ADS1298_MASK_CONFIG1_HR; /* Fastest possible */ 271 272 return regmap_update_bits(priv->regmap, ADS1298_REG_CONFIG1, 273 ADS1298_MASK_CONFIG1_HR | ADS1298_MASK_CONFIG1_DR, 274 cfg); 275} 276 277static const u8 ads1298_pga_settings[] = { 6, 1, 2, 3, 4, 8, 12 }; 278 279static int ads1298_get_scale(struct ads1298_private *priv, 280 int channel, int *val, int *val2) 281{ 282 int ret; 283 unsigned int regval; 284 u8 gain; 285 286 if (priv->reg_vref) { 287 ret = regulator_get_voltage(priv->reg_vref); 288 if (ret < 0) 289 return ret; 290 291 *val = ret / MILLI; /* Convert to millivolts */ 292 } else { 293 ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG3, ®val); 294 if (ret) 295 return ret; 296 297 /* Refererence in millivolts */ 298 *val = regval & ADS1298_MASK_CONFIG3_VREF_4V ? 4000 : 2400; 299 } 300 301 ret = regmap_read(priv->regmap, ADS1298_REG_CHnSET(channel), ®val); 302 if (ret) 303 return ret; 304 305 gain = ads1298_pga_settings[FIELD_GET(ADS1298_MASK_CH_PGA, regval)]; 306 *val /= gain; /* Full scale is VREF / gain */ 307 308 *val2 = ADS1298_BITS_PER_SAMPLE - 1; /* Signed, hence the -1 */ 309 310 return IIO_VAL_FRACTIONAL_LOG2; 311} 312 313static int ads1298_read_raw(struct iio_dev *indio_dev, 314 struct iio_chan_spec const *chan, 315 int *val, int *val2, long mask) 316{ 317 struct ads1298_private *priv = iio_priv(indio_dev); 318 int ret; 319 320 switch (mask) { 321 case IIO_CHAN_INFO_RAW: 322 ret = iio_device_claim_direct_mode(indio_dev); 323 if (ret) 324 return ret; 325 326 ret = ads1298_read_one(priv, chan->scan_index); 327 328 iio_device_release_direct_mode(indio_dev); 329 330 if (ret) 331 return ret; 332 333 *val = sign_extend32(get_unaligned_be24(priv->rx_buffer + chan->address), 334 ADS1298_BITS_PER_SAMPLE - 1); 335 return IIO_VAL_INT; 336 case IIO_CHAN_INFO_SCALE: 337 return ads1298_get_scale(priv, chan->channel, val, val2); 338 case IIO_CHAN_INFO_SAMP_FREQ: 339 return ads1298_get_samp_freq(priv, val); 340 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 341 ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG1, val); 342 if (ret) 343 return ret; 344 345 *val = 16 << (*val & ADS1298_MASK_CONFIG1_DR); 346 return IIO_VAL_INT; 347 default: 348 return -EINVAL; 349 } 350} 351 352static int ads1298_write_raw(struct iio_dev *indio_dev, 353 struct iio_chan_spec const *chan, int val, 354 int val2, long mask) 355{ 356 struct ads1298_private *priv = iio_priv(indio_dev); 357 358 switch (mask) { 359 case IIO_CHAN_INFO_SAMP_FREQ: 360 return ads1298_set_samp_freq(priv, val); 361 default: 362 return -EINVAL; 363 } 364} 365 366static int ads1298_reg_write(void *context, unsigned int reg, unsigned int val) 367{ 368 struct ads1298_private *priv = context; 369 struct spi_transfer reg_write_xfer = { 370 .tx_buf = priv->cmd_buffer, 371 .rx_buf = priv->cmd_buffer, 372 .len = 3, 373 .speed_hz = ADS1298_SPI_BUS_SPEED_SLOW, 374 .delay = { 375 .value = 2, 376 .unit = SPI_DELAY_UNIT_USECS, 377 }, 378 }; 379 380 priv->cmd_buffer[0] = ADS1298_CMD_WREG | reg; 381 priv->cmd_buffer[1] = 0; /* Number of registers to be written - 1 */ 382 priv->cmd_buffer[2] = val; 383 384 return spi_sync_transfer(priv->spi, ®_write_xfer, 1); 385} 386 387static int ads1298_reg_read(void *context, unsigned int reg, unsigned int *val) 388{ 389 struct ads1298_private *priv = context; 390 struct spi_transfer reg_read_xfer = { 391 .tx_buf = priv->cmd_buffer, 392 .rx_buf = priv->cmd_buffer, 393 .len = 3, 394 .speed_hz = ADS1298_SPI_BUS_SPEED_SLOW, 395 .delay = { 396 .value = 2, 397 .unit = SPI_DELAY_UNIT_USECS, 398 }, 399 }; 400 int ret; 401 402 priv->cmd_buffer[0] = ADS1298_CMD_RREG | reg; 403 priv->cmd_buffer[1] = 0; /* Number of registers to be read - 1 */ 404 priv->cmd_buffer[2] = 0; 405 406 ret = spi_sync_transfer(priv->spi, ®_read_xfer, 1); 407 if (ret) 408 return ret; 409 410 *val = priv->cmd_buffer[2]; 411 412 return 0; 413} 414 415static int ads1298_reg_access(struct iio_dev *indio_dev, unsigned int reg, 416 unsigned int writeval, unsigned int *readval) 417{ 418 struct ads1298_private *priv = iio_priv(indio_dev); 419 420 if (readval) 421 return regmap_read(priv->regmap, reg, readval); 422 423 return regmap_write(priv->regmap, reg, writeval); 424} 425 426static void ads1298_rdata_unmark_busy(struct ads1298_private *priv) 427{ 428 /* Notify we're no longer waiting for the SPI transfer to complete */ 429 guard(spinlock_irqsave)(&priv->irq_busy_lock); 430 priv->rdata_xfer_busy = 0; 431} 432 433static int ads1298_update_scan_mode(struct iio_dev *indio_dev, 434 const unsigned long *scan_mask) 435{ 436 struct ads1298_private *priv = iio_priv(indio_dev); 437 unsigned int val; 438 int ret; 439 int i; 440 441 /* Make the interrupt routines start with a clean slate */ 442 ads1298_rdata_unmark_busy(priv); 443 444 /* Configure power-down bits to match scan mask */ 445 for (i = 0; i < indio_dev->num_channels; i++) { 446 val = test_bit(i, scan_mask) ? 0 : ADS1298_MASK_CH_PD; 447 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CHnSET(i), 448 ADS1298_MASK_CH_PD, val); 449 if (ret) 450 return ret; 451 } 452 453 return 0; 454} 455 456static const struct iio_info ads1298_info = { 457 .read_raw = &ads1298_read_raw, 458 .write_raw = &ads1298_write_raw, 459 .update_scan_mode = &ads1298_update_scan_mode, 460 .debugfs_reg_access = &ads1298_reg_access, 461}; 462 463static void ads1298_rdata_release_busy_or_restart(struct ads1298_private *priv) 464{ 465 guard(spinlock_irqsave)(&priv->irq_busy_lock); 466 467 if (priv->rdata_xfer_busy > 1) { 468 /* 469 * DRDY interrupt occurred before SPI completion. Start a new 470 * SPI transaction now to retrieve the data that wasn't latched 471 * into the ADS1298 chip's transfer buffer yet. 472 */ 473 spi_async(priv->spi, &priv->rdata_msg); 474 /* 475 * If more than one DRDY took place, there was an overrun. Since 476 * the sample is already lost, reset the counter to 1 so that 477 * we will wait for a DRDY interrupt after this SPI transaction. 478 */ 479 priv->rdata_xfer_busy = 1; 480 } else { 481 /* No pending data, wait for DRDY */ 482 priv->rdata_xfer_busy = 0; 483 } 484} 485 486/* Called from SPI completion interrupt handler */ 487static void ads1298_rdata_complete(void *context) 488{ 489 struct iio_dev *indio_dev = context; 490 struct ads1298_private *priv = iio_priv(indio_dev); 491 int scan_index; 492 u32 *bounce = priv->bounce_buffer; 493 494 if (!iio_buffer_enabled(indio_dev)) { 495 /* 496 * for a single transfer mode we're kept in direct_mode until 497 * completion, avoiding a race with buffered IO. 498 */ 499 ads1298_rdata_unmark_busy(priv); 500 complete(&priv->completion); 501 return; 502 } 503 504 /* Demux the channel data into our bounce buffer */ 505 for_each_set_bit(scan_index, indio_dev->active_scan_mask, 506 indio_dev->masklength) { 507 const struct iio_chan_spec *scan_chan = 508 &indio_dev->channels[scan_index]; 509 const u8 *data = priv->rx_buffer + scan_chan->address; 510 511 *bounce++ = get_unaligned_be24(data); 512 } 513 514 /* rx_buffer can be overwritten from this point on */ 515 ads1298_rdata_release_busy_or_restart(priv); 516 517 iio_push_to_buffers(indio_dev, priv->bounce_buffer); 518} 519 520static irqreturn_t ads1298_interrupt(int irq, void *dev_id) 521{ 522 struct iio_dev *indio_dev = dev_id; 523 struct ads1298_private *priv = iio_priv(indio_dev); 524 unsigned int wasbusy; 525 526 guard(spinlock_irqsave)(&priv->irq_busy_lock); 527 528 wasbusy = priv->rdata_xfer_busy++; 529 /* When no SPI transfer in transit, start one now */ 530 if (!wasbusy) 531 spi_async(priv->spi, &priv->rdata_msg); 532 533 return IRQ_HANDLED; 534}; 535 536static int ads1298_buffer_postenable(struct iio_dev *indio_dev) 537{ 538 struct ads1298_private *priv = iio_priv(indio_dev); 539 int ret; 540 541 /* Disable single-shot mode */ 542 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CONFIG4, 543 ADS1298_MASK_CONFIG4_SINGLE_SHOT, 0); 544 if (ret) 545 return ret; 546 547 return ads1298_write_cmd(priv, ADS1298_CMD_START); 548} 549 550static int ads1298_buffer_predisable(struct iio_dev *indio_dev) 551{ 552 struct ads1298_private *priv = iio_priv(indio_dev); 553 554 return ads1298_write_cmd(priv, ADS1298_CMD_STOP); 555} 556 557static const struct iio_buffer_setup_ops ads1298_setup_ops = { 558 .postenable = &ads1298_buffer_postenable, 559 .predisable = &ads1298_buffer_predisable, 560}; 561 562static void ads1298_reg_disable(void *reg) 563{ 564 regulator_disable(reg); 565} 566 567static const struct regmap_range ads1298_regmap_volatile_range[] = { 568 regmap_reg_range(ADS1298_REG_LOFF_STATP, ADS1298_REG_LOFF_STATN), 569}; 570 571static const struct regmap_access_table ads1298_regmap_volatile = { 572 .yes_ranges = ads1298_regmap_volatile_range, 573 .n_yes_ranges = ARRAY_SIZE(ads1298_regmap_volatile_range), 574}; 575 576static const struct regmap_config ads1298_regmap_config = { 577 .reg_bits = 8, 578 .val_bits = 8, 579 .reg_read = ads1298_reg_read, 580 .reg_write = ads1298_reg_write, 581 .max_register = ADS1298_REG_WCT2, 582 .volatile_table = &ads1298_regmap_volatile, 583 .cache_type = REGCACHE_MAPLE, 584}; 585 586static int ads1298_init(struct iio_dev *indio_dev) 587{ 588 struct ads1298_private *priv = iio_priv(indio_dev); 589 struct device *dev = &priv->spi->dev; 590 const char *suffix; 591 unsigned int val; 592 int ret; 593 594 /* Device initializes into RDATAC mode, which we don't want */ 595 ret = ads1298_write_cmd(priv, ADS1298_CMD_SDATAC); 596 if (ret) 597 return ret; 598 599 ret = regmap_read(priv->regmap, ADS1298_REG_ID, &val); 600 if (ret) 601 return ret; 602 603 /* Fill in name and channel count based on what the chip told us */ 604 indio_dev->num_channels = 4 + 2 * (val & ADS1298_MASK_ID_CHANNELS); 605 switch (val & ADS1298_MASK_ID_FAMILY) { 606 case ADS1298_ID_FAMILY_ADS129X: 607 suffix = ""; 608 break; 609 case ADS1298_ID_FAMILY_ADS129XR: 610 suffix = "r"; 611 break; 612 default: 613 return dev_err_probe(dev, -ENODEV, "Unknown ID: 0x%x\n", val); 614 } 615 indio_dev->name = devm_kasprintf(dev, GFP_KERNEL, "ads129%u%s", 616 indio_dev->num_channels, suffix); 617 618 /* Enable internal test signal, double amplitude, double frequency */ 619 ret = regmap_write(priv->regmap, ADS1298_REG_CONFIG2, 620 ADS1298_MASK_CONFIG2_RESERVED | 621 ADS1298_MASK_CONFIG2_INT_TEST | 622 ADS1298_MASK_CONFIG2_TEST_AMP | 623 ADS1298_MASK_CONFIG2_TEST_FREQ_FAST); 624 if (ret) 625 return ret; 626 627 val = ADS1298_MASK_CONFIG3_RESERVED; /* Must write 1 always */ 628 if (!priv->reg_vref) { 629 /* Enable internal reference */ 630 val |= ADS1298_MASK_CONFIG3_PWR_REFBUF; 631 /* Use 4V VREF when power supply is at least 4.4V */ 632 if (regulator_get_voltage(priv->reg_avdd) >= 4400000) 633 val |= ADS1298_MASK_CONFIG3_VREF_4V; 634 } 635 return regmap_write(priv->regmap, ADS1298_REG_CONFIG3, val); 636} 637 638static int ads1298_probe(struct spi_device *spi) 639{ 640 struct ads1298_private *priv; 641 struct iio_dev *indio_dev; 642 struct device *dev = &spi->dev; 643 struct gpio_desc *reset_gpio; 644 int ret; 645 646 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); 647 if (!indio_dev) 648 return -ENOMEM; 649 650 priv = iio_priv(indio_dev); 651 652 /* Reset to be asserted before enabling clock and power */ 653 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 654 if (IS_ERR(reset_gpio)) 655 return dev_err_probe(dev, PTR_ERR(reset_gpio), 656 "Cannot get reset GPIO\n"); 657 658 /* VREF can be supplied externally, otherwise use internal reference */ 659 priv->reg_vref = devm_regulator_get_optional(dev, "vref"); 660 if (IS_ERR(priv->reg_vref)) { 661 if (PTR_ERR(priv->reg_vref) != -ENODEV) 662 return dev_err_probe(dev, PTR_ERR(priv->reg_vref), 663 "Failed to get vref regulator\n"); 664 665 priv->reg_vref = NULL; 666 } else { 667 ret = regulator_enable(priv->reg_vref); 668 if (ret) 669 return ret; 670 671 ret = devm_add_action_or_reset(dev, ads1298_reg_disable, priv->reg_vref); 672 if (ret) 673 return ret; 674 } 675 676 priv->clk = devm_clk_get_optional_enabled(dev, "clk"); 677 if (IS_ERR(priv->clk)) 678 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clk\n"); 679 680 priv->reg_avdd = devm_regulator_get(dev, "avdd"); 681 if (IS_ERR(priv->reg_avdd)) 682 return dev_err_probe(dev, PTR_ERR(priv->reg_avdd), 683 "Failed to get avdd regulator\n"); 684 685 ret = regulator_enable(priv->reg_avdd); 686 if (ret) 687 return dev_err_probe(dev, ret, "Failed to enable avdd regulator\n"); 688 689 ret = devm_add_action_or_reset(dev, ads1298_reg_disable, priv->reg_avdd); 690 if (ret) 691 return ret; 692 693 priv->spi = spi; 694 init_completion(&priv->completion); 695 spin_lock_init(&priv->irq_busy_lock); 696 priv->regmap = devm_regmap_init(dev, NULL, priv, &ads1298_regmap_config); 697 if (IS_ERR(priv->regmap)) 698 return PTR_ERR(priv->regmap); 699 700 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 701 indio_dev->channels = ads1298_channels; 702 indio_dev->info = &ads1298_info; 703 704 if (reset_gpio) { 705 /* 706 * Deassert reset now that clock and power are active. 707 * Minimum reset pulsewidth is 2 clock cycles. 708 */ 709 fsleep(ADS1298_CLOCKS_TO_USECS(2)); 710 gpiod_set_value_cansleep(reset_gpio, 0); 711 } else { 712 ret = ads1298_write_cmd(priv, ADS1298_CMD_RESET); 713 if (ret) 714 return dev_err_probe(dev, ret, "RESET failed\n"); 715 } 716 /* Wait 18 clock cycles for reset command to complete */ 717 fsleep(ADS1298_CLOCKS_TO_USECS(18)); 718 719 ret = ads1298_init(indio_dev); 720 if (ret) 721 return dev_err_probe(dev, ret, "Init failed\n"); 722 723 priv->tx_buffer[0] = ADS1298_CMD_RDATA; 724 priv->rdata_xfer.tx_buf = priv->tx_buffer; 725 priv->rdata_xfer.rx_buf = priv->rx_buffer; 726 priv->rdata_xfer.len = ADS1298_SPI_RDATA_BUFFER_SIZE(indio_dev->num_channels); 727 /* Must keep CS low for 4 clocks */ 728 priv->rdata_xfer.delay.value = 2; 729 priv->rdata_xfer.delay.unit = SPI_DELAY_UNIT_USECS; 730 spi_message_init_with_transfers(&priv->rdata_msg, &priv->rdata_xfer, 1); 731 priv->rdata_msg.complete = &ads1298_rdata_complete; 732 priv->rdata_msg.context = indio_dev; 733 734 ret = devm_request_irq(dev, spi->irq, &ads1298_interrupt, 735 IRQF_TRIGGER_FALLING, indio_dev->name, 736 indio_dev); 737 if (ret) 738 return ret; 739 740 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &ads1298_setup_ops); 741 if (ret) 742 return ret; 743 744 return devm_iio_device_register(dev, indio_dev); 745} 746 747static const struct spi_device_id ads1298_id[] = { 748 { "ads1298" }, 749 { } 750}; 751MODULE_DEVICE_TABLE(spi, ads1298_id); 752 753static const struct of_device_id ads1298_of_table[] = { 754 { .compatible = "ti,ads1298" }, 755 { } 756}; 757MODULE_DEVICE_TABLE(of, ads1298_of_table); 758 759static struct spi_driver ads1298_driver = { 760 .driver = { 761 .name = "ads1298", 762 .of_match_table = ads1298_of_table, 763 }, 764 .probe = ads1298_probe, 765 .id_table = ads1298_id, 766}; 767module_spi_driver(ads1298_driver); 768 769MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 770MODULE_DESCRIPTION("TI ADS1298 ADC"); 771MODULE_LICENSE("GPL"); 772