1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Microchip MCP3911, Two-channel Analog Front End 4 * 5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com> 6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se> 7 */ 8#include <linux/bitfield.h> 9#include <linux/bits.h> 10#include <linux/cleanup.h> 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/err.h> 14#include <linux/module.h> 15#include <linux/mod_devicetable.h> 16#include <linux/property.h> 17#include <linux/regulator/consumer.h> 18#include <linux/spi/spi.h> 19 20#include <linux/iio/iio.h> 21#include <linux/iio/buffer.h> 22#include <linux/iio/triggered_buffer.h> 23#include <linux/iio/trigger_consumer.h> 24#include <linux/iio/trigger.h> 25 26#include <asm/unaligned.h> 27 28#define MCP3911_REG_CHANNEL0 0x00 29#define MCP3911_REG_CHANNEL1 0x03 30#define MCP3911_REG_MOD 0x06 31#define MCP3911_REG_PHASE 0x07 32#define MCP3911_REG_GAIN 0x09 33#define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch)) 34#define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch)) 35 36#define MCP3911_REG_STATUSCOM 0x0a 37#define MCP3911_STATUSCOM_DRHIZ BIT(12) 38#define MCP3911_STATUSCOM_READ GENMASK(7, 6) 39#define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) 40#define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) 41#define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) 42#define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) 43 44#define MCP3911_REG_CONFIG 0x0c 45#define MCP3911_CONFIG_CLKEXT BIT(1) 46#define MCP3911_CONFIG_VREFEXT BIT(2) 47#define MCP3911_CONFIG_OSR GENMASK(13, 11) 48 49#define MCP3911_REG_OFFCAL_CH0 0x0e 50#define MCP3911_REG_GAINCAL_CH0 0x11 51#define MCP3911_REG_OFFCAL_CH1 0x14 52#define MCP3911_REG_GAINCAL_CH1 0x17 53#define MCP3911_REG_VREFCAL 0x1a 54 55#define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3) 56#define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6) 57 58/* Internal voltage reference in mV */ 59#define MCP3911_INT_VREF_MV 1200 60 61#define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff) 62#define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff) 63#define MCP3911_REG_MASK GENMASK(4, 1) 64 65#define MCP3911_NUM_SCALES 6 66 67/* Registers compatible with MCP3910 */ 68#define MCP3910_REG_STATUSCOM 0x0c 69#define MCP3910_STATUSCOM_READ GENMASK(23, 22) 70#define MCP3910_STATUSCOM_DRHIZ BIT(20) 71 72#define MCP3910_REG_GAIN 0x0b 73 74#define MCP3910_REG_CONFIG0 0x0d 75#define MCP3910_CONFIG0_EN_OFFCAL BIT(23) 76#define MCP3910_CONFIG0_OSR GENMASK(15, 13) 77 78#define MCP3910_REG_CONFIG1 0x0e 79#define MCP3910_CONFIG1_CLKEXT BIT(6) 80#define MCP3910_CONFIG1_VREFEXT BIT(7) 81 82#define MCP3910_REG_OFFCAL_CH0 0x0f 83#define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6) 84 85/* Maximal number of channels used by the MCP39XX family */ 86#define MCP39XX_MAX_NUM_CHANNELS 8 87 88static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; 89static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2]; 90 91enum mcp3911_id { 92 MCP3910, 93 MCP3911, 94 MCP3912, 95 MCP3913, 96 MCP3914, 97 MCP3918, 98 MCP3919, 99}; 100 101struct mcp3911; 102struct mcp3911_chip_info { 103 const struct iio_chan_spec *channels; 104 unsigned int num_channels; 105 106 int (*config)(struct mcp3911 *adc); 107 int (*get_osr)(struct mcp3911 *adc, u32 *val); 108 int (*set_osr)(struct mcp3911 *adc, u32 val); 109 int (*enable_offset)(struct mcp3911 *adc, bool enable); 110 int (*get_offset)(struct mcp3911 *adc, int channel, int *val); 111 int (*set_offset)(struct mcp3911 *adc, int channel, int val); 112 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val); 113}; 114 115struct mcp3911 { 116 struct spi_device *spi; 117 struct mutex lock; 118 struct regulator *vref; 119 struct clk *clki; 120 u32 dev_addr; 121 struct iio_trigger *trig; 122 u32 gain[MCP39XX_MAX_NUM_CHANNELS]; 123 const struct mcp3911_chip_info *chip; 124 struct { 125 u32 channels[MCP39XX_MAX_NUM_CHANNELS]; 126 s64 ts __aligned(8); 127 } scan; 128 129 u8 tx_buf __aligned(IIO_DMA_MINALIGN); 130 u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3]; 131}; 132 133static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) 134{ 135 int ret; 136 137 reg = MCP3911_REG_READ(reg, adc->dev_addr); 138 ret = spi_write_then_read(adc->spi, ®, 1, val, len); 139 if (ret < 0) 140 return ret; 141 142 be32_to_cpus(val); 143 *val >>= ((4 - len) * 8); 144 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, 145 FIELD_GET(MCP3911_REG_MASK, reg)); 146 return ret; 147} 148 149static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) 150{ 151 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); 152 153 val <<= (3 - len) * 8; 154 cpu_to_be32s(&val); 155 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); 156 157 return spi_write(adc->spi, &val, len + 1); 158} 159 160static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len) 161{ 162 u32 tmp; 163 int ret; 164 165 ret = mcp3911_read(adc, reg, &tmp, len); 166 if (ret) 167 return ret; 168 169 val &= mask; 170 val |= tmp & ~mask; 171 return mcp3911_write(adc, reg, val, len); 172} 173 174static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) 175{ 176 unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL; 177 unsigned int value = enable ? mask : 0; 178 179 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); 180} 181 182static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) 183{ 184 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3); 185} 186 187static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) 188{ 189 int ret; 190 191 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3); 192 if (ret) 193 return ret; 194 195 return adc->chip->enable_offset(adc, 1); 196} 197 198static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) 199{ 200 unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL; 201 unsigned int value = enable ? mask : 0; 202 203 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2); 204} 205 206static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) 207{ 208 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3); 209} 210 211static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) 212{ 213 int ret; 214 215 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3); 216 if (ret) 217 return ret; 218 219 return adc->chip->enable_offset(adc, 1); 220} 221 222static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) 223{ 224 int ret; 225 unsigned int osr; 226 227 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); 228 if (ret) 229 return ret; 230 231 osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val); 232 *val = 32 << osr; 233 return 0; 234} 235 236static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) 237{ 238 unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val); 239 unsigned int mask = MCP3910_CONFIG0_OSR; 240 241 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); 242} 243 244static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) 245{ 246 unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val); 247 unsigned int mask = MCP3911_CONFIG_OSR; 248 249 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); 250} 251 252static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) 253{ 254 int ret; 255 unsigned int osr; 256 257 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 258 if (ret) 259 return ret; 260 261 osr = FIELD_GET(MCP3911_CONFIG_OSR, *val); 262 *val = 32 << osr; 263 return ret; 264} 265 266static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) 267{ 268 return mcp3911_update(adc, MCP3910_REG_GAIN, 269 MCP3911_GAIN_MASK(channel), 270 MCP3911_GAIN_VAL(channel, val), 3); 271} 272 273static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) 274{ 275 return mcp3911_update(adc, MCP3911_REG_GAIN, 276 MCP3911_GAIN_MASK(channel), 277 MCP3911_GAIN_VAL(channel, val), 1); 278} 279 280static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, 281 struct iio_chan_spec const *chan, 282 long mask) 283{ 284 switch (mask) { 285 case IIO_CHAN_INFO_SCALE: 286 return IIO_VAL_INT_PLUS_NANO; 287 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 288 return IIO_VAL_INT; 289 default: 290 return IIO_VAL_INT_PLUS_NANO; 291 } 292} 293 294static int mcp3911_read_avail(struct iio_dev *indio_dev, 295 struct iio_chan_spec const *chan, 296 const int **vals, int *type, int *length, 297 long info) 298{ 299 switch (info) { 300 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 301 *type = IIO_VAL_INT; 302 *vals = mcp3911_osr_table; 303 *length = ARRAY_SIZE(mcp3911_osr_table); 304 return IIO_AVAIL_LIST; 305 case IIO_CHAN_INFO_SCALE: 306 *type = IIO_VAL_INT_PLUS_NANO; 307 *vals = (int *)mcp3911_scale_table; 308 *length = ARRAY_SIZE(mcp3911_scale_table) * 2; 309 return IIO_AVAIL_LIST; 310 default: 311 return -EINVAL; 312 } 313} 314 315static int mcp3911_read_raw(struct iio_dev *indio_dev, 316 struct iio_chan_spec const *channel, int *val, 317 int *val2, long mask) 318{ 319 struct mcp3911 *adc = iio_priv(indio_dev); 320 int ret; 321 322 guard(mutex)(&adc->lock); 323 switch (mask) { 324 case IIO_CHAN_INFO_RAW: 325 ret = mcp3911_read(adc, 326 MCP3911_CHANNEL(channel->channel), val, 3); 327 if (ret) 328 return ret; 329 330 *val = sign_extend32(*val, 23); 331 return IIO_VAL_INT; 332 case IIO_CHAN_INFO_OFFSET: 333 ret = adc->chip->get_offset(adc, channel->channel, val); 334 if (ret) 335 return ret; 336 337 return IIO_VAL_INT; 338 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 339 ret = adc->chip->get_osr(adc, val); 340 if (ret) 341 return ret; 342 343 return IIO_VAL_INT; 344 case IIO_CHAN_INFO_SCALE: 345 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0]; 346 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1]; 347 return IIO_VAL_INT_PLUS_NANO; 348 default: 349 return -EINVAL; 350 } 351} 352 353static int mcp3911_write_raw(struct iio_dev *indio_dev, 354 struct iio_chan_spec const *channel, int val, 355 int val2, long mask) 356{ 357 struct mcp3911 *adc = iio_priv(indio_dev); 358 359 guard(mutex)(&adc->lock); 360 switch (mask) { 361 case IIO_CHAN_INFO_SCALE: 362 for (int i = 0; i < MCP3911_NUM_SCALES; i++) { 363 if (val == mcp3911_scale_table[i][0] && 364 val2 == mcp3911_scale_table[i][1]) { 365 366 adc->gain[channel->channel] = BIT(i); 367 return adc->chip->set_scale(adc, channel->channel, i); 368 } 369 } 370 return -EINVAL; 371 case IIO_CHAN_INFO_OFFSET: 372 if (val2 != 0) 373 return -EINVAL; 374 375 return adc->chip->set_offset(adc, channel->channel, val); 376 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 377 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) { 378 if (val == mcp3911_osr_table[i]) { 379 return adc->chip->set_osr(adc, i); 380 } 381 } 382 return -EINVAL; 383 default: 384 return -EINVAL; 385 } 386} 387 388static int mcp3911_calc_scale_table(struct mcp3911 *adc) 389{ 390 struct device *dev = &adc->spi->dev; 391 u32 ref = MCP3911_INT_VREF_MV; 392 u32 div; 393 int ret; 394 u64 tmp; 395 396 if (adc->vref) { 397 ret = regulator_get_voltage(adc->vref); 398 if (ret < 0) { 399 return dev_err_probe(dev, ret, "failed to get vref voltage\n"); 400 } 401 402 ref = ret / 1000; 403 } 404 405 /* 406 * For 24-bit Conversion 407 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5 408 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5) 409 * 410 * ref = Reference voltage 411 * div = (2^23 * 1.5 * gain) = 12582912 * gain 412 */ 413 for (int i = 0; i < MCP3911_NUM_SCALES; i++) { 414 div = 12582912 * BIT(i); 415 tmp = div_s64((s64)ref * 1000000000LL, div); 416 417 mcp3911_scale_table[i][0] = 0; 418 mcp3911_scale_table[i][1] = tmp; 419 } 420 421 return 0; 422} 423 424#define MCP3911_CHAN(idx) { \ 425 .type = IIO_VOLTAGE, \ 426 .indexed = 1, \ 427 .channel = idx, \ 428 .scan_index = idx, \ 429 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 430 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 431 BIT(IIO_CHAN_INFO_OFFSET) | \ 432 BIT(IIO_CHAN_INFO_SCALE), \ 433 .info_mask_shared_by_type_available = \ 434 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 435 .info_mask_separate_available = \ 436 BIT(IIO_CHAN_INFO_SCALE), \ 437 .scan_type = { \ 438 .sign = 's', \ 439 .realbits = 24, \ 440 .storagebits = 32, \ 441 .endianness = IIO_BE, \ 442 }, \ 443} 444 445static const struct iio_chan_spec mcp3910_channels[] = { 446 MCP3911_CHAN(0), 447 MCP3911_CHAN(1), 448 IIO_CHAN_SOFT_TIMESTAMP(2), 449}; 450 451static const struct iio_chan_spec mcp3911_channels[] = { 452 MCP3911_CHAN(0), 453 MCP3911_CHAN(1), 454 IIO_CHAN_SOFT_TIMESTAMP(2), 455}; 456 457static const struct iio_chan_spec mcp3912_channels[] = { 458 MCP3911_CHAN(0), 459 MCP3911_CHAN(1), 460 MCP3911_CHAN(2), 461 MCP3911_CHAN(3), 462 IIO_CHAN_SOFT_TIMESTAMP(4), 463}; 464 465static const struct iio_chan_spec mcp3913_channels[] = { 466 MCP3911_CHAN(0), 467 MCP3911_CHAN(1), 468 MCP3911_CHAN(2), 469 MCP3911_CHAN(3), 470 MCP3911_CHAN(4), 471 MCP3911_CHAN(5), 472 IIO_CHAN_SOFT_TIMESTAMP(6), 473}; 474 475static const struct iio_chan_spec mcp3914_channels[] = { 476 MCP3911_CHAN(0), 477 MCP3911_CHAN(1), 478 MCP3911_CHAN(2), 479 MCP3911_CHAN(3), 480 MCP3911_CHAN(4), 481 MCP3911_CHAN(5), 482 MCP3911_CHAN(6), 483 MCP3911_CHAN(7), 484 IIO_CHAN_SOFT_TIMESTAMP(8), 485}; 486 487static const struct iio_chan_spec mcp3918_channels[] = { 488 MCP3911_CHAN(0), 489 IIO_CHAN_SOFT_TIMESTAMP(1), 490}; 491 492static const struct iio_chan_spec mcp3919_channels[] = { 493 MCP3911_CHAN(0), 494 MCP3911_CHAN(1), 495 MCP3911_CHAN(2), 496 IIO_CHAN_SOFT_TIMESTAMP(3), 497}; 498 499static irqreturn_t mcp3911_trigger_handler(int irq, void *p) 500{ 501 struct iio_poll_func *pf = p; 502 struct iio_dev *indio_dev = pf->indio_dev; 503 struct mcp3911 *adc = iio_priv(indio_dev); 504 struct device *dev = &adc->spi->dev; 505 struct spi_transfer xfer[] = { 506 { 507 .tx_buf = &adc->tx_buf, 508 .len = 1, 509 }, { 510 .rx_buf = adc->rx_buf, 511 .len = (adc->chip->num_channels - 1) * 3, 512 }, 513 }; 514 int scan_index; 515 int i = 0; 516 int ret; 517 518 guard(mutex)(&adc->lock); 519 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); 520 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer)); 521 if (ret < 0) { 522 dev_warn(dev, "failed to get conversion data\n"); 523 goto out; 524 } 525 526 for_each_set_bit(scan_index, indio_dev->active_scan_mask, indio_dev->masklength) { 527 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index]; 528 529 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]); 530 i++; 531 } 532 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan, 533 iio_get_time_ns(indio_dev)); 534out: 535 iio_trigger_notify_done(indio_dev->trig); 536 537 return IRQ_HANDLED; 538} 539 540static const struct iio_info mcp3911_info = { 541 .read_raw = mcp3911_read_raw, 542 .write_raw = mcp3911_write_raw, 543 .read_avail = mcp3911_read_avail, 544 .write_raw_get_fmt = mcp3911_write_raw_get_fmt, 545}; 546 547static int mcp3911_config(struct mcp3911 *adc) 548{ 549 struct device *dev = &adc->spi->dev; 550 u32 regval; 551 int ret; 552 553 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2); 554 if (ret) 555 return ret; 556 557 regval &= ~MCP3911_CONFIG_VREFEXT; 558 if (adc->vref) { 559 dev_dbg(dev, "use external voltage reference\n"); 560 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1); 561 } else { 562 dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 563 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0); 564 } 565 566 regval &= ~MCP3911_CONFIG_CLKEXT; 567 if (adc->clki) { 568 dev_dbg(dev, "use external clock as clocksource\n"); 569 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1); 570 } else { 571 dev_dbg(dev, "use crystal oscillator as clocksource\n"); 572 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0); 573 } 574 575 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2); 576 if (ret) 577 return ret; 578 579 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2); 580 if (ret) 581 return ret; 582 583 /* Address counter incremented, cycle through register types */ 584 regval &= ~MCP3911_STATUSCOM_READ; 585 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02); 586 587 regval &= ~MCP3911_STATUSCOM_DRHIZ; 588 if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 589 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0); 590 else 591 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1); 592 593 /* Disable offset to ignore any old values in offset register */ 594 regval &= ~MCP3911_STATUSCOM_EN_OFFCAL; 595 596 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 597 if (ret) 598 return ret; 599 600 /* Set gain to 1 for all channels */ 601 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1); 602 if (ret) 603 return ret; 604 605 for (int i = 0; i < adc->chip->num_channels - 1; i++) { 606 adc->gain[i] = 1; 607 regval &= ~MCP3911_GAIN_MASK(i); 608 } 609 610 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1); 611} 612 613static int mcp3910_config(struct mcp3911 *adc) 614{ 615 struct device *dev = &adc->spi->dev; 616 u32 regval; 617 int ret; 618 619 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3); 620 if (ret) 621 return ret; 622 623 regval &= ~MCP3910_CONFIG1_VREFEXT; 624 if (adc->vref) { 625 dev_dbg(dev, "use external voltage reference\n"); 626 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1); 627 } else { 628 dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 629 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0); 630 } 631 632 regval &= ~MCP3910_CONFIG1_CLKEXT; 633 if (adc->clki) { 634 dev_dbg(dev, "use external clock as clocksource\n"); 635 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1); 636 } else { 637 dev_dbg(dev, "use crystal oscillator as clocksource\n"); 638 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0); 639 } 640 641 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3); 642 if (ret) 643 return ret; 644 645 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3); 646 if (ret) 647 return ret; 648 649 /* Address counter incremented, cycle through register types */ 650 regval &= ~MCP3910_STATUSCOM_READ; 651 regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02); 652 653 regval &= ~MCP3910_STATUSCOM_DRHIZ; 654 if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 655 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0); 656 else 657 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1); 658 659 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3); 660 if (ret) 661 return ret; 662 663 /* Set gain to 1 for all channels */ 664 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3); 665 if (ret) 666 return ret; 667 668 for (int i = 0; i < adc->chip->num_channels - 1; i++) { 669 adc->gain[i] = 1; 670 regval &= ~MCP3911_GAIN_MASK(i); 671 } 672 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3); 673 if (ret) 674 return ret; 675 676 /* Disable offset to ignore any old values in offset register */ 677 return adc->chip->enable_offset(adc, 0); 678} 679 680static void mcp3911_cleanup_regulator(void *vref) 681{ 682 regulator_disable(vref); 683} 684 685static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable) 686{ 687 struct mcp3911 *adc = iio_trigger_get_drvdata(trig); 688 689 if (enable) 690 enable_irq(adc->spi->irq); 691 else 692 disable_irq(adc->spi->irq); 693 694 return 0; 695} 696 697static const struct iio_trigger_ops mcp3911_trigger_ops = { 698 .validate_device = iio_trigger_validate_own_device, 699 .set_trigger_state = mcp3911_set_trigger_state, 700}; 701 702static int mcp3911_probe(struct spi_device *spi) 703{ 704 struct device *dev = &spi->dev; 705 struct iio_dev *indio_dev; 706 struct mcp3911 *adc; 707 int ret; 708 709 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 710 if (!indio_dev) 711 return -ENOMEM; 712 713 adc = iio_priv(indio_dev); 714 adc->spi = spi; 715 adc->chip = spi_get_device_match_data(spi); 716 717 adc->vref = devm_regulator_get_optional(dev, "vref"); 718 if (IS_ERR(adc->vref)) { 719 if (PTR_ERR(adc->vref) == -ENODEV) { 720 adc->vref = NULL; 721 } else { 722 return dev_err_probe(dev, PTR_ERR(adc->vref), "failed to get regulator\n"); 723 } 724 725 } else { 726 ret = regulator_enable(adc->vref); 727 if (ret) 728 return ret; 729 730 ret = devm_add_action_or_reset(dev, mcp3911_cleanup_regulator, adc->vref); 731 if (ret) 732 return ret; 733 } 734 735 adc->clki = devm_clk_get_enabled(dev, NULL); 736 if (IS_ERR(adc->clki)) { 737 if (PTR_ERR(adc->clki) == -ENOENT) { 738 adc->clki = NULL; 739 } else { 740 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n"); 741 } 742 } 743 744 /* 745 * Fallback to "device-addr" due to historical mismatch between 746 * dt-bindings and implementation. 747 */ 748 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 749 if (ret) 750 device_property_read_u32(dev, "device-addr", &adc->dev_addr); 751 if (adc->dev_addr > 3) { 752 return dev_err_probe(dev, -EINVAL, 753 "invalid device address (%i). Must be in range 0-3.\n", 754 adc->dev_addr); 755 } 756 dev_dbg(dev, "use device address %i\n", adc->dev_addr); 757 758 ret = adc->chip->config(adc); 759 if (ret) 760 return ret; 761 762 ret = mcp3911_calc_scale_table(adc); 763 if (ret) 764 return ret; 765 766 /* Set gain to 1 for all channels */ 767 for (int i = 0; i < adc->chip->num_channels - 1; i++) { 768 adc->gain[i] = 1; 769 ret = mcp3911_update(adc, MCP3911_REG_GAIN, 770 MCP3911_GAIN_MASK(i), 771 MCP3911_GAIN_VAL(i, 0), 1); 772 if (ret) 773 return ret; 774 } 775 776 indio_dev->name = spi_get_device_id(spi)->name; 777 indio_dev->modes = INDIO_DIRECT_MODE; 778 indio_dev->info = &mcp3911_info; 779 spi_set_drvdata(spi, indio_dev); 780 781 indio_dev->channels = adc->chip->channels; 782 indio_dev->num_channels = adc->chip->num_channels; 783 784 mutex_init(&adc->lock); 785 786 if (spi->irq > 0) { 787 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 788 iio_device_id(indio_dev)); 789 if (!adc->trig) 790 return -ENOMEM; 791 792 adc->trig->ops = &mcp3911_trigger_ops; 793 iio_trigger_set_drvdata(adc->trig, adc); 794 ret = devm_iio_trigger_register(dev, adc->trig); 795 if (ret) 796 return ret; 797 798 /* 799 * The device generates interrupts as long as it is powered up. 800 * Some platforms might not allow the option to power it down so 801 * don't enable the interrupt to avoid extra load on the system. 802 */ 803 ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll, 804 IRQF_NO_AUTOEN | IRQF_ONESHOT, 805 indio_dev->name, adc->trig); 806 if (ret) 807 return ret; 808 } 809 810 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 811 mcp3911_trigger_handler, NULL); 812 if (ret) 813 return ret; 814 815 return devm_iio_device_register(dev, indio_dev); 816} 817 818static const struct mcp3911_chip_info mcp3911_chip_info[] = { 819 [MCP3910] = { 820 .channels = mcp3910_channels, 821 .num_channels = ARRAY_SIZE(mcp3910_channels), 822 .config = mcp3910_config, 823 .get_osr = mcp3910_get_osr, 824 .set_osr = mcp3910_set_osr, 825 .enable_offset = mcp3910_enable_offset, 826 .get_offset = mcp3910_get_offset, 827 .set_offset = mcp3910_set_offset, 828 .set_scale = mcp3910_set_scale, 829 }, 830 [MCP3911] = { 831 .channels = mcp3911_channels, 832 .num_channels = ARRAY_SIZE(mcp3911_channels), 833 .config = mcp3911_config, 834 .get_osr = mcp3911_get_osr, 835 .set_osr = mcp3911_set_osr, 836 .enable_offset = mcp3911_enable_offset, 837 .get_offset = mcp3911_get_offset, 838 .set_offset = mcp3911_set_offset, 839 .set_scale = mcp3911_set_scale, 840 }, 841 [MCP3912] = { 842 .channels = mcp3912_channels, 843 .num_channels = ARRAY_SIZE(mcp3912_channels), 844 .config = mcp3910_config, 845 .get_osr = mcp3910_get_osr, 846 .set_osr = mcp3910_set_osr, 847 .enable_offset = mcp3910_enable_offset, 848 .get_offset = mcp3910_get_offset, 849 .set_offset = mcp3910_set_offset, 850 .set_scale = mcp3910_set_scale, 851 }, 852 [MCP3913] = { 853 .channels = mcp3913_channels, 854 .num_channels = ARRAY_SIZE(mcp3913_channels), 855 .config = mcp3910_config, 856 .get_osr = mcp3910_get_osr, 857 .set_osr = mcp3910_set_osr, 858 .enable_offset = mcp3910_enable_offset, 859 .get_offset = mcp3910_get_offset, 860 .set_offset = mcp3910_set_offset, 861 .set_scale = mcp3910_set_scale, 862 }, 863 [MCP3914] = { 864 .channels = mcp3914_channels, 865 .num_channels = ARRAY_SIZE(mcp3914_channels), 866 .config = mcp3910_config, 867 .get_osr = mcp3910_get_osr, 868 .set_osr = mcp3910_set_osr, 869 .enable_offset = mcp3910_enable_offset, 870 .get_offset = mcp3910_get_offset, 871 .set_offset = mcp3910_set_offset, 872 .set_scale = mcp3910_set_scale, 873 }, 874 [MCP3918] = { 875 .channels = mcp3918_channels, 876 .num_channels = ARRAY_SIZE(mcp3918_channels), 877 .config = mcp3910_config, 878 .get_osr = mcp3910_get_osr, 879 .set_osr = mcp3910_set_osr, 880 .enable_offset = mcp3910_enable_offset, 881 .get_offset = mcp3910_get_offset, 882 .set_offset = mcp3910_set_offset, 883 .set_scale = mcp3910_set_scale, 884 }, 885 [MCP3919] = { 886 .channels = mcp3919_channels, 887 .num_channels = ARRAY_SIZE(mcp3919_channels), 888 .config = mcp3910_config, 889 .get_osr = mcp3910_get_osr, 890 .set_osr = mcp3910_set_osr, 891 .enable_offset = mcp3910_enable_offset, 892 .get_offset = mcp3910_get_offset, 893 .set_offset = mcp3910_set_offset, 894 .set_scale = mcp3910_set_scale, 895 }, 896}; 897static const struct of_device_id mcp3911_dt_ids[] = { 898 { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] }, 899 { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] }, 900 { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] }, 901 { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] }, 902 { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] }, 903 { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] }, 904 { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] }, 905 { } 906}; 907MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); 908 909static const struct spi_device_id mcp3911_id[] = { 910 { "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] }, 911 { "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] }, 912 { "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] }, 913 { "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] }, 914 { "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] }, 915 { "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] }, 916 { "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] }, 917 { } 918}; 919MODULE_DEVICE_TABLE(spi, mcp3911_id); 920 921static struct spi_driver mcp3911_driver = { 922 .driver = { 923 .name = "mcp3911", 924 .of_match_table = mcp3911_dt_ids, 925 }, 926 .probe = mcp3911_probe, 927 .id_table = mcp3911_id, 928}; 929module_spi_driver(mcp3911_driver); 930 931MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>"); 932MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>"); 933MODULE_DESCRIPTION("Microchip Technology MCP3911"); 934MODULE_LICENSE("GPL v2"); 935