1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2021 Intel Corporation 4 */ 5 6#include "xe_pci.h" 7 8#include <kunit/static_stub.h> 9#include <linux/device/driver.h> 10#include <linux/module.h> 11#include <linux/pci.h> 12#include <linux/pm_runtime.h> 13 14#include <drm/drm_color_mgmt.h> 15#include <drm/drm_drv.h> 16#include <drm/xe_pciids.h> 17 18#include "display/xe_display.h" 19#include "regs/xe_gt_regs.h" 20#include "xe_device.h" 21#include "xe_drv.h" 22#include "xe_gt.h" 23#include "xe_macros.h" 24#include "xe_mmio.h" 25#include "xe_module.h" 26#include "xe_pci_types.h" 27#include "xe_pm.h" 28#include "xe_sriov.h" 29#include "xe_step.h" 30#include "xe_tile.h" 31 32enum toggle_d3cold { 33 D3COLD_DISABLE, 34 D3COLD_ENABLE, 35}; 36 37struct xe_subplatform_desc { 38 enum xe_subplatform subplatform; 39 const char *name; 40 const u16 *pciidlist; 41}; 42 43struct xe_gt_desc { 44 enum xe_gt_type type; 45 u32 mmio_adj_limit; 46 u32 mmio_adj_offset; 47}; 48 49struct xe_device_desc { 50 /* Should only ever be set for platforms without GMD_ID */ 51 const struct xe_graphics_desc *graphics; 52 /* Should only ever be set for platforms without GMD_ID */ 53 const struct xe_media_desc *media; 54 55 const char *platform_name; 56 const struct xe_subplatform_desc *subplatforms; 57 58 enum xe_platform platform; 59 60 u8 require_force_probe:1; 61 u8 is_dgfx:1; 62 63 u8 has_display:1; 64 u8 has_heci_gscfi:1; 65 u8 has_llc:1; 66 u8 has_mmio_ext:1; 67 u8 has_sriov:1; 68 u8 skip_guc_pc:1; 69 u8 skip_mtcfg:1; 70 u8 skip_pcode:1; 71}; 72 73__diag_push(); 74__diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 75 76#define PLATFORM(x) \ 77 .platform = (x), \ 78 .platform_name = #x 79 80#define NOP(x) x 81 82static const struct xe_graphics_desc graphics_xelp = { 83 .name = "Xe_LP", 84 .ver = 12, 85 .rel = 0, 86 87 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 88 89 .dma_mask_size = 39, 90 .va_bits = 48, 91 .vm_max_level = 3, 92}; 93 94static const struct xe_graphics_desc graphics_xelpp = { 95 .name = "Xe_LP+", 96 .ver = 12, 97 .rel = 10, 98 99 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 100 101 .dma_mask_size = 39, 102 .va_bits = 48, 103 .vm_max_level = 3, 104}; 105 106#define XE_HP_FEATURES \ 107 .has_range_tlb_invalidation = true, \ 108 .has_flat_ccs = true, \ 109 .dma_mask_size = 46, \ 110 .va_bits = 48, \ 111 .vm_max_level = 3 112 113static const struct xe_graphics_desc graphics_xehpg = { 114 .name = "Xe_HPG", 115 .ver = 12, 116 .rel = 55, 117 118 .hw_engine_mask = 119 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 120 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 121 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 122 123 XE_HP_FEATURES, 124 .vram_flags = XE_VRAM_FLAGS_NEED64K, 125}; 126 127static const struct xe_graphics_desc graphics_xehpc = { 128 .name = "Xe_HPC", 129 .ver = 12, 130 .rel = 60, 131 132 .hw_engine_mask = 133 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 134 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 135 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 136 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 137 BIT(XE_HW_ENGINE_BCS8) | 138 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 139 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 140 141 XE_HP_FEATURES, 142 .dma_mask_size = 52, 143 .max_remote_tiles = 1, 144 .va_bits = 57, 145 .vm_max_level = 4, 146 .vram_flags = XE_VRAM_FLAGS_NEED64K, 147 148 .has_asid = 1, 149 .has_flat_ccs = 0, 150 .has_usm = 1, 151}; 152 153static const struct xe_graphics_desc graphics_xelpg = { 154 .name = "Xe_LPG", 155 .hw_engine_mask = 156 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 157 BIT(XE_HW_ENGINE_CCS0), 158 159 XE_HP_FEATURES, 160 .has_flat_ccs = 0, 161}; 162 163#define XE2_GFX_FEATURES \ 164 .dma_mask_size = 46, \ 165 .has_asid = 1, \ 166 .has_flat_ccs = 1, \ 167 .has_range_tlb_invalidation = 1, \ 168 .has_usm = 1, \ 169 .va_bits = 48, \ 170 .vm_max_level = 4, \ 171 .hw_engine_mask = \ 172 BIT(XE_HW_ENGINE_RCS0) | \ 173 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 174 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 175 176static const struct xe_graphics_desc graphics_xe2 = { 177 .name = "Xe2_LPG", 178 179 XE2_GFX_FEATURES, 180}; 181 182static const struct xe_media_desc media_xem = { 183 .name = "Xe_M", 184 .ver = 12, 185 .rel = 0, 186 187 .hw_engine_mask = 188 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | 189 BIT(XE_HW_ENGINE_VECS0), 190}; 191 192static const struct xe_media_desc media_xehpm = { 193 .name = "Xe_HPM", 194 .ver = 12, 195 .rel = 55, 196 197 .hw_engine_mask = 198 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | 199 BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS1), 200}; 201 202static const struct xe_media_desc media_xelpmp = { 203 .name = "Xe_LPM+", 204 .hw_engine_mask = 205 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | 206 BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_GSCCS0) 207}; 208 209static const struct xe_media_desc media_xe2 = { 210 .name = "Xe2_LPM", 211 .hw_engine_mask = 212 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0), /* TODO: GSC0 */ 213}; 214 215static const struct xe_device_desc tgl_desc = { 216 .graphics = &graphics_xelp, 217 .media = &media_xem, 218 PLATFORM(XE_TIGERLAKE), 219 .has_display = true, 220 .has_llc = true, 221 .require_force_probe = true, 222}; 223 224static const struct xe_device_desc rkl_desc = { 225 .graphics = &graphics_xelp, 226 .media = &media_xem, 227 PLATFORM(XE_ROCKETLAKE), 228 .has_display = true, 229 .has_llc = true, 230 .require_force_probe = true, 231}; 232 233static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 }; 234 235static const struct xe_device_desc adl_s_desc = { 236 .graphics = &graphics_xelp, 237 .media = &media_xem, 238 PLATFORM(XE_ALDERLAKE_S), 239 .has_display = true, 240 .has_llc = true, 241 .require_force_probe = true, 242 .subplatforms = (const struct xe_subplatform_desc[]) { 243 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 244 {}, 245 }, 246}; 247 248static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 }; 249 250static const struct xe_device_desc adl_p_desc = { 251 .graphics = &graphics_xelp, 252 .media = &media_xem, 253 PLATFORM(XE_ALDERLAKE_P), 254 .has_display = true, 255 .has_llc = true, 256 .require_force_probe = true, 257 .subplatforms = (const struct xe_subplatform_desc[]) { 258 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 259 {}, 260 }, 261}; 262 263static const struct xe_device_desc adl_n_desc = { 264 .graphics = &graphics_xelp, 265 .media = &media_xem, 266 PLATFORM(XE_ALDERLAKE_N), 267 .has_display = true, 268 .has_llc = true, 269 .require_force_probe = true, 270}; 271 272#define DGFX_FEATURES \ 273 .is_dgfx = 1 274 275static const struct xe_device_desc dg1_desc = { 276 .graphics = &graphics_xelpp, 277 .media = &media_xem, 278 DGFX_FEATURES, 279 PLATFORM(XE_DG1), 280 .has_display = true, 281 .has_heci_gscfi = 1, 282 .require_force_probe = true, 283}; 284 285static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 }; 286static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 }; 287static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 }; 288 289#define DG2_FEATURES \ 290 DGFX_FEATURES, \ 291 PLATFORM(XE_DG2), \ 292 .has_heci_gscfi = 1, \ 293 .subplatforms = (const struct xe_subplatform_desc[]) { \ 294 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 295 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 296 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 297 { } \ 298 } 299 300static const struct xe_device_desc ats_m_desc = { 301 .graphics = &graphics_xehpg, 302 .media = &media_xehpm, 303 .require_force_probe = true, 304 305 DG2_FEATURES, 306 .has_display = false, 307}; 308 309static const struct xe_device_desc dg2_desc = { 310 .graphics = &graphics_xehpg, 311 .media = &media_xehpm, 312 .require_force_probe = true, 313 314 DG2_FEATURES, 315 .has_display = true, 316}; 317 318static const __maybe_unused struct xe_device_desc pvc_desc = { 319 .graphics = &graphics_xehpc, 320 DGFX_FEATURES, 321 PLATFORM(XE_PVC), 322 .has_display = false, 323 .has_heci_gscfi = 1, 324 .require_force_probe = true, 325}; 326 327static const struct xe_device_desc mtl_desc = { 328 /* .graphics and .media determined via GMD_ID */ 329 .require_force_probe = true, 330 PLATFORM(XE_METEORLAKE), 331 .has_display = true, 332}; 333 334static const struct xe_device_desc lnl_desc = { 335 PLATFORM(XE_LUNARLAKE), 336 .require_force_probe = true, 337}; 338 339#undef PLATFORM 340__diag_pop(); 341 342/* Map of GMD_ID values to graphics IP */ 343static const struct gmdid_map graphics_ip_map[] = { 344 { 1270, &graphics_xelpg }, 345 { 1271, &graphics_xelpg }, 346 { 2004, &graphics_xe2 }, 347}; 348 349/* Map of GMD_ID values to media IP */ 350static const struct gmdid_map media_ip_map[] = { 351 { 1300, &media_xelpmp }, 352 { 2000, &media_xe2 }, 353}; 354 355#define INTEL_VGA_DEVICE(id, info) { \ 356 PCI_DEVICE(PCI_VENDOR_ID_INTEL, id), \ 357 PCI_BASE_CLASS_DISPLAY << 16, 0xff << 16, \ 358 (unsigned long) info } 359 360/* 361 * Make sure any device matches here are from most specific to most 362 * general. For example, since the Quanta match is based on the subsystem 363 * and subvendor IDs, we need it to come before the more general IVB 364 * PCI ID matches, otherwise we'll use the wrong info struct above. 365 */ 366static const struct pci_device_id pciidlist[] = { 367 XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 368 XE_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 369 XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 370 XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 371 XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 372 XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 373 XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 374 XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 375 XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 376 XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 377 XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 378 XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 379 { } 380}; 381MODULE_DEVICE_TABLE(pci, pciidlist); 382 383#undef INTEL_VGA_DEVICE 384 385/* is device_id present in comma separated list of ids */ 386static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 387{ 388 char *s, *p, *tok; 389 bool ret; 390 391 if (!devices || !*devices) 392 return false; 393 394 /* match everything */ 395 if (negative && strcmp(devices, "!*") == 0) 396 return true; 397 if (!negative && strcmp(devices, "*") == 0) 398 return true; 399 400 s = kstrdup(devices, GFP_KERNEL); 401 if (!s) 402 return false; 403 404 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 405 u16 val; 406 407 if (negative && tok[0] == '!') 408 tok++; 409 else if ((negative && tok[0] != '!') || 410 (!negative && tok[0] == '!')) 411 continue; 412 413 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 414 ret = true; 415 break; 416 } 417 } 418 419 kfree(s); 420 421 return ret; 422} 423 424static bool id_forced(u16 device_id) 425{ 426 return device_id_in_list(device_id, xe_modparam.force_probe, false); 427} 428 429static bool id_blocked(u16 device_id) 430{ 431 return device_id_in_list(device_id, xe_modparam.force_probe, true); 432} 433 434static const struct xe_subplatform_desc * 435find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 436{ 437 const struct xe_subplatform_desc *sp; 438 const u16 *id; 439 440 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 441 for (id = sp->pciidlist; *id; id++) 442 if (*id == xe->info.devid) 443 return sp; 444 445 return NULL; 446} 447 448enum xe_gmdid_type { 449 GMDID_GRAPHICS, 450 GMDID_MEDIA 451}; 452 453static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 454{ 455 struct xe_gt *gt = xe_root_mmio_gt(xe); 456 struct xe_reg gmdid_reg = GMD_ID; 457 u32 val; 458 459 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 460 461 if (type == GMDID_MEDIA) 462 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 463 464 val = xe_mmio_read32(gt, gmdid_reg); 465 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 466 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 467} 468 469/* 470 * Pre-GMD_ID platform: device descriptor already points to the appropriate 471 * graphics descriptor. Simply forward the description and calculate the version 472 * appropriately. "graphics" should be present in all such platforms, while 473 * media is optional. 474 */ 475static void handle_pre_gmdid(struct xe_device *xe, 476 const struct xe_graphics_desc *graphics, 477 const struct xe_media_desc *media) 478{ 479 xe->info.graphics_verx100 = graphics->ver * 100 + graphics->rel; 480 481 if (media) 482 xe->info.media_verx100 = media->ver * 100 + media->rel; 483 484} 485 486/* 487 * GMD_ID platform: read IP version from hardware and select graphics descriptor 488 * based on the result. 489 */ 490static void handle_gmdid(struct xe_device *xe, 491 const struct xe_graphics_desc **graphics, 492 const struct xe_media_desc **media, 493 u32 *graphics_revid, 494 u32 *media_revid) 495{ 496 u32 ver; 497 498 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 499 500 for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) { 501 if (ver == graphics_ip_map[i].ver) { 502 xe->info.graphics_verx100 = ver; 503 *graphics = graphics_ip_map[i].ip; 504 505 break; 506 } 507 } 508 509 if (!xe->info.graphics_verx100) { 510 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 511 ver / 100, ver % 100); 512 } 513 514 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 515 516 /* Media may legitimately be fused off / not present */ 517 if (ver == 0) 518 return; 519 520 for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) { 521 if (ver == media_ip_map[i].ver) { 522 xe->info.media_verx100 = ver; 523 *media = media_ip_map[i].ip; 524 525 break; 526 } 527 } 528 529 if (!xe->info.media_verx100) { 530 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 531 ver / 100, ver % 100); 532 } 533} 534 535/* 536 * Initialize device info content that only depends on static driver_data 537 * passed to the driver at probe time from PCI ID table. 538 */ 539static int xe_info_init_early(struct xe_device *xe, 540 const struct xe_device_desc *desc, 541 const struct xe_subplatform_desc *subplatform_desc) 542{ 543 int err; 544 545 xe->info.platform = desc->platform; 546 xe->info.subplatform = subplatform_desc ? 547 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 548 549 xe->info.is_dgfx = desc->is_dgfx; 550 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 551 xe->info.has_llc = desc->has_llc; 552 xe->info.has_mmio_ext = desc->has_mmio_ext; 553 xe->info.has_sriov = desc->has_sriov; 554 xe->info.skip_guc_pc = desc->skip_guc_pc; 555 xe->info.skip_mtcfg = desc->skip_mtcfg; 556 xe->info.skip_pcode = desc->skip_pcode; 557 558 xe->info.enable_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 559 xe_modparam.enable_display && 560 desc->has_display; 561 562 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 563 if (err) 564 return err; 565 566 return 0; 567} 568 569/* 570 * Initialize device info content that does require knowledge about 571 * graphics / media IP version. 572 * Make sure that GT / tile structures allocated by the driver match the data 573 * present in device info. 574 */ 575static int xe_info_init(struct xe_device *xe, 576 const struct xe_graphics_desc *graphics_desc, 577 const struct xe_media_desc *media_desc) 578{ 579 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 580 struct xe_tile *tile; 581 struct xe_gt *gt; 582 u8 id; 583 584 /* 585 * If this platform supports GMD_ID, we'll detect the proper IP 586 * descriptor to use from hardware registers. desc->graphics will only 587 * ever be set at this point for platforms before GMD_ID. In that case 588 * the IP descriptions and versions are simply derived from that. 589 */ 590 if (graphics_desc) { 591 handle_pre_gmdid(xe, graphics_desc, media_desc); 592 xe->info.step = xe_step_pre_gmdid_get(xe); 593 } else { 594 xe_assert(xe, !media_desc); 595 handle_gmdid(xe, &graphics_desc, &media_desc, 596 &graphics_gmdid_revid, &media_gmdid_revid); 597 xe->info.step = xe_step_gmdid_get(xe, 598 graphics_gmdid_revid, 599 media_gmdid_revid); 600 } 601 602 /* 603 * If we couldn't detect the graphics IP, that's considered a fatal 604 * error and we should abort driver load. Failing to detect media 605 * IP is non-fatal; we'll just proceed without enabling media support. 606 */ 607 if (!graphics_desc) 608 return -ENODEV; 609 610 xe->info.graphics_name = graphics_desc->name; 611 xe->info.media_name = media_desc ? media_desc->name : "none"; 612 xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size; 613 614 xe->info.dma_mask_size = graphics_desc->dma_mask_size; 615 xe->info.vram_flags = graphics_desc->vram_flags; 616 xe->info.va_bits = graphics_desc->va_bits; 617 xe->info.vm_max_level = graphics_desc->vm_max_level; 618 xe->info.has_asid = graphics_desc->has_asid; 619 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 620 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation; 621 xe->info.has_usm = graphics_desc->has_usm; 622 623 /* 624 * All platforms have at least one primary GT. Any platform with media 625 * version 13 or higher has an additional dedicated media GT. And 626 * depending on the graphics IP there may be additional "remote tiles." 627 * All of these together determine the overall GT count. 628 * 629 * FIXME: 'tile_count' here is misnamed since the rest of the driver 630 * treats it as the number of GTs rather than just the number of tiles. 631 */ 632 xe->info.tile_count = 1 + graphics_desc->max_remote_tiles; 633 634 for_each_remote_tile(tile, xe, id) { 635 int err; 636 637 err = xe_tile_init_early(tile, xe, id); 638 if (err) 639 return err; 640 } 641 642 for_each_tile(tile, xe, id) { 643 gt = tile->primary_gt; 644 gt->info.id = xe->info.gt_count++; 645 gt->info.type = XE_GT_TYPE_MAIN; 646 gt->info.__engine_mask = graphics_desc->hw_engine_mask; 647 if (MEDIA_VER(xe) < 13 && media_desc) 648 gt->info.__engine_mask |= media_desc->hw_engine_mask; 649 650 if (MEDIA_VER(xe) < 13 || !media_desc) 651 continue; 652 653 /* 654 * Allocate and setup media GT for platforms with standalone 655 * media. 656 */ 657 tile->media_gt = xe_gt_alloc(tile); 658 if (IS_ERR(tile->media_gt)) 659 return PTR_ERR(tile->media_gt); 660 661 gt = tile->media_gt; 662 gt->info.type = XE_GT_TYPE_MEDIA; 663 gt->info.__engine_mask = media_desc->hw_engine_mask; 664 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 665 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 666 667 /* 668 * FIXME: At the moment multi-tile and standalone media are 669 * mutually exclusive on current platforms. We'll need to 670 * come up with a better way to number GTs if we ever wind 671 * up with platforms that support both together. 672 */ 673 drm_WARN_ON(&xe->drm, id != 0); 674 gt->info.id = xe->info.gt_count++; 675 } 676 677 return 0; 678} 679 680static void xe_pci_remove(struct pci_dev *pdev) 681{ 682 struct xe_device *xe; 683 684 xe = pci_get_drvdata(pdev); 685 if (!xe) /* driver load aborted, nothing to cleanup */ 686 return; 687 688 xe_device_remove(xe); 689 xe_pm_runtime_fini(xe); 690 pci_set_drvdata(pdev, NULL); 691} 692 693static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 694{ 695 const struct xe_device_desc *desc = (const void *)ent->driver_data; 696 const struct xe_subplatform_desc *subplatform_desc; 697 struct xe_device *xe; 698 int err; 699 700 if (desc->require_force_probe && !id_forced(pdev->device)) { 701 dev_info(&pdev->dev, 702 "Your graphics device %04x is not officially supported\n" 703 "by xe driver in this kernel version. To force Xe probe,\n" 704 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 705 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 706 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 707 pdev->device, pdev->device, pdev->device, 708 pdev->device, pdev->device); 709 return -ENODEV; 710 } 711 712 if (id_blocked(pdev->device)) { 713 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 714 pdev->vendor, pdev->device); 715 return -ENODEV; 716 } 717 718 if (xe_display_driver_probe_defer(pdev)) 719 return -EPROBE_DEFER; 720 721 err = pcim_enable_device(pdev); 722 if (err) 723 return err; 724 725 xe = xe_device_create(pdev, ent); 726 if (IS_ERR(xe)) 727 return PTR_ERR(xe); 728 729 pci_set_drvdata(pdev, xe); 730 731 xe_pm_assert_unbounded_bridge(xe); 732 subplatform_desc = find_subplatform(xe, desc); 733 734 pci_set_master(pdev); 735 736 err = xe_info_init_early(xe, desc, subplatform_desc); 737 if (err) 738 return err; 739 740 xe_sriov_probe_early(xe, desc->has_sriov); 741 742 err = xe_device_probe_early(xe); 743 if (err) 744 return err; 745 746 err = xe_info_init(xe, desc->graphics, desc->media); 747 if (err) 748 return err; 749 750 xe_display_probe(xe); 751 752 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d", 753 desc->platform_name, 754 subplatform_desc ? subplatform_desc->name : "", 755 xe->info.devid, xe->info.revid, 756 xe->info.is_dgfx, 757 xe->info.graphics_name, 758 xe->info.graphics_verx100 / 100, 759 xe->info.graphics_verx100 % 100, 760 xe->info.media_name, 761 xe->info.media_verx100 / 100, 762 xe->info.media_verx100 % 100, 763 str_yes_no(xe->info.enable_display), 764 xe->info.dma_mask_size, xe->info.tile_count, 765 xe->info.has_heci_gscfi); 766 767 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n", 768 xe_step_name(xe->info.step.graphics), 769 xe_step_name(xe->info.step.media), 770 xe_step_name(xe->info.step.display), 771 xe_step_name(xe->info.step.basedie)); 772 773 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 774 str_yes_no(xe_device_has_sriov(xe)), 775 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 776 777 xe_pm_init_early(xe); 778 779 err = xe_device_probe(xe); 780 if (err) 781 return err; 782 783 xe_pm_init(xe); 784 785 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 786 str_yes_no(xe->d3cold.capable)); 787 788 return 0; 789} 790 791static void xe_pci_shutdown(struct pci_dev *pdev) 792{ 793 xe_device_shutdown(pdev_to_xe_device(pdev)); 794} 795 796#ifdef CONFIG_PM_SLEEP 797static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 798{ 799 struct xe_device *xe = pdev_to_xe_device(pdev); 800 struct pci_dev *root_pdev; 801 802 if (!xe->d3cold.capable) 803 return; 804 805 root_pdev = pcie_find_root_port(pdev); 806 if (!root_pdev) 807 return; 808 809 switch (toggle) { 810 case D3COLD_DISABLE: 811 pci_d3cold_disable(root_pdev); 812 break; 813 case D3COLD_ENABLE: 814 pci_d3cold_enable(root_pdev); 815 break; 816 } 817} 818 819static int xe_pci_suspend(struct device *dev) 820{ 821 struct pci_dev *pdev = to_pci_dev(dev); 822 int err; 823 824 err = xe_pm_suspend(pdev_to_xe_device(pdev)); 825 if (err) 826 return err; 827 828 /* 829 * Enabling D3Cold is needed for S2Idle/S0ix. 830 * It is save to allow here since xe_pm_suspend has evicted 831 * the local memory and the direct complete optimization is disabled. 832 */ 833 d3cold_toggle(pdev, D3COLD_ENABLE); 834 835 pci_save_state(pdev); 836 pci_disable_device(pdev); 837 838 return 0; 839} 840 841static int xe_pci_resume(struct device *dev) 842{ 843 struct pci_dev *pdev = to_pci_dev(dev); 844 int err; 845 846 /* Give back the D3Cold decision to the runtime P M*/ 847 d3cold_toggle(pdev, D3COLD_DISABLE); 848 849 err = pci_set_power_state(pdev, PCI_D0); 850 if (err) 851 return err; 852 853 err = pci_enable_device(pdev); 854 if (err) 855 return err; 856 857 pci_set_master(pdev); 858 859 err = xe_pm_resume(pdev_to_xe_device(pdev)); 860 if (err) 861 return err; 862 863 return 0; 864} 865 866static int xe_pci_runtime_suspend(struct device *dev) 867{ 868 struct pci_dev *pdev = to_pci_dev(dev); 869 struct xe_device *xe = pdev_to_xe_device(pdev); 870 int err; 871 872 err = xe_pm_runtime_suspend(xe); 873 if (err) 874 return err; 875 876 pci_save_state(pdev); 877 878 if (xe->d3cold.allowed) { 879 d3cold_toggle(pdev, D3COLD_ENABLE); 880 pci_disable_device(pdev); 881 pci_ignore_hotplug(pdev); 882 pci_set_power_state(pdev, PCI_D3cold); 883 } else { 884 d3cold_toggle(pdev, D3COLD_DISABLE); 885 pci_set_power_state(pdev, PCI_D3hot); 886 } 887 888 return 0; 889} 890 891static int xe_pci_runtime_resume(struct device *dev) 892{ 893 struct pci_dev *pdev = to_pci_dev(dev); 894 struct xe_device *xe = pdev_to_xe_device(pdev); 895 int err; 896 897 err = pci_set_power_state(pdev, PCI_D0); 898 if (err) 899 return err; 900 901 pci_restore_state(pdev); 902 903 if (xe->d3cold.allowed) { 904 err = pci_enable_device(pdev); 905 if (err) 906 return err; 907 908 pci_set_master(pdev); 909 } 910 911 return xe_pm_runtime_resume(xe); 912} 913 914static int xe_pci_runtime_idle(struct device *dev) 915{ 916 struct pci_dev *pdev = to_pci_dev(dev); 917 struct xe_device *xe = pdev_to_xe_device(pdev); 918 919 xe_pm_d3cold_allowed_toggle(xe); 920 921 return 0; 922} 923 924static const struct dev_pm_ops xe_pm_ops = { 925 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 926 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 927}; 928#endif 929 930static struct pci_driver xe_pci_driver = { 931 .name = DRIVER_NAME, 932 .id_table = pciidlist, 933 .probe = xe_pci_probe, 934 .remove = xe_pci_remove, 935 .shutdown = xe_pci_shutdown, 936#ifdef CONFIG_PM_SLEEP 937 .driver.pm = &xe_pm_ops, 938#endif 939}; 940 941int xe_register_pci_driver(void) 942{ 943 return pci_register_driver(&xe_pci_driver); 944} 945 946void xe_unregister_pci_driver(void) 947{ 948 pci_unregister_driver(&xe_pci_driver); 949} 950 951#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 952#include "tests/xe_pci.c" 953#endif 954