1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright �� 2022 Intel Corporation
4 */
5
6#ifndef _XE_GUC_TYPES_H_
7#define _XE_GUC_TYPES_H_
8
9#include <linux/idr.h>
10#include <linux/xarray.h>
11
12#include "regs/xe_reg_defs.h"
13#include "xe_guc_ads_types.h"
14#include "xe_guc_ct_types.h"
15#include "xe_guc_fwif.h"
16#include "xe_guc_log_types.h"
17#include "xe_guc_pc_types.h"
18#include "xe_guc_relay_types.h"
19#include "xe_uc_fw_types.h"
20
21/**
22 * struct xe_guc_db_mgr - GuC Doorbells Manager.
23 *
24 * Note: GuC Doorbells Manager is relying on &xe_guc::submission_state.lock
25 * to protect its members.
26 */
27struct xe_guc_db_mgr {
28	/** @count: number of doorbells to manage */
29	unsigned int count;
30	/** @bitmap: bitmap to track allocated doorbells */
31	unsigned long *bitmap;
32};
33
34/**
35 * struct xe_guc - Graphic micro controller
36 */
37struct xe_guc {
38	/** @fw: Generic uC firmware management */
39	struct xe_uc_fw fw;
40	/** @log: GuC log */
41	struct xe_guc_log log;
42	/** @ads: GuC ads */
43	struct xe_guc_ads ads;
44	/** @ct: GuC ct */
45	struct xe_guc_ct ct;
46	/** @pc: GuC Power Conservation */
47	struct xe_guc_pc pc;
48	/** @dbm: GuC Doorbell Manager */
49	struct xe_guc_db_mgr dbm;
50	/** @submission_state: GuC submission state */
51	struct {
52		/** @submission_state.exec_queue_lookup: Lookup an xe_engine from guc_id */
53		struct xarray exec_queue_lookup;
54		/** @submission_state.guc_ids: used to allocate new guc_ids, single-lrc */
55		struct ida guc_ids;
56		/** @submission_state.guc_ids_bitmap: used to allocate new guc_ids, multi-lrc */
57		unsigned long *guc_ids_bitmap;
58		/** @submission_state.stopped: submissions are stopped */
59		atomic_t stopped;
60		/** @submission_state.lock: protects submission state */
61		struct mutex lock;
62		/** @submission_state.suspend: suspend fence state */
63		struct {
64			/** @submission_state.suspend.lock: suspend fences lock */
65			spinlock_t lock;
66			/** @submission_state.suspend.context: suspend fences context */
67			u64 context;
68			/** @submission_state.suspend.seqno: suspend fences seqno */
69			u32 seqno;
70		} suspend;
71#ifdef CONFIG_PROVE_LOCKING
72#define NUM_SUBMIT_WQ	256
73		/** @submission_state.submit_wq_pool: submission ordered workqueues pool */
74		struct workqueue_struct *submit_wq_pool[NUM_SUBMIT_WQ];
75		/** @submission_state.submit_wq_idx: submission ordered workqueue index */
76		int submit_wq_idx;
77#endif
78		/** @submission_state.enabled: submission is enabled */
79		bool enabled;
80	} submission_state;
81	/** @hwconfig: Hardware config state */
82	struct {
83		/** @hwconfig.bo: buffer object of the hardware config */
84		struct xe_bo *bo;
85		/** @hwconfig.size: size of the hardware config */
86		u32 size;
87	} hwconfig;
88
89	/** @relay: GuC Relay Communication used in SR-IOV */
90	struct xe_guc_relay relay;
91
92	/**
93	 * @notify_reg: Register which is written to notify GuC of H2G messages
94	 */
95	struct xe_reg notify_reg;
96	/** @params: Control params for fw initialization */
97	u32 params[GUC_CTL_MAX_DWORDS];
98};
99
100#endif
101