1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5 */
6
7#ifndef _STI_HDMI_H_
8#define _STI_HDMI_H_
9
10#include <linux/hdmi.h>
11#include <linux/platform_device.h>
12
13#include <media/cec-notifier.h>
14
15#include <drm/drm_modes.h>
16#include <drm/drm_property.h>
17
18#define HDMI_STA           0x0010
19#define HDMI_STA_DLL_LCK   BIT(5)
20#define HDMI_STA_HOT_PLUG  BIT(4)
21
22struct sti_hdmi;
23
24struct hdmi_phy_ops {
25	bool (*start)(struct sti_hdmi *hdmi);
26	void (*stop)(struct sti_hdmi *hdmi);
27};
28
29struct hdmi_audio_params {
30	bool enabled;
31	unsigned int sample_width;
32	unsigned int sample_rate;
33	struct hdmi_audio_infoframe cea;
34};
35
36#define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB
37
38/**
39 * STI hdmi structure
40 *
41 * @dev: driver device
42 * @drm_dev: pointer to drm device
43 * @mode: current display mode selected
44 * @regs: hdmi register
45 * @syscfg: syscfg register for pll rejection configuration
46 * @clk_pix: hdmi pixel clock
47 * @clk_tmds: hdmi tmds clock
48 * @clk_phy: hdmi phy clock
49 * @clk_audio: hdmi audio clock
50 * @irq: hdmi interrupt number
51 * @irq_status: interrupt status register
52 * @phy_ops: phy start/stop operations
53 * @enabled: true if hdmi is enabled else false
54 * @hpd: hot plug detect status
55 * @wait_event: wait event
56 * @event_received: wait event status
57 * @reset: reset control of the hdmi phy
58 * @ddc_adapt: i2c ddc adapter
59 * @colorspace: current colorspace selected
60 * @audio_pdev: ASoC hdmi-codec platform device
61 * @audio: hdmi audio parameters.
62 * @drm_connector: hdmi connector
63 * @notifier: hotplug detect notifier
64 */
65struct sti_hdmi {
66	struct device dev;
67	struct drm_device *drm_dev;
68	struct drm_display_mode mode;
69	void __iomem *regs;
70	void __iomem *syscfg;
71	struct clk *clk_pix;
72	struct clk *clk_tmds;
73	struct clk *clk_phy;
74	struct clk *clk_audio;
75	int irq;
76	u32 irq_status;
77	struct hdmi_phy_ops *phy_ops;
78	bool enabled;
79	bool hpd;
80	wait_queue_head_t wait_event;
81	bool event_received;
82	struct reset_control *reset;
83	struct i2c_adapter *ddc_adapt;
84	enum hdmi_colorspace colorspace;
85	struct platform_device *audio_pdev;
86	struct hdmi_audio_params audio;
87	struct drm_connector *drm_connector;
88	struct cec_notifier *notifier;
89};
90
91u32 hdmi_read(struct sti_hdmi *hdmi, int offset);
92void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset);
93
94/**
95 * hdmi phy config structure
96 *
97 * A pointer to an array of these structures is passed to a TMDS (HDMI) output
98 * via the control interface to provide board and SoC specific
99 * configurations of the HDMI PHY. Each entry in the array specifies a hardware
100 * specific configuration for a given TMDS clock frequency range.
101 *
102 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
103 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to
104 * @config: SoC specific register configuration
105 */
106struct hdmi_phy_config {
107	u32 min_tmds_freq;
108	u32 max_tmds_freq;
109	u32 config[4];
110};
111
112#endif
113