11. stiH display hardware IP
2---------------------------
3The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
4- The High Quality Video Display Processor (HQVDP) gets video frames from a
5  video decoder and does high quality video processing, including scaling.
6
7- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
8  has several inputs:
9  - The graphics planes are internally processed by the Generic Display
10    Pipeline (GDP).
11  - The video plug (VID) connects to the HQVDP output.
12  - The cursor handles ... a cursor.
13- The TV OUT pre-formats (convert, clip, round) the compositor output data
14- The HDMI / DVO / HD Analog / SD analog IP builds the video signals
15  - DVO (Digital Video Output) handles a 24bits parallel signal
16  - The HD analog signal is typically driven by a YCbCr cable, supporting up to
17    1080i mode.
18  - The SD analog signal is typically used for legacy TV
19- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
20Note that some stiH drivers support only a subset of thee HW IP.
21
22                  .-------------.   .-----------.   .-----------.
23GPU >-------------+GDP     Main |   |           +---+    HDMI   +--> HDMI
24GPU >-------------+GDP     mixer+---+           |   :===========:
25GPU >-------------+Cursor       |   |           +---+    DVO    +--> 24b//
26        -------   |  COMPOSITOR |   |  TV OUT   |   :===========:
27       |       |  |             |   |           +---+ HD analog +--> YCbCr
28Vid >--+ HQVDP +--+VID     Aux  +---+           |   :===========:
29dec    |       |  |        mixer|   |           +---+ SD analog +--> CVBS
30       '-------'  '-------------'   '-----------'   '-----------'
31                   .-----------.
32                   |       main+--> Vsync
33                   | VTG       |
34                   |        aux+--> Vsync
35                   '-----------'
36
372. DRM / HW mapping
38-------------------
39These IP are mapped to the DRM objects as following:
40- The CRTCs are mapped to the Compositor Main and Aux Mixers
41- The Framebuffers and planes are mapped to the Compositor GDP (non video
42  buffers) and to HQVDP+VID (video buffers)
43- The Cursor is mapped to the Compositor Cursor
44- The Encoders are mapped to the TVOut
45- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
46
47FB & planes         Cursor      CRTC     Encoders    Bridges/Connectors
48   |                   |          |         |                       |
49   |                   |          |         |                       |
50   |              .-------------. | .-----------.   .-----------.   |
51   +------------> |GDP |   Main | | |       +-> |   |    HDMI   | <-+
52   +------------> |GDP v   mixer|<+ |       |   |   :===========:   |
53   |              |Cursor       | | |       +-> |   |    DVO    | <-+
54   |    -------   |  COMPOSITOR | | |TV OUT |   |   :===========:   |
55   |   |       |  |             | | |       +-> |   | HD analog | <-+
56   +-> | HQVDP |  |VID     Aux  |<+ |       |   |   :===========:   |
57       |       |  |        mixer|   |       +-> |   | SD analog | <-+
58       '-------'  '-------------'   '-----------'   '-----------'
59