1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7#ifndef _ROCKCHIP_DRM_VOP2_H 8#define _ROCKCHIP_DRM_VOP2_H 9 10#include <linux/regmap.h> 11#include <drm/drm_modes.h> 12#include "rockchip_drm_vop.h" 13 14#define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0) 15 16#define VOP2_FEATURE_HAS_SYS_GRF BIT(0) 17#define VOP2_FEATURE_HAS_VO0_GRF BIT(1) 18#define VOP2_FEATURE_HAS_VO1_GRF BIT(2) 19#define VOP2_FEATURE_HAS_VOP_GRF BIT(3) 20#define VOP2_FEATURE_HAS_SYS_PMU BIT(4) 21 22#define WIN_FEATURE_AFBDC BIT(0) 23#define WIN_FEATURE_CLUSTER BIT(1) 24 25#define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) 26/* 27 * the delay number of a window in different mode. 28 */ 29enum win_dly_mode { 30 VOP2_DLY_MODE_DEFAULT, /**< default mode */ 31 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ 32 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ 33 VOP2_DLY_MODE_MAX, 34}; 35 36enum vop2_scale_up_mode { 37 VOP2_SCALE_UP_NRST_NBOR, 38 VOP2_SCALE_UP_BIL, 39 VOP2_SCALE_UP_BIC, 40}; 41 42enum vop2_scale_down_mode { 43 VOP2_SCALE_DOWN_NRST_NBOR, 44 VOP2_SCALE_DOWN_BIL, 45 VOP2_SCALE_DOWN_AVG, 46}; 47 48/* 49 * vop2 internal power domain id, 50 * should be all none zero, 0 will be treat as invalid; 51 */ 52#define VOP2_PD_CLUSTER0 BIT(0) 53#define VOP2_PD_CLUSTER1 BIT(1) 54#define VOP2_PD_CLUSTER2 BIT(2) 55#define VOP2_PD_CLUSTER3 BIT(3) 56#define VOP2_PD_DSC_8K BIT(5) 57#define VOP2_PD_DSC_4K BIT(6) 58#define VOP2_PD_ESMART BIT(7) 59 60enum vop2_win_regs { 61 VOP2_WIN_ENABLE, 62 VOP2_WIN_FORMAT, 63 VOP2_WIN_CSC_MODE, 64 VOP2_WIN_XMIRROR, 65 VOP2_WIN_YMIRROR, 66 VOP2_WIN_RB_SWAP, 67 VOP2_WIN_UV_SWAP, 68 VOP2_WIN_ACT_INFO, 69 VOP2_WIN_DSP_INFO, 70 VOP2_WIN_DSP_ST, 71 VOP2_WIN_YRGB_MST, 72 VOP2_WIN_UV_MST, 73 VOP2_WIN_YRGB_VIR, 74 VOP2_WIN_UV_VIR, 75 VOP2_WIN_YUV_CLIP, 76 VOP2_WIN_Y2R_EN, 77 VOP2_WIN_R2Y_EN, 78 VOP2_WIN_COLOR_KEY, 79 VOP2_WIN_COLOR_KEY_EN, 80 VOP2_WIN_DITHER_UP, 81 82 /* scale regs */ 83 VOP2_WIN_SCALE_YRGB_X, 84 VOP2_WIN_SCALE_YRGB_Y, 85 VOP2_WIN_SCALE_CBCR_X, 86 VOP2_WIN_SCALE_CBCR_Y, 87 VOP2_WIN_YRGB_HOR_SCL_MODE, 88 VOP2_WIN_YRGB_HSCL_FILTER_MODE, 89 VOP2_WIN_YRGB_VER_SCL_MODE, 90 VOP2_WIN_YRGB_VSCL_FILTER_MODE, 91 VOP2_WIN_CBCR_VER_SCL_MODE, 92 VOP2_WIN_CBCR_HSCL_FILTER_MODE, 93 VOP2_WIN_CBCR_HOR_SCL_MODE, 94 VOP2_WIN_CBCR_VSCL_FILTER_MODE, 95 VOP2_WIN_VSD_CBCR_GT2, 96 VOP2_WIN_VSD_CBCR_GT4, 97 VOP2_WIN_VSD_YRGB_GT2, 98 VOP2_WIN_VSD_YRGB_GT4, 99 VOP2_WIN_BIC_COE_SEL, 100 101 /* cluster regs */ 102 VOP2_WIN_CLUSTER_ENABLE, 103 VOP2_WIN_AFBC_ENABLE, 104 VOP2_WIN_CLUSTER_LB_MODE, 105 106 /* afbc regs */ 107 VOP2_WIN_AFBC_FORMAT, 108 VOP2_WIN_AFBC_RB_SWAP, 109 VOP2_WIN_AFBC_UV_SWAP, 110 VOP2_WIN_AFBC_AUTO_GATING_EN, 111 VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 112 VOP2_WIN_AFBC_PIC_VIR_WIDTH, 113 VOP2_WIN_AFBC_TILE_NUM, 114 VOP2_WIN_AFBC_PIC_OFFSET, 115 VOP2_WIN_AFBC_PIC_SIZE, 116 VOP2_WIN_AFBC_DSP_OFFSET, 117 VOP2_WIN_AFBC_TRANSFORM_OFFSET, 118 VOP2_WIN_AFBC_HDR_PTR, 119 VOP2_WIN_AFBC_HALF_BLOCK_EN, 120 VOP2_WIN_AFBC_ROTATE_270, 121 VOP2_WIN_AFBC_ROTATE_90, 122 VOP2_WIN_MAX_REG, 123}; 124 125struct vop2_win_data { 126 const char *name; 127 unsigned int phys_id; 128 129 u32 base; 130 enum drm_plane_type type; 131 132 u32 nformats; 133 const u32 *formats; 134 const uint64_t *format_modifiers; 135 const unsigned int supported_rotations; 136 137 /** 138 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 139 */ 140 unsigned int layer_sel_id; 141 uint64_t feature; 142 143 unsigned int max_upscale_factor; 144 unsigned int max_downscale_factor; 145 const u8 dly[VOP2_DLY_MODE_MAX]; 146}; 147 148struct vop2_video_port_data { 149 unsigned int id; 150 u32 feature; 151 u16 gamma_lut_len; 152 u16 cubic_lut_len; 153 struct vop_rect max_output; 154 const u8 pre_scan_max_dly[4]; 155 unsigned int offset; 156}; 157 158struct vop2_data { 159 u8 nr_vps; 160 u64 feature; 161 const struct vop2_win_data *win; 162 const struct vop2_video_port_data *vp; 163 struct vop_rect max_input; 164 struct vop_rect max_output; 165 166 unsigned int win_size; 167 unsigned int soc_id; 168}; 169 170/* interrupt define */ 171#define FS_NEW_INTR BIT(4) 172#define ADDR_SAME_INTR BIT(5) 173#define LINE_FLAG1_INTR BIT(6) 174#define WIN0_EMPTY_INTR BIT(7) 175#define WIN1_EMPTY_INTR BIT(8) 176#define WIN2_EMPTY_INTR BIT(9) 177#define WIN3_EMPTY_INTR BIT(10) 178#define HWC_EMPTY_INTR BIT(11) 179#define POST_BUF_EMPTY_INTR BIT(12) 180#define PWM_GEN_INTR BIT(13) 181#define DMA_FINISH_INTR BIT(14) 182#define FS_FIELD_INTR BIT(15) 183#define FE_INTR BIT(16) 184#define WB_UV_FIFO_FULL_INTR BIT(17) 185#define WB_YRGB_FIFO_FULL_INTR BIT(18) 186#define WB_COMPLETE_INTR BIT(19) 187 188 189enum vop_csc_format { 190 CSC_BT601L, 191 CSC_BT709L, 192 CSC_BT601F, 193 CSC_BT2020, 194}; 195 196enum src_factor_mode { 197 SRC_FAC_ALPHA_ZERO, 198 SRC_FAC_ALPHA_ONE, 199 SRC_FAC_ALPHA_DST, 200 SRC_FAC_ALPHA_DST_INVERSE, 201 SRC_FAC_ALPHA_SRC, 202 SRC_FAC_ALPHA_SRC_GLOBAL, 203}; 204 205enum dst_factor_mode { 206 DST_FAC_ALPHA_ZERO, 207 DST_FAC_ALPHA_ONE, 208 DST_FAC_ALPHA_SRC, 209 DST_FAC_ALPHA_SRC_INVERSE, 210 DST_FAC_ALPHA_DST, 211 DST_FAC_ALPHA_DST_GLOBAL, 212}; 213 214#define RK3568_GRF_VO_CON1 0x0364 215 216#define RK3588_GRF_SOC_CON1 0x0304 217#define RK3588_GRF_VOP_CON2 0x08 218#define RK3588_GRF_VO1_CON0 0x00 219 220/* System registers definition */ 221#define RK3568_REG_CFG_DONE 0x000 222#define RK3568_VERSION_INFO 0x004 223#define RK3568_SYS_AUTO_GATING_CTRL 0x008 224#define RK3568_SYS_AXI_LUT_CTRL 0x024 225#define RK3568_DSP_IF_EN 0x028 226#define RK3568_DSP_IF_CTRL 0x02c 227#define RK3568_DSP_IF_POL 0x030 228#define RK3588_SYS_PD_CTRL 0x034 229#define RK3568_WB_CTRL 0x40 230#define RK3568_WB_XSCAL_FACTOR 0x44 231#define RK3568_WB_YRGB_MST 0x48 232#define RK3568_WB_CBR_MST 0x4C 233#define RK3568_OTP_WIN_EN 0x050 234#define RK3568_LUT_PORT_SEL 0x058 235#define RK3568_SYS_STATUS0 0x060 236#define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) 237#define RK3568_SYS0_INT_EN 0x80 238#define RK3568_SYS0_INT_CLR 0x84 239#define RK3568_SYS0_INT_STATUS 0x88 240#define RK3568_SYS1_INT_EN 0x90 241#define RK3568_SYS1_INT_CLR 0x94 242#define RK3568_SYS1_INT_STATUS 0x98 243#define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) 244#define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) 245#define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) 246#define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) 247 248/* Video Port registers definition */ 249#define RK3568_VP0_CTRL_BASE 0x0C00 250#define RK3568_VP1_CTRL_BASE 0x0D00 251#define RK3568_VP2_CTRL_BASE 0x0E00 252#define RK3588_VP3_CTRL_BASE 0x0F00 253#define RK3568_VP_DSP_CTRL 0x00 254#define RK3568_VP_MIPI_CTRL 0x04 255#define RK3568_VP_COLOR_BAR_CTRL 0x08 256#define RK3588_VP_CLK_CTRL 0x0C 257#define RK3568_VP_3D_LUT_CTRL 0x10 258#define RK3568_VP_3D_LUT_MST 0x20 259#define RK3568_VP_DSP_BG 0x2C 260#define RK3568_VP_PRE_SCAN_HTIMING 0x30 261#define RK3568_VP_POST_DSP_HACT_INFO 0x34 262#define RK3568_VP_POST_DSP_VACT_INFO 0x38 263#define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C 264#define RK3568_VP_POST_SCL_CTRL 0x40 265#define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 266#define RK3568_VP_DSP_HTOTAL_HS_END 0x48 267#define RK3568_VP_DSP_HACT_ST_END 0x4C 268#define RK3568_VP_DSP_VTOTAL_VS_END 0x50 269#define RK3568_VP_DSP_VACT_ST_END 0x54 270#define RK3568_VP_DSP_VS_ST_END_F1 0x58 271#define RK3568_VP_DSP_VACT_ST_END_F1 0x5C 272#define RK3568_VP_BCSH_CTRL 0x60 273#define RK3568_VP_BCSH_BCS 0x64 274#define RK3568_VP_BCSH_H 0x68 275#define RK3568_VP_BCSH_COLOR_BAR 0x6C 276 277/* Overlay registers definition */ 278#define RK3568_OVL_CTRL 0x600 279#define RK3568_OVL_LAYER_SEL 0x604 280#define RK3568_OVL_PORT_SEL 0x608 281#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 282#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 283#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 284#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 285#define RK3568_MIX0_SRC_COLOR_CTRL 0x650 286#define RK3568_MIX0_DST_COLOR_CTRL 0x654 287#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 288#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 289#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 290#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 291#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 292#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 293#define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) 294#define RK3568_CLUSTER_DLY_NUM 0x6F0 295#define RK3568_SMART_DLY_NUM 0x6F8 296 297/* Cluster register definition, offset relative to window base */ 298#define RK3568_CLUSTER0_CTRL_BASE 0x1000 299#define RK3568_CLUSTER1_CTRL_BASE 0x1200 300#define RK3588_CLUSTER2_CTRL_BASE 0x1400 301#define RK3588_CLUSTER3_CTRL_BASE 0x1600 302#define RK3568_ESMART0_CTRL_BASE 0x1800 303#define RK3568_ESMART1_CTRL_BASE 0x1A00 304#define RK3568_SMART0_CTRL_BASE 0x1C00 305#define RK3568_SMART1_CTRL_BASE 0x1E00 306#define RK3588_ESMART2_CTRL_BASE 0x1C00 307#define RK3588_ESMART3_CTRL_BASE 0x1E00 308 309#define RK3568_CLUSTER_WIN_CTRL0 0x00 310#define RK3568_CLUSTER_WIN_CTRL1 0x04 311#define RK3568_CLUSTER_WIN_YRGB_MST 0x10 312#define RK3568_CLUSTER_WIN_CBR_MST 0x14 313#define RK3568_CLUSTER_WIN_VIR 0x18 314#define RK3568_CLUSTER_WIN_ACT_INFO 0x20 315#define RK3568_CLUSTER_WIN_DSP_INFO 0x24 316#define RK3568_CLUSTER_WIN_DSP_ST 0x28 317#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 318#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C 319#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 320#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 321#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 322#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C 323#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 324#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 325#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 326#define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C 327 328#define RK3568_CLUSTER_CTRL 0x100 329 330/* (E)smart register definition, offset relative to window base */ 331#define RK3568_SMART_CTRL0 0x00 332#define RK3568_SMART_CTRL1 0x04 333#define RK3568_SMART_REGION0_CTRL 0x10 334#define RK3568_SMART_REGION0_YRGB_MST 0x14 335#define RK3568_SMART_REGION0_CBR_MST 0x18 336#define RK3568_SMART_REGION0_VIR 0x1C 337#define RK3568_SMART_REGION0_ACT_INFO 0x20 338#define RK3568_SMART_REGION0_DSP_INFO 0x24 339#define RK3568_SMART_REGION0_DSP_ST 0x28 340#define RK3568_SMART_REGION0_SCL_CTRL 0x30 341#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 342#define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 343#define RK3568_SMART_REGION0_SCL_OFFSET 0x3C 344#define RK3568_SMART_REGION1_CTRL 0x40 345#define RK3568_SMART_REGION1_YRGB_MST 0x44 346#define RK3568_SMART_REGION1_CBR_MST 0x48 347#define RK3568_SMART_REGION1_VIR 0x4C 348#define RK3568_SMART_REGION1_ACT_INFO 0x50 349#define RK3568_SMART_REGION1_DSP_INFO 0x54 350#define RK3568_SMART_REGION1_DSP_ST 0x58 351#define RK3568_SMART_REGION1_SCL_CTRL 0x60 352#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 353#define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 354#define RK3568_SMART_REGION1_SCL_OFFSET 0x6C 355#define RK3568_SMART_REGION2_CTRL 0x70 356#define RK3568_SMART_REGION2_YRGB_MST 0x74 357#define RK3568_SMART_REGION2_CBR_MST 0x78 358#define RK3568_SMART_REGION2_VIR 0x7C 359#define RK3568_SMART_REGION2_ACT_INFO 0x80 360#define RK3568_SMART_REGION2_DSP_INFO 0x84 361#define RK3568_SMART_REGION2_DSP_ST 0x88 362#define RK3568_SMART_REGION2_SCL_CTRL 0x90 363#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 364#define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 365#define RK3568_SMART_REGION2_SCL_OFFSET 0x9C 366#define RK3568_SMART_REGION3_CTRL 0xA0 367#define RK3568_SMART_REGION3_YRGB_MST 0xA4 368#define RK3568_SMART_REGION3_CBR_MST 0xA8 369#define RK3568_SMART_REGION3_VIR 0xAC 370#define RK3568_SMART_REGION3_ACT_INFO 0xB0 371#define RK3568_SMART_REGION3_DSP_INFO 0xB4 372#define RK3568_SMART_REGION3_DSP_ST 0xB8 373#define RK3568_SMART_REGION3_SCL_CTRL 0xC0 374#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 375#define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 376#define RK3568_SMART_REGION3_SCL_OFFSET 0xCC 377#define RK3568_SMART_COLOR_KEY_CTRL 0xD0 378 379/* HDR register definition */ 380#define RK3568_HDR_LUT_CTRL 0x2000 381#define RK3568_HDR_LUT_MST 0x2004 382#define RK3568_SDR2HDR_CTRL 0x2010 383#define RK3568_HDR2SDR_CTRL 0x2020 384#define RK3568_HDR2SDR_SRC_RANGE 0x2024 385#define RK3568_HDR2SDR_NORMFACEETF 0x2028 386#define RK3568_HDR2SDR_DST_RANGE 0x202C 387#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 388#define RK3568_HDR_EETF_OETF_Y0 0x203C 389#define RK3568_HDR_SAT_Y0 0x20C0 390#define RK3568_HDR_EOTF_OETF_Y0 0x20F0 391#define RK3568_HDR_OETF_DX_POW1 0x2200 392#define RK3568_HDR_OETF_XN1 0x2300 393 394#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) 395 396#define RK3568_VP_DSP_CTRL__STANDBY BIT(31) 397#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) 398#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) 399#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) 400#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) 401#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) 402#define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10) 403#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) 404#define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8) 405#define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) 406#define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) 407#define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) 408#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) 409#define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) 410 411#define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2) 412#define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0) 413 414#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) 415#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) 416 417#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) 418#define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) 419#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) 420#define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) 421#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) 422#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) 423#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) 424#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) 425#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) 426#define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) 427#define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) 428#define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) 429#define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) 430#define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) 431 432#define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) 433#define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(20, 20) 434#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX GENMASK(19, 18) 435#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX GENMASK(17, 16) 436#define RK3588_SYS_DSP_INFACE_EN_DP1_MUX GENMASK(15, 14) 437#define RK3588_SYS_DSP_INFACE_EN_DP0_MUX GENMASK(13, 12) 438#define RK3588_SYS_DSP_INFACE_EN_DPI GENMASK(9, 8) 439#define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7) 440#define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6) 441#define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5) 442#define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4) 443#define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3) 444#define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2) 445#define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1) 446#define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0) 447 448#define RK3588_DSP_IF_MIPI1_PCLK_DIV GENMASK(27, 26) 449#define RK3588_DSP_IF_MIPI0_PCLK_DIV GENMASK(25, 24) 450#define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV GENMASK(22, 22) 451#define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV GENMASK(21, 20) 452#define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV GENMASK(18, 18) 453#define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV GENMASK(17, 16) 454 455#define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) 456#define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) 457#define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) 458#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) 459 460#define RK3588_DSP_IF_POL__DP1_PIN_POL GENMASK(14, 12) 461#define RK3588_DSP_IF_POL__DP0_PIN_POL GENMASK(10, 8) 462 463#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) 464#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) 465 466#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) 467 468#define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) 469 470#define VOP2_SYS_AXI_BUS_NUM 2 471 472#define VOP2_CLUSTER_YUV444_10 0x12 473 474#define VOP2_COLOR_KEY_MASK BIT(31) 475 476#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) 477#define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp) 478 479#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) 480 481#define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) 482#define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) 483#define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) 484#define RK3588_OVL_PORT_SEL__ESMART3 GENMASK(31, 30) 485#define RK3588_OVL_PORT_SEL__ESMART2 GENMASK(29, 28) 486#define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) 487#define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) 488#define RK3588_OVL_PORT_SEL__CLUSTER3 GENMASK(23, 22) 489#define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20) 490#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) 491#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) 492#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) 493#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) 494#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) 495#define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) 496 497#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) 498#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) 499#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) 500#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) 501 502#define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0) 503 504#define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0) 505 506#define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) 507#define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) 508#define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) 509#define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) 510 511#define VP_INT_DSP_HOLD_VALID BIT(6) 512#define VP_INT_FS_FIELD BIT(5) 513#define VP_INT_POST_BUF_EMPTY BIT(4) 514#define VP_INT_LINE_FLAG1 BIT(3) 515#define VP_INT_LINE_FLAG0 BIT(2) 516#define VOP2_INT_BUS_ERRPR BIT(1) 517#define VP_INT_FS BIT(0) 518 519#define POLFLAG_DCLK_INV BIT(3) 520 521enum vop2_layer_phy_id { 522 ROCKCHIP_VOP2_CLUSTER0 = 0, 523 ROCKCHIP_VOP2_CLUSTER1, 524 ROCKCHIP_VOP2_ESMART0, 525 ROCKCHIP_VOP2_ESMART1, 526 ROCKCHIP_VOP2_SMART0, 527 ROCKCHIP_VOP2_SMART1, 528 ROCKCHIP_VOP2_CLUSTER2, 529 ROCKCHIP_VOP2_CLUSTER3, 530 ROCKCHIP_VOP2_ESMART2, 531 ROCKCHIP_VOP2_ESMART3, 532 ROCKCHIP_VOP2_PHY_ID_INVALID = -1, 533}; 534 535extern const struct component_ops vop2_component_ops; 536 537#endif /* _ROCKCHIP_DRM_VOP2_H */ 538