1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * R-Car LVDS Interface Registers Definitions
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#ifndef __RCAR_LVDS_REGS_H__
11#define __RCAR_LVDS_REGS_H__
12
13#define LVDCR0				0x0000
14#define LVDCR0_DUSEL			(1 << 15)
15#define LVDCR0_DMD			(1 << 12)		/* Gen2 only */
16#define LVDCR0_LVMD_MASK		(0xf << 8)
17#define LVDCR0_LVMD_SHIFT		8
18#define LVDCR0_PLLON			(1 << 4)
19#define LVDCR0_PWD			(1 << 2)		/* Gen3 only */
20#define LVDCR0_BEN			(1 << 2)		/* Gen2 only */
21#define LVDCR0_LVEN			(1 << 1)
22#define LVDCR0_LVRES			(1 << 0)
23
24#define LVDCR1				0x0004
25#define LVDCR1_CKSEL			(1 << 15)		/* Gen2 only */
26#define LVDCR1_CHSTBY(n)		(3 << (2 + (n) * 2))
27#define LVDCR1_CLKSTBY			(3 << 0)
28
29#define LVDPLLCR			0x0008
30/* Gen2 & V3M */
31#define LVDPLLCR_CEEN			(1 << 14)
32#define LVDPLLCR_FBEN			(1 << 13)
33#define LVDPLLCR_COSEL			(1 << 12)
34#define LVDPLLCR_PLLDLYCNT_150M		(0x1bf << 0)
35#define LVDPLLCR_PLLDLYCNT_121M		(0x22c << 0)
36#define LVDPLLCR_PLLDLYCNT_60M		(0x77b << 0)
37#define LVDPLLCR_PLLDLYCNT_38M		(0x69a << 0)
38#define LVDPLLCR_PLLDLYCNT_MASK		(0x7ff << 0)
39/* Gen3 but V3M,D3 and E3 */
40#define LVDPLLCR_PLLDIVCNT_42M		(0x014cb << 0)
41#define LVDPLLCR_PLLDIVCNT_85M		(0x00a45 << 0)
42#define LVDPLLCR_PLLDIVCNT_128M		(0x006c3 << 0)
43#define LVDPLLCR_PLLDIVCNT_148M		(0x046c1 << 0)
44#define LVDPLLCR_PLLDIVCNT_MASK		(0x7ffff << 0)
45/* D3 and E3 */
46#define LVDPLLCR_PLLON			(1 << 22)
47#define LVDPLLCR_PLLSEL_PLL0		(0 << 20)
48#define LVDPLLCR_PLLSEL_LVX		(1 << 20)
49#define LVDPLLCR_PLLSEL_PLL1		(2 << 20)
50#define LVDPLLCR_CKSEL_LVX		(1 << 17)
51#define LVDPLLCR_CKSEL_EXTAL		(3 << 17)
52#define LVDPLLCR_CKSEL_DU_DOTCLKIN(n)	((5 + (n) * 2) << 17)
53#define LVDPLLCR_OCKSEL			(1 << 16)
54#define LVDPLLCR_STP_CLKOUTE		(1 << 14)
55#define LVDPLLCR_OUTCLKSEL		(1 << 12)
56#define LVDPLLCR_CLKOUT			(1 << 11)
57#define LVDPLLCR_PLLE(n)		((n) << 10)
58#define LVDPLLCR_PLLN(n)		((n) << 3)
59#define LVDPLLCR_PLLM(n)		((n) << 0)
60
61#define LVDCTRCR			0x000c
62#define LVDCTRCR_CTR3SEL_ZERO		(0 << 12)
63#define LVDCTRCR_CTR3SEL_ODD		(1 << 12)
64#define LVDCTRCR_CTR3SEL_CDE		(2 << 12)
65#define LVDCTRCR_CTR3SEL_MASK		(7 << 12)
66#define LVDCTRCR_CTR2SEL_DISP		(0 << 8)
67#define LVDCTRCR_CTR2SEL_ODD		(1 << 8)
68#define LVDCTRCR_CTR2SEL_CDE		(2 << 8)
69#define LVDCTRCR_CTR2SEL_HSYNC		(3 << 8)
70#define LVDCTRCR_CTR2SEL_VSYNC		(4 << 8)
71#define LVDCTRCR_CTR2SEL_MASK		(7 << 8)
72#define LVDCTRCR_CTR1SEL_VSYNC		(0 << 4)
73#define LVDCTRCR_CTR1SEL_DISP		(1 << 4)
74#define LVDCTRCR_CTR1SEL_ODD		(2 << 4)
75#define LVDCTRCR_CTR1SEL_CDE		(3 << 4)
76#define LVDCTRCR_CTR1SEL_HSYNC		(4 << 4)
77#define LVDCTRCR_CTR1SEL_MASK		(7 << 4)
78#define LVDCTRCR_CTR0SEL_HSYNC		(0 << 0)
79#define LVDCTRCR_CTR0SEL_VSYNC		(1 << 0)
80#define LVDCTRCR_CTR0SEL_DISP		(2 << 0)
81#define LVDCTRCR_CTR0SEL_ODD		(3 << 0)
82#define LVDCTRCR_CTR0SEL_CDE		(4 << 0)
83#define LVDCTRCR_CTR0SEL_MASK		(7 << 0)
84
85#define LVDCHCR				0x0010
86#define LVDCHCR_CHSEL_CH(n, c)		((((c) - (n)) & 3) << ((n) * 4))
87#define LVDCHCR_CHSEL_MASK(n)		(3 << ((n) * 4))
88
89/* All registers below are specific to D3 and E3 */
90#define LVDSTRIPE			0x0014
91#define LVDSTRIPE_ST_TRGSEL_DISP	(0 << 2)
92#define LVDSTRIPE_ST_TRGSEL_HSYNC_R	(1 << 2)
93#define LVDSTRIPE_ST_TRGSEL_HSYNC_F	(2 << 2)
94#define LVDSTRIPE_ST_SWAP		(1 << 1)
95#define LVDSTRIPE_ST_ON			(1 << 0)
96
97#define LVDSCR				0x0018
98#define LVDSCR_DEPTH(n)			(((n) - 1) << 29)
99#define LVDSCR_BANDSET			(1 << 28)
100#define LVDSCR_TWGCNT(n)		((((n) - 256) / 16) << 24)
101#define LVDSCR_SDIV(n)			((n) << 22)
102#define LVDSCR_MODE			(1 << 21)
103#define LVDSCR_RSTN			(1 << 20)
104
105#define LVDDIV				0x001c
106#define LVDDIV_DIVSEL			(1 << 8)
107#define LVDDIV_DIVRESET			(1 << 7)
108#define LVDDIV_DIVSTP			(1 << 6)
109#define LVDDIV_DIV(n)			((n) << 0)
110
111#endif /* __RCAR_LVDS_REGS_H__ */
112