1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef SMU7_H 25#define SMU7_H 26 27#pragma pack(push, 1) 28 29#define SMU7_CONTEXT_ID_SMC 1 30#define SMU7_CONTEXT_ID_VBIOS 2 31 32 33#define SMU7_CONTEXT_ID_SMC 1 34#define SMU7_CONTEXT_ID_VBIOS 2 35 36#define SMU7_MAX_LEVELS_VDDC 8 37#define SMU7_MAX_LEVELS_VDDCI 4 38#define SMU7_MAX_LEVELS_MVDD 4 39#define SMU7_MAX_LEVELS_VDDNB 8 40 41#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 42#define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 43#define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 44#define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 45#define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 46#define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 47#define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 48#define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 49#define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 50 51#define DPM_NO_LIMIT 0 52#define DPM_NO_UP 1 53#define DPM_GO_DOWN 2 54#define DPM_GO_UP 3 55 56#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 57#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 58 59#define GPIO_CLAMP_MODE_VRHOT 1 60#define GPIO_CLAMP_MODE_THERM 2 61#define GPIO_CLAMP_MODE_DC 4 62 63#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 64#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 65#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 66#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 67#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 68#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 69#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 70#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 71#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 72#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 73#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 74#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 75#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 76#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 77#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 78#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 79#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 80#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 81#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 82#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 83 84 85struct SMU7_PIDController { 86 uint32_t Ki; 87 int32_t LFWindupUL; 88 int32_t LFWindupLL; 89 uint32_t StatePrecision; 90 uint32_t LfPrecision; 91 uint32_t LfOffset; 92 uint32_t MaxState; 93 uint32_t MaxLfFraction; 94 uint32_t StateShift; 95}; 96 97typedef struct SMU7_PIDController SMU7_PIDController; 98 99// ------------------------------------------------------------------------------------------------------------------------- 100#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 101 102#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 103#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 104#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 105#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 106#define SMU7_UVD_DPM_CONFIG_MASK 0x10 107#define SMU7_VCE_DPM_CONFIG_MASK 0x20 108#define SMU7_ACP_DPM_CONFIG_MASK 0x40 109#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 110#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 111 112#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 113#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 114#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 115#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 116#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 117#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 118 119struct SMU7_Firmware_Header { 120 uint32_t Digest[5]; 121 uint32_t Version; 122 uint32_t HeaderSize; 123 uint32_t Flags; 124 uint32_t EntryPoint; 125 uint32_t CodeSize; 126 uint32_t ImageSize; 127 128 uint32_t Rtos; 129 uint32_t SoftRegisters; 130 uint32_t DpmTable; 131 uint32_t FanTable; 132 uint32_t CacConfigTable; 133 uint32_t CacStatusTable; 134 135 uint32_t mcRegisterTable; 136 137 uint32_t mcArbDramTimingTable; 138 139 uint32_t PmFuseTable; 140 uint32_t Globals; 141 uint32_t Reserved[42]; 142 uint32_t Signature; 143}; 144 145typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; 146 147#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 148 149enum DisplayConfig { 150 PowerDown = 1, 151 DP54x4, 152 DP54x2, 153 DP54x1, 154 DP27x4, 155 DP27x2, 156 DP27x1, 157 HDMI297, 158 HDMI162, 159 LVDS, 160 DP324x4, 161 DP324x2, 162 DP324x1 163}; 164 165#pragma pack(pop) 166 167#endif 168 169