1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <linux/pci.h> 30#include <linux/seq_file.h> 31#include <linux/slab.h> 32 33#include <drm/drm_device.h> 34#include <drm/drm_file.h> 35 36#include "atom.h" 37#include "r100d.h" 38#include "r420_reg_safe.h" 39#include "r420d.h" 40#include "radeon.h" 41#include "radeon_asic.h" 42#include "radeon_reg.h" 43 44void r420_pm_init_profile(struct radeon_device *rdev) 45{ 46 /* default */ 47 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 51 /* low sh */ 52 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 56 /* mid sh */ 57 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 61 /* high sh */ 62 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 66 /* low mh */ 67 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 71 /* mid mh */ 72 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 76 /* high mh */ 77 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 81} 82 83static void r420_set_reg_safe(struct radeon_device *rdev) 84{ 85 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 86 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 87} 88 89void r420_pipes_init(struct radeon_device *rdev) 90{ 91 unsigned tmp; 92 unsigned gb_pipe_select; 93 unsigned num_pipes; 94 95 /* GA_ENHANCE workaround TCL deadlock issue */ 96 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 97 (1 << 2) | (1 << 3)); 98 /* add idle wait as per freedesktop.org bug 24041 */ 99 if (r100_gui_wait_for_idle(rdev)) { 100 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 101 } 102 /* get max number of pipes */ 103 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 104 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 105 106 /* SE chips have 1 pipe */ 107 if ((rdev->pdev->device == 0x5e4c) || 108 (rdev->pdev->device == 0x5e4f)) 109 num_pipes = 1; 110 111 rdev->num_gb_pipes = num_pipes; 112 tmp = 0; 113 switch (num_pipes) { 114 default: 115 /* force to 1 pipe */ 116 num_pipes = 1; 117 fallthrough; 118 case 1: 119 tmp = (0 << 1); 120 break; 121 case 2: 122 tmp = (3 << 1); 123 break; 124 case 3: 125 tmp = (6 << 1); 126 break; 127 case 4: 128 tmp = (7 << 1); 129 break; 130 } 131 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 132 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 133 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 134 WREG32(R300_GB_TILE_CONFIG, tmp); 135 if (r100_gui_wait_for_idle(rdev)) { 136 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 137 } 138 139 tmp = RREG32(R300_DST_PIPE_CONFIG); 140 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 141 142 WREG32(R300_RB2D_DSTCACHE_MODE, 143 RREG32(R300_RB2D_DSTCACHE_MODE) | 144 R300_DC_AUTOFLUSH_ENABLE | 145 R300_DC_DC_DISABLE_IGNORE_PE); 146 147 if (r100_gui_wait_for_idle(rdev)) { 148 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 149 } 150 151 if (rdev->family == CHIP_RV530) { 152 tmp = RREG32(RV530_GB_PIPE_SELECT2); 153 if ((tmp & 3) == 3) 154 rdev->num_z_pipes = 2; 155 else 156 rdev->num_z_pipes = 1; 157 } else 158 rdev->num_z_pipes = 1; 159 160 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 161 rdev->num_gb_pipes, rdev->num_z_pipes); 162} 163 164u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 165{ 166 unsigned long flags; 167 u32 r; 168 169 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 170 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 171 r = RREG32(R_0001FC_MC_IND_DATA); 172 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 173 return r; 174} 175 176void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 177{ 178 unsigned long flags; 179 180 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 181 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 182 S_0001F8_MC_IND_WR_EN(1)); 183 WREG32(R_0001FC_MC_IND_DATA, v); 184 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 185} 186 187static void r420_debugfs(struct radeon_device *rdev) 188{ 189 r100_debugfs_rbbm_init(rdev); 190 r420_debugfs_pipes_info_init(rdev); 191} 192 193static void r420_clock_resume(struct radeon_device *rdev) 194{ 195 u32 sclk_cntl; 196 197 if (radeon_dynclks != -1 && radeon_dynclks) 198 radeon_atom_set_clock_gating(rdev, 1); 199 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 200 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 201 if (rdev->family == CHIP_R420) 202 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 203 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 204} 205 206static void r420_cp_errata_init(struct radeon_device *rdev) 207{ 208 int r; 209 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 210 211 /* RV410 and R420 can lock up if CP DMA to host memory happens 212 * while the 2D engine is busy. 213 * 214 * The proper workaround is to queue a RESYNC at the beginning 215 * of the CP init, apparently. 216 */ 217 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 218 r = radeon_ring_lock(rdev, ring, 8); 219 WARN_ON(r); 220 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 221 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 222 radeon_ring_write(ring, 0xDEADBEEF); 223 radeon_ring_unlock_commit(rdev, ring, false); 224} 225 226static void r420_cp_errata_fini(struct radeon_device *rdev) 227{ 228 int r; 229 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 230 231 /* Catch the RESYNC we dispatched all the way back, 232 * at the very beginning of the CP init. 233 */ 234 r = radeon_ring_lock(rdev, ring, 8); 235 WARN_ON(r); 236 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 237 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 238 radeon_ring_unlock_commit(rdev, ring, false); 239 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 240} 241 242static int r420_startup(struct radeon_device *rdev) 243{ 244 int r; 245 246 /* set common regs */ 247 r100_set_common_regs(rdev); 248 /* program mc */ 249 r300_mc_program(rdev); 250 /* Resume clock */ 251 r420_clock_resume(rdev); 252 /* Initialize GART (initialize after TTM so we can allocate 253 * memory through TTM but finalize after TTM) */ 254 if (rdev->flags & RADEON_IS_PCIE) { 255 r = rv370_pcie_gart_enable(rdev); 256 if (r) 257 return r; 258 } 259 if (rdev->flags & RADEON_IS_PCI) { 260 r = r100_pci_gart_enable(rdev); 261 if (r) 262 return r; 263 } 264 r420_pipes_init(rdev); 265 266 /* allocate wb buffer */ 267 r = radeon_wb_init(rdev); 268 if (r) 269 return r; 270 271 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 272 if (r) { 273 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 274 return r; 275 } 276 277 /* Enable IRQ */ 278 if (!rdev->irq.installed) { 279 r = radeon_irq_kms_init(rdev); 280 if (r) 281 return r; 282 } 283 284 r100_irq_set(rdev); 285 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 286 /* 1M ring buffer */ 287 r = r100_cp_init(rdev, 1024 * 1024); 288 if (r) { 289 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 290 return r; 291 } 292 r420_cp_errata_init(rdev); 293 294 r = radeon_ib_pool_init(rdev); 295 if (r) { 296 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 297 return r; 298 } 299 300 return 0; 301} 302 303int r420_resume(struct radeon_device *rdev) 304{ 305 int r; 306 307 /* Make sur GART are not working */ 308 if (rdev->flags & RADEON_IS_PCIE) 309 rv370_pcie_gart_disable(rdev); 310 if (rdev->flags & RADEON_IS_PCI) 311 r100_pci_gart_disable(rdev); 312 /* Resume clock before doing reset */ 313 r420_clock_resume(rdev); 314 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 315 if (radeon_asic_reset(rdev)) { 316 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 317 RREG32(R_000E40_RBBM_STATUS), 318 RREG32(R_0007C0_CP_STAT)); 319 } 320 /* check if cards are posted or not */ 321 if (rdev->is_atom_bios) { 322 atom_asic_init(rdev->mode_info.atom_context); 323 } else { 324 radeon_combios_asic_init(rdev->ddev); 325 } 326 /* Resume clock after posting */ 327 r420_clock_resume(rdev); 328 /* Initialize surface registers */ 329 radeon_surface_init(rdev); 330 331 rdev->accel_working = true; 332 r = r420_startup(rdev); 333 if (r) { 334 rdev->accel_working = false; 335 } 336 return r; 337} 338 339int r420_suspend(struct radeon_device *rdev) 340{ 341 radeon_pm_suspend(rdev); 342 r420_cp_errata_fini(rdev); 343 r100_cp_disable(rdev); 344 radeon_wb_disable(rdev); 345 r100_irq_disable(rdev); 346 if (rdev->flags & RADEON_IS_PCIE) 347 rv370_pcie_gart_disable(rdev); 348 if (rdev->flags & RADEON_IS_PCI) 349 r100_pci_gart_disable(rdev); 350 return 0; 351} 352 353void r420_fini(struct radeon_device *rdev) 354{ 355 radeon_pm_fini(rdev); 356 r100_cp_fini(rdev); 357 radeon_wb_fini(rdev); 358 radeon_ib_pool_fini(rdev); 359 radeon_gem_fini(rdev); 360 if (rdev->flags & RADEON_IS_PCIE) 361 rv370_pcie_gart_fini(rdev); 362 if (rdev->flags & RADEON_IS_PCI) 363 r100_pci_gart_fini(rdev); 364 radeon_agp_fini(rdev); 365 radeon_irq_kms_fini(rdev); 366 radeon_fence_driver_fini(rdev); 367 radeon_bo_fini(rdev); 368 if (rdev->is_atom_bios) { 369 radeon_atombios_fini(rdev); 370 } else { 371 radeon_combios_fini(rdev); 372 } 373 kfree(rdev->bios); 374 rdev->bios = NULL; 375} 376 377int r420_init(struct radeon_device *rdev) 378{ 379 int r; 380 381 /* Initialize scratch registers */ 382 radeon_scratch_init(rdev); 383 /* Initialize surface registers */ 384 radeon_surface_init(rdev); 385 /* TODO: disable VGA need to use VGA request */ 386 /* restore some register to sane defaults */ 387 r100_restore_sanity(rdev); 388 /* BIOS*/ 389 if (!radeon_get_bios(rdev)) { 390 if (ASIC_IS_AVIVO(rdev)) 391 return -EINVAL; 392 } 393 if (rdev->is_atom_bios) { 394 r = radeon_atombios_init(rdev); 395 if (r) { 396 return r; 397 } 398 } else { 399 r = radeon_combios_init(rdev); 400 if (r) { 401 return r; 402 } 403 } 404 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 405 if (radeon_asic_reset(rdev)) { 406 dev_warn(rdev->dev, 407 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 408 RREG32(R_000E40_RBBM_STATUS), 409 RREG32(R_0007C0_CP_STAT)); 410 } 411 /* check if cards are posted or not */ 412 if (radeon_boot_test_post_card(rdev) == false) 413 return -EINVAL; 414 415 /* Initialize clocks */ 416 radeon_get_clock_info(rdev->ddev); 417 /* initialize AGP */ 418 if (rdev->flags & RADEON_IS_AGP) { 419 r = radeon_agp_init(rdev); 420 if (r) { 421 radeon_agp_disable(rdev); 422 } 423 } 424 /* initialize memory controller */ 425 r300_mc_init(rdev); 426 r420_debugfs(rdev); 427 /* Fence driver */ 428 radeon_fence_driver_init(rdev); 429 /* Memory manager */ 430 r = radeon_bo_init(rdev); 431 if (r) { 432 return r; 433 } 434 if (rdev->family == CHIP_R420) 435 r100_enable_bm(rdev); 436 437 if (rdev->flags & RADEON_IS_PCIE) { 438 r = rv370_pcie_gart_init(rdev); 439 if (r) 440 return r; 441 } 442 if (rdev->flags & RADEON_IS_PCI) { 443 r = r100_pci_gart_init(rdev); 444 if (r) 445 return r; 446 } 447 r420_set_reg_safe(rdev); 448 449 /* Initialize power management */ 450 radeon_pm_init(rdev); 451 452 rdev->accel_working = true; 453 r = r420_startup(rdev); 454 if (r) { 455 /* Somethings want wront with the accel init stop accel */ 456 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 457 r100_cp_fini(rdev); 458 radeon_wb_fini(rdev); 459 radeon_ib_pool_fini(rdev); 460 radeon_irq_kms_fini(rdev); 461 if (rdev->flags & RADEON_IS_PCIE) 462 rv370_pcie_gart_fini(rdev); 463 if (rdev->flags & RADEON_IS_PCI) 464 r100_pci_gart_fini(rdev); 465 radeon_agp_fini(rdev); 466 rdev->accel_working = false; 467 } 468 return 0; 469} 470 471/* 472 * Debugfs info 473 */ 474#if defined(CONFIG_DEBUG_FS) 475static int r420_debugfs_pipes_info_show(struct seq_file *m, void *unused) 476{ 477 struct radeon_device *rdev = m->private; 478 uint32_t tmp; 479 480 tmp = RREG32(R400_GB_PIPE_SELECT); 481 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 482 tmp = RREG32(R300_GB_TILE_CONFIG); 483 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 484 tmp = RREG32(R300_DST_PIPE_CONFIG); 485 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 486 return 0; 487} 488 489DEFINE_SHOW_ATTRIBUTE(r420_debugfs_pipes_info); 490#endif 491 492void r420_debugfs_pipes_info_init(struct radeon_device *rdev) 493{ 494#if defined(CONFIG_DEBUG_FS) 495 struct dentry *root = rdev->ddev->primary->debugfs_root; 496 497 debugfs_create_file("r420_pipes_info", 0444, root, rdev, 498 &r420_debugfs_pipes_info_fops); 499#endif 500} 501