1/* SPDX-License-Identifier: MIT */
2#ifndef __NV40_GR_H__
3#define __NV40_GR_H__
4#define nv40_gr(p) container_of((p), struct nv40_gr, base)
5#include "priv.h"
6
7struct nv40_gr {
8	struct nvkm_gr base;
9	u32 size;
10	struct list_head chan;
11};
12
13int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
14		 struct nvkm_gr **);
15int nv40_gr_init(struct nvkm_gr *);
16void nv40_gr_intr(struct nvkm_gr *);
17u64 nv40_gr_units(struct nvkm_gr *);
18
19#define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object)
20#include <core/object.h>
21
22struct nv40_gr_chan {
23	struct nvkm_object object;
24	struct nv40_gr *gr;
25	struct nvkm_chan *fifo;
26	u32 inst;
27	struct list_head head;
28};
29
30int nv40_gr_chan_new(struct nvkm_gr *, struct nvkm_chan *,
31		     const struct nvkm_oclass *, struct nvkm_object **);
32
33extern const struct nvkm_object_func nv40_gr_object;
34
35/* returns 1 if device is one of the nv4x using the 0x4497 object class,
36 * helpful to determine a number of other hardware features
37 */
38static inline int
39nv44_gr_class(struct nvkm_device *device)
40{
41	if ((device->chipset & 0xf0) == 0x60)
42		return 1;
43
44	return !(0x0aaf & (1 << (device->chipset & 0x0f)));
45}
46
47int  nv40_grctx_init(struct nvkm_device *, u32 *size);
48void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
49#endif
50