1#ifndef __src_nvidia_arch_nvalloc_common_inc_rmRiscvUcode_h__
2#define __src_nvidia_arch_nvalloc_common_inc_rmRiscvUcode_h__
3
4/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
5
6/*
7 * SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8 * SPDX-License-Identifier: MIT
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29typedef struct {
30    //
31    // Version 1
32    // Version 2
33    // Version 3 = for Partition boot
34    // Version 4 = for eb riscv boot
35    // Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later.
36    //
37    NvU32  version;                         // structure version
38    NvU32  bootloaderOffset;
39    NvU32  bootloaderSize;
40    NvU32  bootloaderParamOffset;
41    NvU32  bootloaderParamSize;
42    NvU32  riscvElfOffset;
43    NvU32  riscvElfSize;
44    NvU32  appVersion;                      // Changelist number associated with the image
45    //
46    // Manifest contains information about Monitor and it is
47    // input to BR
48    //
49    NvU32  manifestOffset;
50    NvU32  manifestSize;
51    //
52    // Monitor Data offset within RISCV image and size
53    //
54    NvU32  monitorDataOffset;
55    NvU32  monitorDataSize;
56    //
57    // Monitor Code offset withtin RISCV image and size
58    //
59    NvU32  monitorCodeOffset;
60    NvU32  monitorCodeSize;
61    NvU32  bIsMonitorEnabled;
62    //
63    // Swbrom Code offset within RISCV image and size
64    //
65    NvU32  swbromCodeOffset;
66    NvU32  swbromCodeSize;
67    //
68    // Swbrom Data offset within RISCV image and size
69    //
70    NvU32  swbromDataOffset;
71    NvU32  swbromDataSize;
72    //
73    // Total size of FB carveout (image and reserved space).
74    //
75    NvU32  fbReservedSize;
76    //
77    // Indicates whether the entire RISC-V image is signed as "code" in code section.
78    //
79    NvU32  bSignedAsCode;
80} RM_RISCV_UCODE_DESC;
81
82#endif
83