1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5#ifndef _DPU_HW_SSPP_H
6#define _DPU_HW_SSPP_H
7
8#include "dpu_hw_catalog.h"
9#include "dpu_hw_mdss.h"
10#include "dpu_hw_util.h"
11#include "dpu_formats.h"
12
13struct dpu_hw_sspp;
14
15/**
16 * Flags
17 */
18#define DPU_SSPP_FLIP_LR		BIT(0)
19#define DPU_SSPP_FLIP_UD		BIT(1)
20#define DPU_SSPP_SOURCE_ROTATED_90	BIT(2)
21#define DPU_SSPP_ROT_90			BIT(3)
22#define DPU_SSPP_SOLID_FILL		BIT(4)
23
24/**
25 * Component indices
26 */
27enum {
28	DPU_SSPP_COMP_0,
29	DPU_SSPP_COMP_1_2,
30	DPU_SSPP_COMP_2,
31	DPU_SSPP_COMP_3,
32
33	DPU_SSPP_COMP_MAX
34};
35
36/**
37 * DPU_SSPP_RECT_SOLO - multirect disabled
38 * DPU_SSPP_RECT_0 - rect0 of a multirect pipe
39 * DPU_SSPP_RECT_1 - rect1 of a multirect pipe
40 *
41 * Note: HW supports multirect with either RECT0 or
42 * RECT1. Considering no benefit of such configs over
43 * SOLO mode and to keep the plane management simple,
44 * we dont support single rect multirect configs.
45 */
46enum dpu_sspp_multirect_index {
47	DPU_SSPP_RECT_SOLO = 0,
48	DPU_SSPP_RECT_0,
49	DPU_SSPP_RECT_1,
50};
51
52enum dpu_sspp_multirect_mode {
53	DPU_SSPP_MULTIRECT_NONE = 0,
54	DPU_SSPP_MULTIRECT_PARALLEL,
55	DPU_SSPP_MULTIRECT_TIME_MX,
56};
57
58enum {
59	DPU_FRAME_LINEAR,
60	DPU_FRAME_TILE_A4X,
61	DPU_FRAME_TILE_A5X,
62};
63
64enum dpu_hw_filter {
65	DPU_SCALE_FILTER_NEAREST = 0,
66	DPU_SCALE_FILTER_BIL,
67	DPU_SCALE_FILTER_PCMN,
68	DPU_SCALE_FILTER_CA,
69	DPU_SCALE_FILTER_MAX
70};
71
72enum dpu_hw_filter_alpa {
73	DPU_SCALE_ALPHA_PIXEL_REP,
74	DPU_SCALE_ALPHA_BIL
75};
76
77enum dpu_hw_filter_yuv {
78	DPU_SCALE_2D_4X4,
79	DPU_SCALE_2D_CIR,
80	DPU_SCALE_1D_SEP,
81	DPU_SCALE_BIL
82};
83
84struct dpu_hw_sharp_cfg {
85	u32 strength;
86	u32 edge_thr;
87	u32 smooth_thr;
88	u32 noise_thr;
89};
90
91struct dpu_hw_pixel_ext {
92	/* scaling factors are enabled for this input layer */
93	uint8_t enable_pxl_ext;
94
95	int init_phase_x[DPU_MAX_PLANES];
96	int phase_step_x[DPU_MAX_PLANES];
97	int init_phase_y[DPU_MAX_PLANES];
98	int phase_step_y[DPU_MAX_PLANES];
99
100	/*
101	 * Number of pixels extension in left, right, top and bottom direction
102	 * for all color components. This pixel value for each color component
103	 * should be sum of fetch + repeat pixels.
104	 */
105	int num_ext_pxls_left[DPU_MAX_PLANES];
106	int num_ext_pxls_right[DPU_MAX_PLANES];
107	int num_ext_pxls_top[DPU_MAX_PLANES];
108	int num_ext_pxls_btm[DPU_MAX_PLANES];
109
110	/*
111	 * Number of pixels needs to be overfetched in left, right, top and
112	 * bottom directions from source image for scaling.
113	 */
114	int left_ftch[DPU_MAX_PLANES];
115	int right_ftch[DPU_MAX_PLANES];
116	int top_ftch[DPU_MAX_PLANES];
117	int btm_ftch[DPU_MAX_PLANES];
118
119	/*
120	 * Number of pixels needs to be repeated in left, right, top and
121	 * bottom directions for scaling.
122	 */
123	int left_rpt[DPU_MAX_PLANES];
124	int right_rpt[DPU_MAX_PLANES];
125	int top_rpt[DPU_MAX_PLANES];
126	int btm_rpt[DPU_MAX_PLANES];
127
128	uint32_t roi_w[DPU_MAX_PLANES];
129	uint32_t roi_h[DPU_MAX_PLANES];
130
131	/*
132	 * Filter type to be used for scaling in horizontal and vertical
133	 * directions
134	 */
135	enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
136	enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
137
138};
139
140/**
141 * struct dpu_sw_pipe_cfg : software pipe configuration
142 * @src_rect:  src ROI, caller takes into account the different operations
143 *             such as decimation, flip etc to program this field
144 * @dest_rect: destination ROI.
145 */
146struct dpu_sw_pipe_cfg {
147	struct drm_rect src_rect;
148	struct drm_rect dst_rect;
149};
150
151/**
152 * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
153 * @size: size to prefill in bytes, or zero to disable
154 * @time: time to prefill in usec, or zero to disable
155 */
156struct dpu_hw_pipe_ts_cfg {
157	u64 size;
158	u64 time;
159};
160
161/**
162 * struct dpu_sw_pipe - software pipe description
163 * @sspp:      backing SSPP pipe
164 * @index:     index of the rectangle of SSPP
165 * @mode:      parallel or time multiplex multirect mode
166 */
167struct dpu_sw_pipe {
168	struct dpu_hw_sspp *sspp;
169	enum dpu_sspp_multirect_index multirect_index;
170	enum dpu_sspp_multirect_mode multirect_mode;
171};
172
173/**
174 * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
175 * Caller must call the init function to get the pipe context for each pipe
176 * Assumption is these functions will be called after clocks are enabled
177 */
178struct dpu_hw_sspp_ops {
179	/**
180	 * setup_format - setup pixel format cropping rectangle, flip
181	 * @pipe: Pointer to software pipe context
182	 * @cfg: Pointer to pipe config structure
183	 * @flags: Extra flags for format config
184	 */
185	void (*setup_format)(struct dpu_sw_pipe *pipe,
186			     const struct dpu_format *fmt, u32 flags);
187
188	/**
189	 * setup_rects - setup pipe ROI rectangles
190	 * @pipe: Pointer to software pipe context
191	 * @cfg: Pointer to pipe config structure
192	 */
193	void (*setup_rects)(struct dpu_sw_pipe *pipe,
194			    struct dpu_sw_pipe_cfg *cfg);
195
196	/**
197	 * setup_pe - setup pipe pixel extension
198	 * @ctx: Pointer to pipe context
199	 * @pe_ext: Pointer to pixel ext settings
200	 */
201	void (*setup_pe)(struct dpu_hw_sspp *ctx,
202			struct dpu_hw_pixel_ext *pe_ext);
203
204	/**
205	 * setup_sourceaddress - setup pipe source addresses
206	 * @pipe: Pointer to software pipe context
207	 * @layout: format layout information for programming buffer to hardware
208	 */
209	void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
210				    struct dpu_hw_fmt_layout *layout);
211
212	/**
213	 * setup_csc - setup color space coversion
214	 * @ctx: Pointer to pipe context
215	 * @data: Pointer to config structure
216	 */
217	void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
218
219	/**
220	 * setup_solidfill - enable/disable colorfill
221	 * @pipe: Pointer to software pipe context
222	 * @const_color: Fill color value
223	 * @flags: Pipe flags
224	 */
225	void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color);
226
227	/**
228	 * setup_multirect - setup multirect configuration
229	 * @pipe: Pointer to software pipe context
230	 */
231
232	void (*setup_multirect)(struct dpu_sw_pipe *pipe);
233
234	/**
235	 * setup_sharpening - setup sharpening
236	 * @ctx: Pointer to pipe context
237	 * @cfg: Pointer to config structure
238	 */
239	void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
240			struct dpu_hw_sharp_cfg *cfg);
241
242
243	/**
244	 * setup_qos_lut - setup QoS LUTs
245	 * @ctx: Pointer to pipe context
246	 * @cfg: LUT configuration
247	 */
248	void (*setup_qos_lut)(struct dpu_hw_sspp *ctx,
249			struct dpu_hw_qos_cfg *cfg);
250
251	/**
252	 * setup_qos_ctrl - setup QoS control
253	 * @ctx: Pointer to pipe context
254	 * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT
255	 */
256	void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
257			       bool danger_safe_en);
258
259	/**
260	 * setup_clk_force_ctrl - setup clock force control
261	 * @ctx: Pointer to pipe context
262	 * @enable: enable clock force if true
263	 */
264	bool (*setup_clk_force_ctrl)(struct dpu_hw_sspp *ctx,
265				     bool enable);
266
267	/**
268	 * setup_histogram - setup histograms
269	 * @ctx: Pointer to pipe context
270	 * @cfg: Pointer to histogram configuration
271	 */
272	void (*setup_histogram)(struct dpu_hw_sspp *ctx,
273			void *cfg);
274
275	/**
276	 * setup_scaler - setup scaler
277	 * @scaler3_cfg: Pointer to scaler configuration
278	 * @format: pixel format parameters
279	 */
280	void (*setup_scaler)(struct dpu_hw_sspp *ctx,
281		struct dpu_hw_scaler3_cfg *scaler3_cfg,
282		const struct dpu_format *format);
283
284	/**
285	 * setup_cdp - setup client driven prefetch
286	 * @pipe: Pointer to software pipe context
287	 * @fmt: format used by the sw pipe
288	 * @enable: whether the CDP should be enabled for this pipe
289	 */
290	void (*setup_cdp)(struct dpu_sw_pipe *pipe,
291			  const struct dpu_format *fmt,
292			  bool enable);
293};
294
295/**
296 * struct dpu_hw_sspp - pipe description
297 * @base: hardware block base structure
298 * @hw: block hardware details
299 * @ubwc: UBWC configuration data
300 * @idx: pipe index
301 * @cap: pointer to layer_cfg
302 * @ops: pointer to operations possible for this pipe
303 */
304struct dpu_hw_sspp {
305	struct dpu_hw_blk base;
306	struct dpu_hw_blk_reg_map hw;
307	const struct msm_mdss_data *ubwc;
308
309	/* Pipe */
310	enum dpu_sspp idx;
311	const struct dpu_sspp_cfg *cap;
312
313	/* Ops */
314	struct dpu_hw_sspp_ops ops;
315};
316
317struct dpu_kms;
318/**
319 * dpu_hw_sspp_init() - Initializes the sspp hw driver object.
320 * Should be called once before accessing every pipe.
321 * @dev:  Corresponding device for devres management
322 * @cfg:  Pipe catalog entry for which driver object is required
323 * @addr: Mapped register io address of MDP
324 * @mdss_data: UBWC / MDSS configuration data
325 * @mdss_rev: dpu core's major and minor versions
326 */
327struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
328				     const struct dpu_sspp_cfg *cfg,
329				     void __iomem *addr,
330				     const struct msm_mdss_data *mdss_data,
331				     const struct dpu_mdss_version *mdss_rev);
332
333int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
334			      struct dentry *entry);
335
336#endif /*_DPU_HW_SSPP_H */
337
338