1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7#include "dpu_hwio.h" 8#include "dpu_hw_catalog.h" 9#include "dpu_hw_intf.h" 10#include "dpu_kms.h" 11#include "dpu_trace.h" 12 13#include <linux/iopoll.h> 14 15#include <drm/drm_managed.h> 16 17#define INTF_TIMING_ENGINE_EN 0x000 18#define INTF_CONFIG 0x004 19#define INTF_HSYNC_CTL 0x008 20#define INTF_VSYNC_PERIOD_F0 0x00C 21#define INTF_VSYNC_PERIOD_F1 0x010 22#define INTF_VSYNC_PULSE_WIDTH_F0 0x014 23#define INTF_VSYNC_PULSE_WIDTH_F1 0x018 24#define INTF_DISPLAY_V_START_F0 0x01C 25#define INTF_DISPLAY_V_START_F1 0x020 26#define INTF_DISPLAY_V_END_F0 0x024 27#define INTF_DISPLAY_V_END_F1 0x028 28#define INTF_ACTIVE_V_START_F0 0x02C 29#define INTF_ACTIVE_V_START_F1 0x030 30#define INTF_ACTIVE_V_END_F0 0x034 31#define INTF_ACTIVE_V_END_F1 0x038 32#define INTF_DISPLAY_HCTL 0x03C 33#define INTF_ACTIVE_HCTL 0x040 34#define INTF_BORDER_COLOR 0x044 35#define INTF_UNDERFLOW_COLOR 0x048 36#define INTF_HSYNC_SKEW 0x04C 37#define INTF_POLARITY_CTL 0x050 38#define INTF_TEST_CTL 0x054 39#define INTF_TP_COLOR0 0x058 40#define INTF_TP_COLOR1 0x05C 41#define INTF_CONFIG2 0x060 42#define INTF_DISPLAY_DATA_HCTL 0x064 43#define INTF_ACTIVE_DATA_HCTL 0x068 44 45#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 46#define INTF_PANEL_FORMAT 0x090 47 48#define INTF_FRAME_LINE_COUNT_EN 0x0A8 49#define INTF_FRAME_COUNT 0x0AC 50#define INTF_LINE_COUNT 0x0B0 51 52#define INTF_DEFLICKER_CONFIG 0x0F0 53#define INTF_DEFLICKER_STRNG_COEFF 0x0F4 54#define INTF_DEFLICKER_WEAK_COEFF 0x0F8 55 56#define INTF_TPG_ENABLE 0x100 57#define INTF_TPG_MAIN_CONTROL 0x104 58#define INTF_TPG_VIDEO_CONFIG 0x108 59#define INTF_TPG_COMPONENT_LIMITS 0x10C 60#define INTF_TPG_RECTANGLE 0x110 61#define INTF_TPG_INITIAL_VALUE 0x114 62#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 63#define INTF_TPG_RGB_MAPPING 0x11C 64#define INTF_PROG_FETCH_START 0x170 65#define INTF_PROG_ROT_START 0x174 66 67#define INTF_MISR_CTRL 0x180 68#define INTF_MISR_SIGNATURE 0x184 69 70#define INTF_MUX 0x25C 71#define INTF_STATUS 0x26C 72#define INTF_AVR_CONTROL 0x270 73#define INTF_AVR_MODE 0x274 74#define INTF_AVR_TRIGGER 0x278 75#define INTF_AVR_VTOTAL 0x27C 76#define INTF_TEAR_MDP_VSYNC_SEL 0x280 77#define INTF_TEAR_TEAR_CHECK_EN 0x284 78#define INTF_TEAR_SYNC_CONFIG_VSYNC 0x288 79#define INTF_TEAR_SYNC_CONFIG_HEIGHT 0x28C 80#define INTF_TEAR_SYNC_WRCOUNT 0x290 81#define INTF_TEAR_VSYNC_INIT_VAL 0x294 82#define INTF_TEAR_INT_COUNT_VAL 0x298 83#define INTF_TEAR_SYNC_THRESH 0x29C 84#define INTF_TEAR_START_POS 0x2A0 85#define INTF_TEAR_RD_PTR_IRQ 0x2A4 86#define INTF_TEAR_WR_PTR_IRQ 0x2A8 87#define INTF_TEAR_OUT_LINE_COUNT 0x2AC 88#define INTF_TEAR_LINE_COUNT 0x2B0 89#define INTF_TEAR_AUTOREFRESH_CONFIG 0x2B4 90 91#define INTF_CFG_ACTIVE_H_EN BIT(29) 92#define INTF_CFG_ACTIVE_V_EN BIT(30) 93 94#define INTF_CFG2_DATABUS_WIDEN BIT(0) 95#define INTF_CFG2_DATA_HCTL_EN BIT(4) 96#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) 97 98 99static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 100 const struct dpu_hw_intf_timing_params *p, 101 const struct dpu_format *fmt) 102{ 103 struct dpu_hw_blk_reg_map *c = &ctx->hw; 104 u32 hsync_period, vsync_period; 105 u32 display_v_start, display_v_end; 106 u32 hsync_start_x, hsync_end_x; 107 u32 hsync_data_start_x, hsync_data_end_x; 108 u32 active_h_start, active_h_end; 109 u32 active_v_start, active_v_end; 110 u32 active_hctl, display_hctl, hsync_ctl; 111 u32 polarity_ctl, den_polarity; 112 u32 panel_format; 113 u32 intf_cfg, intf_cfg2 = 0; 114 u32 display_data_hctl = 0, active_data_hctl = 0; 115 u32 data_width; 116 bool dp_intf = false; 117 118 /* read interface_cfg */ 119 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 120 121 if (ctx->cap->type == INTF_DP) 122 dp_intf = true; 123 124 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 125 p->h_front_porch; 126 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 127 p->v_front_porch; 128 129 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 130 hsync_period) + p->hsync_skew; 131 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 132 p->hsync_skew - 1; 133 134 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 135 hsync_end_x = hsync_period - p->h_front_porch - 1; 136 137 if (p->width != p->xres) { /* border fill added */ 138 active_h_start = hsync_start_x; 139 active_h_end = active_h_start + p->xres - 1; 140 } else { 141 active_h_start = 0; 142 active_h_end = 0; 143 } 144 145 if (p->height != p->yres) { /* border fill added */ 146 active_v_start = display_v_start; 147 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 148 } else { 149 active_v_start = 0; 150 active_v_end = 0; 151 } 152 153 if (active_h_end) { 154 active_hctl = (active_h_end << 16) | active_h_start; 155 intf_cfg |= INTF_CFG_ACTIVE_H_EN; 156 } else { 157 active_hctl = 0; 158 } 159 160 if (active_v_end) 161 intf_cfg |= INTF_CFG_ACTIVE_V_EN; 162 163 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 164 display_hctl = (hsync_end_x << 16) | hsync_start_x; 165 166 if (p->wide_bus_en) 167 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; 168 169 data_width = p->width; 170 171 hsync_data_start_x = hsync_start_x; 172 hsync_data_end_x = hsync_start_x + data_width - 1; 173 174 display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x; 175 176 if (dp_intf) { 177 /* DP timing adjustment */ 178 display_v_start += p->hsync_pulse_width + p->h_back_porch; 179 display_v_end -= p->h_front_porch; 180 181 active_h_start = hsync_start_x; 182 active_h_end = active_h_start + p->xres - 1; 183 active_v_start = display_v_start; 184 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 185 186 active_hctl = (active_h_end << 16) | active_h_start; 187 display_hctl = active_hctl; 188 189 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; 190 } 191 192 den_polarity = 0; 193 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 194 (p->vsync_polarity << 1) | /* VSYNC Polarity */ 195 (p->hsync_polarity << 0); /* HSYNC Polarity */ 196 197 if (!DPU_FORMAT_IS_YUV(fmt)) 198 panel_format = (fmt->bits[C0_G_Y] | 199 (fmt->bits[C1_B_Cb] << 2) | 200 (fmt->bits[C2_R_Cr] << 4) | 201 (0x21 << 8)); 202 else 203 /* Interface treats all the pixel data in RGB888 format */ 204 panel_format = (COLOR_8BIT | 205 (COLOR_8BIT << 2) | 206 (COLOR_8BIT << 4) | 207 (0x21 << 8)); 208 209 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 210 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 211 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 212 p->vsync_pulse_width * hsync_period); 213 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 214 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 215 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 216 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 217 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 218 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 219 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 220 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 221 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 222 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 223 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 224 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 225 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 226 if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { 227 /* 228 * DATA_HCTL_EN controls data timing which can be different from 229 * video timing. It is recommended to enable it for all cases, except 230 * if compression is enabled in 1 pixel per clock mode 231 */ 232 if (!(p->compression_en && !p->wide_bus_en)) 233 intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; 234 235 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); 236 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); 237 DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); 238 } 239} 240 241static void dpu_hw_intf_enable_timing_engine( 242 struct dpu_hw_intf *intf, 243 u8 enable) 244{ 245 struct dpu_hw_blk_reg_map *c = &intf->hw; 246 /* Note: Display interface select is handled in top block hw layer */ 247 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 248} 249 250static void dpu_hw_intf_setup_prg_fetch( 251 struct dpu_hw_intf *intf, 252 const struct dpu_hw_intf_prog_fetch *fetch) 253{ 254 struct dpu_hw_blk_reg_map *c = &intf->hw; 255 int fetch_enable; 256 257 /* 258 * Fetch should always be outside the active lines. If the fetching 259 * is programmed within active region, hardware behavior is unknown. 260 */ 261 262 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 263 if (fetch->enable) { 264 fetch_enable |= BIT(31); 265 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 266 fetch->fetch_start); 267 } else { 268 fetch_enable &= ~BIT(31); 269 } 270 271 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 272} 273 274static void dpu_hw_intf_bind_pingpong_blk( 275 struct dpu_hw_intf *intf, 276 const enum dpu_pingpong pp) 277{ 278 struct dpu_hw_blk_reg_map *c = &intf->hw; 279 u32 mux_cfg; 280 281 mux_cfg = DPU_REG_READ(c, INTF_MUX); 282 mux_cfg &= ~0xf; 283 284 if (pp) 285 mux_cfg |= (pp - PINGPONG_0) & 0x7; 286 else 287 mux_cfg |= 0xf; 288 289 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); 290} 291 292static void dpu_hw_intf_get_status( 293 struct dpu_hw_intf *intf, 294 struct dpu_hw_intf_status *s) 295{ 296 struct dpu_hw_blk_reg_map *c = &intf->hw; 297 unsigned long cap = intf->cap->features; 298 299 if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) 300 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); 301 else 302 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 303 304 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); 305 if (s->is_en) { 306 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 307 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 308 } else { 309 s->line_count = 0; 310 s->frame_count = 0; 311 } 312} 313 314static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 315{ 316 struct dpu_hw_blk_reg_map *c; 317 318 if (!intf) 319 return 0; 320 321 c = &intf->hw; 322 323 return DPU_REG_READ(c, INTF_LINE_COUNT); 324} 325 326static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf) 327{ 328 dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1); 329} 330 331static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) 332{ 333 return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); 334} 335 336static int dpu_hw_intf_enable_te(struct dpu_hw_intf *intf, 337 struct dpu_hw_tear_check *te) 338{ 339 struct dpu_hw_blk_reg_map *c; 340 int cfg; 341 342 if (!intf) 343 return -EINVAL; 344 345 c = &intf->hw; 346 347 cfg = BIT(19); /* VSYNC_COUNTER_EN */ 348 if (te->hw_vsync_mode) 349 cfg |= BIT(20); 350 351 cfg |= te->vsync_count; 352 353 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); 354 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); 355 DPU_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val); 356 DPU_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq); 357 DPU_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos); 358 DPU_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, 359 ((te->sync_threshold_continue << 16) | 360 te->sync_threshold_start)); 361 DPU_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, 362 (te->start_pos + te->sync_threshold_start + 1)); 363 364 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 1); 365 366 return 0; 367} 368 369static void dpu_hw_intf_setup_autorefresh_config(struct dpu_hw_intf *intf, 370 u32 frame_count, bool enable) 371{ 372 struct dpu_hw_blk_reg_map *c; 373 u32 refresh_cfg; 374 375 c = &intf->hw; 376 refresh_cfg = DPU_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG); 377 if (enable) 378 refresh_cfg = BIT(31) | frame_count; 379 else 380 refresh_cfg &= ~BIT(31); 381 382 DPU_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg); 383} 384 385/* 386 * dpu_hw_intf_get_autorefresh_config - Get autorefresh config from HW 387 * @intf: DPU intf structure 388 * @frame_count: Used to return the current frame count from hw 389 * 390 * Returns: True if autorefresh enabled, false if disabled. 391 */ 392static bool dpu_hw_intf_get_autorefresh_config(struct dpu_hw_intf *intf, 393 u32 *frame_count) 394{ 395 u32 val = DPU_REG_READ(&intf->hw, INTF_TEAR_AUTOREFRESH_CONFIG); 396 397 if (frame_count != NULL) 398 *frame_count = val & 0xffff; 399 return !!((val & BIT(31)) >> 31); 400} 401 402static int dpu_hw_intf_disable_te(struct dpu_hw_intf *intf) 403{ 404 struct dpu_hw_blk_reg_map *c; 405 406 if (!intf) 407 return -EINVAL; 408 409 c = &intf->hw; 410 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 0); 411 return 0; 412} 413 414static int dpu_hw_intf_connect_external_te(struct dpu_hw_intf *intf, 415 bool enable_external_te) 416{ 417 struct dpu_hw_blk_reg_map *c = &intf->hw; 418 u32 cfg; 419 int orig; 420 421 if (!intf) 422 return -EINVAL; 423 424 c = &intf->hw; 425 cfg = DPU_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC); 426 orig = (bool)(cfg & BIT(20)); 427 if (enable_external_te) 428 cfg |= BIT(20); 429 else 430 cfg &= ~BIT(20); 431 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); 432 trace_dpu_intf_connect_ext_te(intf->idx - INTF_0, cfg); 433 434 return orig; 435} 436 437static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf, 438 struct dpu_hw_pp_vsync_info *info) 439{ 440 struct dpu_hw_blk_reg_map *c = &intf->hw; 441 u32 val; 442 443 if (!intf || !info) 444 return -EINVAL; 445 446 c = &intf->hw; 447 448 val = DPU_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL); 449 info->rd_ptr_init_val = val & 0xffff; 450 451 val = DPU_REG_READ(c, INTF_TEAR_INT_COUNT_VAL); 452 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; 453 info->rd_ptr_line_count = val & 0xffff; 454 455 val = DPU_REG_READ(c, INTF_TEAR_LINE_COUNT); 456 info->wr_ptr_line_count = val & 0xffff; 457 458 val = DPU_REG_READ(c, INTF_FRAME_COUNT); 459 info->intf_frame_count = val; 460 461 return 0; 462} 463 464static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf, 465 u32 vsync_source) 466{ 467 struct dpu_hw_blk_reg_map *c; 468 469 if (!intf) 470 return; 471 472 c = &intf->hw; 473 474 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); 475} 476 477static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, 478 uint32_t encoder_id, u16 vdisplay) 479{ 480 struct dpu_hw_pp_vsync_info info; 481 int trial = 0; 482 483 /* If autorefresh is already disabled, we have nothing to do */ 484 if (!dpu_hw_intf_get_autorefresh_config(intf, NULL)) 485 return; 486 487 /* 488 * If autorefresh is enabled, disable it and make sure it is safe to 489 * proceed with current frame commit/push. Sequence followed is, 490 * 1. Disable TE 491 * 2. Disable autorefresh config 492 * 4. Poll for frame transfer ongoing to be false 493 * 5. Enable TE back 494 */ 495 496 dpu_hw_intf_connect_external_te(intf, false); 497 dpu_hw_intf_setup_autorefresh_config(intf, 0, false); 498 499 do { 500 udelay(DPU_ENC_MAX_POLL_TIMEOUT_US); 501 if ((trial * DPU_ENC_MAX_POLL_TIMEOUT_US) 502 > (KICKOFF_TIMEOUT_MS * USEC_PER_MSEC)) { 503 DPU_ERROR("enc%d intf%d disable autorefresh failed\n", 504 encoder_id, intf->idx - INTF_0); 505 break; 506 } 507 508 trial++; 509 510 dpu_hw_intf_get_vsync_info(intf, &info); 511 } while (info.wr_ptr_line_count > 0 && 512 info.wr_ptr_line_count < vdisplay); 513 514 dpu_hw_intf_connect_external_te(intf, true); 515 516 DPU_DEBUG("enc%d intf%d disabled autorefresh\n", 517 encoder_id, intf->idx - INTF_0); 518 519} 520 521static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, 522 struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) 523{ 524 u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); 525 526 if (cmd_mode_cfg->data_compress) 527 intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; 528 529 if (cmd_mode_cfg->wide_bus_en) 530 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; 531 532 DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); 533} 534 535struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 536 const struct dpu_intf_cfg *cfg, 537 void __iomem *addr, 538 const struct dpu_mdss_version *mdss_rev) 539{ 540 struct dpu_hw_intf *c; 541 542 if (cfg->type == INTF_NONE) { 543 DPU_DEBUG("Skip intf %d with type NONE\n", cfg->id - INTF_0); 544 return NULL; 545 } 546 547 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL); 548 if (!c) 549 return ERR_PTR(-ENOMEM); 550 551 c->hw.blk_addr = addr + cfg->base; 552 c->hw.log_mask = DPU_DBG_MASK_INTF; 553 554 /* 555 * Assign ops 556 */ 557 c->idx = cfg->id; 558 c->cap = cfg; 559 560 c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; 561 c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 562 c->ops.get_status = dpu_hw_intf_get_status; 563 c->ops.enable_timing = dpu_hw_intf_enable_timing_engine; 564 c->ops.get_line_count = dpu_hw_intf_get_line_count; 565 c->ops.setup_misr = dpu_hw_intf_setup_misr; 566 c->ops.collect_misr = dpu_hw_intf_collect_misr; 567 568 if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) 569 c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; 570 571 /* INTF TE is only for DSI interfaces */ 572 if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) { 573 WARN_ON(!cfg->intr_tear_rd_ptr); 574 575 c->ops.enable_tearcheck = dpu_hw_intf_enable_te; 576 c->ops.disable_tearcheck = dpu_hw_intf_disable_te; 577 c->ops.connect_external_te = dpu_hw_intf_connect_external_te; 578 c->ops.vsync_sel = dpu_hw_intf_vsync_sel; 579 c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh; 580 } 581 582 /* Technically, INTF_CONFIG2 is present for DPU 5.0+, but 583 * we can configure it for DPU 7.0+ since the wide bus and DSC flags 584 * would not be set for DPU < 7.0 anyways 585 */ 586 if (mdss_rev->core_major_ver >= 7) 587 c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; 588 589 return c; 590} 591