1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 4 */ 5 6#ifndef __MESON_REGISTERS_H 7#define __MESON_REGISTERS_H 8 9#include <linux/io.h> 10 11/* Shift all registers by 2 */ 12#define _REG(reg) ((reg) << 2) 13 14#define writel_bits_relaxed(mask, val, addr) \ 15 writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr) 16 17/* vpp2 */ 18#define VPP2_DUMMY_DATA 0x1900 19#define VPP2_LINE_IN_LENGTH 0x1901 20#define VPP2_PIC_IN_HEIGHT 0x1902 21#define VPP2_SCALE_COEF_IDX 0x1903 22#define VPP2_SCALE_COEF 0x1904 23#define VPP2_VSC_REGION12_STARTP 0x1905 24#define VPP2_VSC_REGION34_STARTP 0x1906 25#define VPP2_VSC_REGION4_ENDP 0x1907 26#define VPP2_VSC_START_PHASE_STEP 0x1908 27#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 28#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 29#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 30#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 31#define VPP2_VSC_PHASE_CTRL 0x190d 32#define VPP2_VSC_INI_PHASE 0x190e 33#define VPP2_HSC_REGION12_STARTP 0x1910 34#define VPP2_HSC_REGION34_STARTP 0x1911 35#define VPP2_HSC_REGION4_ENDP 0x1912 36#define VPP2_HSC_START_PHASE_STEP 0x1913 37#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 38#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 39#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 40#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 41#define VPP2_HSC_PHASE_CTRL 0x1918 42#define VPP2_SC_MISC 0x1919 43#define VPP2_PREBLEND_VD1_H_START_END 0x191a 44#define VPP2_PREBLEND_VD1_V_START_END 0x191b 45#define VPP2_POSTBLEND_VD1_H_START_END 0x191c 46#define VPP2_POSTBLEND_VD1_V_START_END 0x191d 47#define VPP2_PREBLEND_H_SIZE 0x1920 48#define VPP2_POSTBLEND_H_SIZE 0x1921 49#define VPP2_HOLD_LINES 0x1922 50#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 51#define VPP2_PREBLEND_CURRENT_XY 0x1924 52#define VPP2_POSTBLEND_CURRENT_XY 0x1925 53#define VPP2_MISC 0x1926 54#define VPP2_OFIFO_SIZE 0x1927 55#define VPP2_FIFO_STATUS 0x1928 56#define VPP2_SMOKE_CTRL 0x1929 57#define VPP2_SMOKE1_VAL 0x192a 58#define VPP2_SMOKE2_VAL 0x192b 59#define VPP2_SMOKE1_H_START_END 0x192d 60#define VPP2_SMOKE1_V_START_END 0x192e 61#define VPP2_SMOKE2_H_START_END 0x192f 62#define VPP2_SMOKE2_V_START_END 0x1930 63#define VPP2_SCO_FIFO_CTRL 0x1933 64#define VPP2_HSC_PHASE_CTRL1 0x1934 65#define VPP2_HSC_INI_PAT_CTRL 0x1935 66#define VPP2_VADJ_CTRL 0x1940 67#define VPP2_VADJ1_Y 0x1941 68#define VPP2_VADJ1_MA_MB 0x1942 69#define VPP2_VADJ1_MC_MD 0x1943 70#define VPP2_VADJ2_Y 0x1944 71#define VPP2_VADJ2_MA_MB 0x1945 72#define VPP2_VADJ2_MC_MD 0x1946 73#define VPP2_MATRIX_PROBE_COLOR 0x195c 74#define VPP2_MATRIX_HL_COLOR 0x195d 75#define VPP2_MATRIX_PROBE_POS 0x195e 76#define VPP2_MATRIX_CTRL 0x195f 77#define VPP2_MATRIX_COEF00_01 0x1960 78#define VPP2_MATRIX_COEF02_10 0x1961 79#define VPP2_MATRIX_COEF11_12 0x1962 80#define VPP2_MATRIX_COEF20_21 0x1963 81#define VPP2_MATRIX_COEF22 0x1964 82#define VPP2_MATRIX_OFFSET0_1 0x1965 83#define VPP2_MATRIX_OFFSET2 0x1966 84#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 85#define VPP2_MATRIX_PRE_OFFSET2 0x1968 86#define VPP2_DUMMY_DATA1 0x1969 87#define VPP2_GAINOFF_CTRL0 0x196a 88#define VPP2_GAINOFF_CTRL1 0x196b 89#define VPP2_GAINOFF_CTRL2 0x196c 90#define VPP2_GAINOFF_CTRL3 0x196d 91#define VPP2_GAINOFF_CTRL4 0x196e 92#define VPP2_CHROMA_ADDR_PORT 0x1970 93#define VPP2_CHROMA_DATA_PORT 0x1971 94#define VPP2_GCLK_CTRL0 0x1972 95#define VPP2_GCLK_CTRL1 0x1973 96#define VPP2_SC_GCLK_CTRL 0x1974 97#define VPP2_MISC1 0x1976 98#define VPP2_DNLP_CTRL_00 0x1981 99#define VPP2_DNLP_CTRL_01 0x1982 100#define VPP2_DNLP_CTRL_02 0x1983 101#define VPP2_DNLP_CTRL_03 0x1984 102#define VPP2_DNLP_CTRL_04 0x1985 103#define VPP2_DNLP_CTRL_05 0x1986 104#define VPP2_DNLP_CTRL_06 0x1987 105#define VPP2_DNLP_CTRL_07 0x1988 106#define VPP2_DNLP_CTRL_08 0x1989 107#define VPP2_DNLP_CTRL_09 0x198a 108#define VPP2_DNLP_CTRL_10 0x198b 109#define VPP2_DNLP_CTRL_11 0x198c 110#define VPP2_DNLP_CTRL_12 0x198d 111#define VPP2_DNLP_CTRL_13 0x198e 112#define VPP2_DNLP_CTRL_14 0x198f 113#define VPP2_DNLP_CTRL_15 0x1990 114#define VPP2_VE_ENABLE_CTRL 0x19a1 115#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 116#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 117#define VPP2_VE_H_V_SIZE 0x19a4 118#define VPP2_VDO_MEAS_CTRL 0x19a8 119#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 120#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 121#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 122#define VPP2_OSD_VSC_INI_PHASE 0x19c1 123#define VPP2_OSD_VSC_CTRL0 0x19c2 124#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 125#define VPP2_OSD_HSC_INI_PHASE 0x19c4 126#define VPP2_OSD_HSC_CTRL0 0x19c5 127#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 128#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 129#define VPP2_OSD_SC_CTRL0 0x19c8 130#define VPP2_OSD_SCI_WH_M1 0x19c9 131#define VPP2_OSD_SCO_H_START_END 0x19ca 132#define VPP2_OSD_SCO_V_START_END 0x19cb 133#define VPP2_OSD_SCALE_COEF_IDX 0x19cc 134#define VPP2_OSD_SCALE_COEF 0x19cd 135#define VPP2_INT_LINE_NUM 0x19ce 136 137/* viu */ 138#define VIU_ADDR_START 0x1a00 139#define VIU_ADDR_END 0x1aff 140#define VIU_SW_RESET 0x1a01 141#define VIU_SW_RESET_OSD1_AFBCD BIT(31) 142#define VIU_SW_RESET_G12A_OSD1_AFBCD BIT(21) 143#define VIU_SW_RESET_G12A_AFBC_ARB BIT(19) 144#define VIU_SW_RESET_OSD1 BIT(0) 145#define VIU_MISC_CTRL0 0x1a06 146#define VIU_CTRL0_VD1_AFBC_MASK 0x170000 147#define VIU_CTRL0_AFBC_TO_VD1 BIT(20) 148#define VIU_MISC_CTRL1 0x1a07 149#define MALI_AFBC_MISC GENMASK(15, 8) 150#define D2D3_INTF_LENGTH 0x1a08 151#define D2D3_INTF_CTRL0 0x1a09 152#define VD1_AFBCD0_MISC_CTRL 0x1a0a 153#define VD1_AXI_SEL_AFBC (1 << 12) 154#define AFBC_VD1_SEL (1 << 10) 155#define VD2_AFBCD1_MISC_CTRL 0x1a0b 156#define VIU_OSD1_CTRL_STAT 0x1a10 157#define VIU_OSD1_OSD_BLK_ENABLE BIT(0) 158#define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2) 159#define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8) 160#define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8) 161#define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8) 162#define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8) 163#define VIU_OSD1_OSD_ENABLE BIT(21) 164#define VIU_OSD1_CFG_SYN_EN BIT(31) 165#define VIU_OSD1_CTRL_STAT2 0x1a2d 166#define VIU_OSD1_COLOR_ADDR 0x1a11 167#define VIU_OSD1_COLOR 0x1a12 168#define VIU_OSD1_TCOLOR_AG0 0x1a17 169#define VIU_OSD1_TCOLOR_AG1 0x1a18 170#define VIU_OSD1_TCOLOR_AG2 0x1a19 171#define VIU_OSD1_TCOLOR_AG3 0x1a1a 172#define VIU_OSD1_BLK0_CFG_W0 0x1a1b 173#define VIU_OSD1_BLK1_CFG_W0 0x1a1f 174#define VIU_OSD1_BLK2_CFG_W0 0x1a23 175#define VIU_OSD1_BLK3_CFG_W0 0x1a27 176#define VIU_OSD1_BLK0_CFG_W1 0x1a1c 177#define VIU_OSD1_BLK1_CFG_W1 0x1a20 178#define VIU_OSD1_BLK2_CFG_W1 0x1a24 179#define VIU_OSD1_BLK3_CFG_W1 0x1a28 180#define VIU_OSD1_BLK0_CFG_W2 0x1a1d 181#define VIU_OSD1_BLK1_CFG_W2 0x1a21 182#define VIU_OSD1_BLK2_CFG_W2 0x1a25 183#define VIU_OSD1_BLK3_CFG_W2 0x1a29 184#define VIU_OSD1_BLK0_CFG_W3 0x1a1e 185#define VIU_OSD1_BLK1_CFG_W3 0x1a22 186#define VIU_OSD1_BLK2_CFG_W3 0x1a26 187#define VIU_OSD1_BLK3_CFG_W3 0x1a2a 188#define VIU_OSD1_BLK0_CFG_W4 0x1a13 189#define VIU_OSD1_BLK1_CFG_W4 0x1a14 190#define VIU_OSD1_BLK2_CFG_W4 0x1a15 191#define VIU_OSD1_BLK3_CFG_W4 0x1a16 192#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 193#define VIU_OSD1_TEST_RDDATA 0x1a2c 194#define VIU_OSD1_PROT_CTRL 0x1a2e 195#define VIU_OSD1_MALI_UNPACK_CTRL 0x1a2f 196#define VIU_OSD1_MALI_UNPACK_EN BIT(31) 197#define VIU_OSD1_MALI_AFBCD_R_REORDER GENMASK(15, 12) 198#define VIU_OSD1_MALI_AFBCD_G_REORDER GENMASK(11, 8) 199#define VIU_OSD1_MALI_AFBCD_B_REORDER GENMASK(7, 4) 200#define VIU_OSD1_MALI_AFBCD_A_REORDER GENMASK(3, 0) 201#define VIU_OSD1_MALI_REORDER_R 1 202#define VIU_OSD1_MALI_REORDER_G 2 203#define VIU_OSD1_MALI_REORDER_B 3 204#define VIU_OSD1_MALI_REORDER_A 4 205#define VIU_OSD2_CTRL_STAT 0x1a30 206#define VIU_OSD2_CTRL_STAT2 0x1a4d 207#define VIU_OSD2_COLOR_ADDR 0x1a31 208#define VIU_OSD2_COLOR 0x1a32 209#define VIU_OSD2_HL1_H_START_END 0x1a33 210#define VIU_OSD2_HL1_V_START_END 0x1a34 211#define VIU_OSD2_HL2_H_START_END 0x1a35 212#define VIU_OSD2_HL2_V_START_END 0x1a36 213#define VIU_OSD2_TCOLOR_AG0 0x1a37 214#define VIU_OSD2_TCOLOR_AG1 0x1a38 215#define VIU_OSD2_TCOLOR_AG2 0x1a39 216#define VIU_OSD2_TCOLOR_AG3 0x1a3a 217#define VIU_OSD2_BLK0_CFG_W0 0x1a3b 218#define VIU_OSD2_BLK1_CFG_W0 0x1a3f 219#define VIU_OSD2_BLK2_CFG_W0 0x1a43 220#define VIU_OSD2_BLK3_CFG_W0 0x1a47 221#define VIU_OSD2_BLK0_CFG_W1 0x1a3c 222#define VIU_OSD2_BLK1_CFG_W1 0x1a40 223#define VIU_OSD2_BLK2_CFG_W1 0x1a44 224#define VIU_OSD2_BLK3_CFG_W1 0x1a48 225#define VIU_OSD2_BLK0_CFG_W2 0x1a3d 226#define VIU_OSD2_BLK1_CFG_W2 0x1a41 227#define VIU_OSD2_BLK2_CFG_W2 0x1a45 228#define VIU_OSD2_BLK3_CFG_W2 0x1a49 229#define VIU_OSD2_BLK0_CFG_W3 0x1a3e 230#define VIU_OSD2_BLK1_CFG_W3 0x1a42 231#define VIU_OSD2_BLK2_CFG_W3 0x1a46 232#define VIU_OSD2_BLK3_CFG_W3 0x1a4a 233#define VIU_OSD2_BLK0_CFG_W4 0x1a64 234#define VIU_OSD2_BLK1_CFG_W4 0x1a65 235#define VIU_OSD2_BLK2_CFG_W4 0x1a66 236#define VIU_OSD2_BLK3_CFG_W4 0x1a67 237#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 238#define VIU_OSD2_TEST_RDDATA 0x1a4c 239#define VIU_OSD2_PROT_CTRL 0x1a4e 240#define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd 241#define VIU_OSD2_DIMM_CTRL 0x1acf 242 243#define VIU_OSD3_CTRL_STAT 0x3d80 244#define VIU_OSD3_CTRL_STAT2 0x3d81 245#define VIU_OSD3_COLOR_ADDR 0x3d82 246#define VIU_OSD3_COLOR 0x3d83 247#define VIU_OSD3_TCOLOR_AG0 0x3d84 248#define VIU_OSD3_TCOLOR_AG1 0x3d85 249#define VIU_OSD3_TCOLOR_AG2 0x3d86 250#define VIU_OSD3_TCOLOR_AG3 0x3d87 251#define VIU_OSD3_BLK0_CFG_W0 0x3d88 252#define VIU_OSD3_BLK0_CFG_W1 0x3d8c 253#define VIU_OSD3_BLK0_CFG_W2 0x3d90 254#define VIU_OSD3_BLK0_CFG_W3 0x3d94 255#define VIU_OSD3_BLK0_CFG_W4 0x3d98 256#define VIU_OSD3_BLK1_CFG_W4 0x3d99 257#define VIU_OSD3_BLK2_CFG_W4 0x3d9a 258#define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c 259#define VIU_OSD3_TEST_RDDATA 0x3d9d 260#define VIU_OSD3_PROT_CTRL 0x3d9e 261#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f 262#define VIU_OSD3_DIMM_CTRL 0x3da0 263 264#define VIU_OSD_DDR_PRIORITY_URGENT BIT(0) 265#define VIU_OSD_HOLD_FIFO_LINES(lines) ((lines & 0x1f) << 5) 266#define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12) 267#define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22) 268#define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24) 269#define VIU_OSD_BURST_LENGTH_24 (0x0 << 31 | 0x0 << 10) 270#define VIU_OSD_BURST_LENGTH_32 (0x0 << 31 | 0x1 << 10) 271#define VIU_OSD_BURST_LENGTH_48 (0x0 << 31 | 0x2 << 10) 272#define VIU_OSD_BURST_LENGTH_64 (0x0 << 31 | 0x3 << 10) 273#define VIU_OSD_BURST_LENGTH_96 (0x1 << 31 | 0x0 << 10) 274#define VIU_OSD_BURST_LENGTH_128 (0x1 << 31 | 0x1 << 10) 275 276#define VD1_IF0_GEN_REG 0x1a50 277#define VD1_IF0_CANVAS0 0x1a51 278#define VD1_IF0_CANVAS1 0x1a52 279#define VD1_IF0_LUMA_X0 0x1a53 280#define VD1_IF0_LUMA_Y0 0x1a54 281#define VD1_IF0_CHROMA_X0 0x1a55 282#define VD1_IF0_CHROMA_Y0 0x1a56 283#define VD1_IF0_LUMA_X1 0x1a57 284#define VD1_IF0_LUMA_Y1 0x1a58 285#define VD1_IF0_CHROMA_X1 0x1a59 286#define VD1_IF0_CHROMA_Y1 0x1a5a 287#define VD1_IF0_RPT_LOOP 0x1a5b 288#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 289#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 290#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 291#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 292#define VD1_IF0_LUMA_PSEL 0x1a60 293#define VD1_IF0_CHROMA_PSEL 0x1a61 294#define VD1_IF0_DUMMY_PIXEL 0x1a62 295#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 296#define VD1_IF0_RANGE_MAP_Y 0x1a6a 297#define VD1_IF0_RANGE_MAP_CB 0x1a6b 298#define VD1_IF0_RANGE_MAP_CR 0x1a6c 299#define VD1_IF0_GEN_REG2 0x1a6d 300#define VD1_IF0_PROT_CNTL 0x1a6e 301#define VIU_VD1_FMT_CTRL 0x1a68 302#define VIU_VD1_FMT_W 0x1a69 303#define VD2_IF0_GEN_REG 0x1a70 304#define VD2_IF0_CANVAS0 0x1a71 305#define VD2_IF0_CANVAS1 0x1a72 306#define VD2_IF0_LUMA_X0 0x1a73 307#define VD2_IF0_LUMA_Y0 0x1a74 308#define VD2_IF0_CHROMA_X0 0x1a75 309#define VD2_IF0_CHROMA_Y0 0x1a76 310#define VD2_IF0_LUMA_X1 0x1a77 311#define VD2_IF0_LUMA_Y1 0x1a78 312#define VD2_IF0_CHROMA_X1 0x1a79 313#define VD2_IF0_CHROMA_Y1 0x1a7a 314#define VD2_IF0_RPT_LOOP 0x1a7b 315#define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 316#define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 317#define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 318#define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 319#define VD2_IF0_LUMA_PSEL 0x1a80 320#define VD2_IF0_CHROMA_PSEL 0x1a81 321#define VD2_IF0_DUMMY_PIXEL 0x1a82 322#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 323#define VD2_IF0_RANGE_MAP_Y 0x1a8a 324#define VD2_IF0_RANGE_MAP_CB 0x1a8b 325#define VD2_IF0_RANGE_MAP_CR 0x1a8c 326#define VD2_IF0_GEN_REG2 0x1a8d 327#define VD2_IF0_PROT_CNTL 0x1a8e 328#define VIU_VD2_FMT_CTRL 0x1a88 329#define VIU_VD2_FMT_W 0x1a89 330 331/* VIU Matrix Registers */ 332#define VIU_OSD1_MATRIX_CTRL 0x1a90 333#define VIU_OSD1_MATRIX_COEF00_01 0x1a91 334#define VIU_OSD1_MATRIX_COEF02_10 0x1a92 335#define VIU_OSD1_MATRIX_COEF11_12 0x1a93 336#define VIU_OSD1_MATRIX_COEF20_21 0x1a94 337#define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 338#define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 339#define VIU_OSD1_MATRIX_OFFSET2 0x1a97 340#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 341#define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 342#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d 343#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e 344#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f 345#define VD1_IF0_GEN_REG3 0x1aa7 346 347#define VIU_OSD_BLENDO_H_START_END 0x1aa9 348#define VIU_OSD_BLENDO_V_START_END 0x1aaa 349#define VIU_OSD_BLEND_GEN_CTRL0 0x1aab 350#define VIU_OSD_BLEND_GEN_CTRL1 0x1aac 351#define VIU_OSD_BLEND_DUMMY_DATA 0x1aad 352#define VIU_OSD_BLEND_CURRENT_XY 0x1aae 353 354#define VIU_OSD2_MATRIX_CTRL 0x1ab0 355#define VIU_OSD2_MATRIX_COEF00_01 0x1ab1 356#define VIU_OSD2_MATRIX_COEF02_10 0x1ab2 357#define VIU_OSD2_MATRIX_COEF11_12 0x1ab3 358#define VIU_OSD2_MATRIX_COEF20_21 0x1ab4 359#define VIU_OSD2_MATRIX_COEF22 0x1ab5 360#define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6 361#define VIU_OSD2_MATRIX_OFFSET2 0x1ab7 362#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8 363#define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9 364#define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba 365#define VIU_OSD2_MATRIX_HL_COLOR 0x1abb 366#define VIU_OSD2_MATRIX_PROBE_POS 0x1abc 367#define VIU_OSD1_EOTF_CTL 0x1ad4 368#define VIU_OSD1_EOTF_COEF00_01 0x1ad5 369#define VIU_OSD1_EOTF_COEF02_10 0x1ad6 370#define VIU_OSD1_EOTF_COEF11_12 0x1ad7 371#define VIU_OSD1_EOTF_COEF20_21 0x1ad8 372#define VIU_OSD1_EOTF_COEF22_RS 0x1ad9 373#define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada 374#define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb 375#define VIU_OSD1_OETF_CTL 0x1adc 376#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add 377#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade 378#define AFBC_ENABLE 0x1ae0 379#define AFBC_MODE 0x1ae1 380#define AFBC_SIZE_IN 0x1ae2 381#define AFBC_DEC_DEF_COLOR 0x1ae3 382#define AFBC_CONV_CTRL 0x1ae4 383#define AFBC_LBUF_DEPTH 0x1ae5 384#define AFBC_HEAD_BADDR 0x1ae6 385#define AFBC_BODY_BADDR 0x1ae7 386#define AFBC_SIZE_OUT 0x1ae8 387#define AFBC_OUT_YSCOPE 0x1ae9 388#define AFBC_STAT 0x1aea 389#define AFBC_VD_CFMT_CTRL 0x1aeb 390#define AFBC_VD_CFMT_W 0x1aec 391#define AFBC_MIF_HOR_SCOPE 0x1aed 392#define AFBC_MIF_VER_SCOPE 0x1aee 393#define AFBC_PIXEL_HOR_SCOPE 0x1aef 394#define AFBC_PIXEL_VER_SCOPE 0x1af0 395#define AFBC_VD_CFMT_H 0x1af1 396 397/* vpp */ 398#define VPP_DUMMY_DATA 0x1d00 399#define VPP_LINE_IN_LENGTH 0x1d01 400#define VPP_PIC_IN_HEIGHT 0x1d02 401#define VPP_SCALE_COEF_IDX 0x1d03 402#define VPP_SCALE_HORIZONTAL_COEF BIT(8) 403#define VPP_SCALE_COEF 0x1d04 404#define VPP_VSC_REGION12_STARTP 0x1d05 405#define VPP_VSC_REGION34_STARTP 0x1d06 406#define VPP_VSC_REGION4_ENDP 0x1d07 407#define VPP_VSC_START_PHASE_STEP 0x1d08 408#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 409#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 410#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 411#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 412#define VPP_VSC_PHASE_CTRL 0x1d0d 413#define VPP_VSC_INI_PHASE 0x1d0e 414#define VPP_HSC_REGION12_STARTP 0x1d10 415#define VPP_HSC_REGION34_STARTP 0x1d11 416#define VPP_HSC_REGION4_ENDP 0x1d12 417#define VPP_HSC_START_PHASE_STEP 0x1d13 418#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 419#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 420#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 421#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 422#define VPP_HSC_PHASE_CTRL 0x1d18 423#define VPP_SC_MISC 0x1d19 424#define VPP_SC_VD_EN_ENABLE BIT(15) 425#define VPP_SC_TOP_EN_ENABLE BIT(16) 426#define VPP_SC_HSC_EN_ENABLE BIT(17) 427#define VPP_SC_VSC_EN_ENABLE BIT(18) 428#define VPP_VSC_BANK_LENGTH(length) (length & 0x7) 429#define VPP_HSC_BANK_LENGTH(length) ((length & 0x7) << 8) 430#define VPP_PREBLEND_VD1_H_START_END 0x1d1a 431#define VPP_PREBLEND_VD1_V_START_END 0x1d1b 432#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 433#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 434#define VPP_BLEND_VD2_H_START_END 0x1d1e 435#define VPP_BLEND_VD2_V_START_END 0x1d1f 436#define VPP_PREBLEND_H_SIZE 0x1d20 437#define VPP_POSTBLEND_H_SIZE 0x1d21 438#define VPP_HOLD_LINES 0x1d22 439#define VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf) 440#define VPP_PREBLEND_HOLD_LINES(lines) ((lines & 0xf) << 8) 441#define VPP_BLEND_ONECOLOR_CTRL 0x1d23 442#define VPP_PREBLEND_CURRENT_XY 0x1d24 443#define VPP_POSTBLEND_CURRENT_XY 0x1d25 444#define VPP_MISC 0x1d26 445#define VPP_PREBLEND_ENABLE BIT(6) 446#define VPP_POSTBLEND_ENABLE BIT(7) 447#define VPP_OSD2_ALPHA_PREMULT BIT(8) 448#define VPP_OSD1_ALPHA_PREMULT BIT(9) 449#define VPP_VD1_POSTBLEND BIT(10) 450#define VPP_VD2_POSTBLEND BIT(11) 451#define VPP_OSD1_POSTBLEND BIT(12) 452#define VPP_OSD2_POSTBLEND BIT(13) 453#define VPP_VD1_PREBLEND BIT(14) 454#define VPP_VD2_PREBLEND BIT(15) 455#define VPP_OSD1_PREBLEND BIT(16) 456#define VPP_OSD2_PREBLEND BIT(17) 457#define VPP_COLOR_MNG_ENABLE BIT(28) 458#define VPP_OFIFO_SIZE 0x1d27 459#define VPP_OFIFO_SIZE_MASK GENMASK(13, 0) 460#define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000) 461#define VPP_FIFO_STATUS 0x1d28 462#define VPP_SMOKE_CTRL 0x1d29 463#define VPP_SMOKE1_VAL 0x1d2a 464#define VPP_SMOKE2_VAL 0x1d2b 465#define VPP_SMOKE3_VAL 0x1d2c 466#define VPP_SMOKE1_H_START_END 0x1d2d 467#define VPP_SMOKE1_V_START_END 0x1d2e 468#define VPP_SMOKE2_H_START_END 0x1d2f 469#define VPP_SMOKE2_V_START_END 0x1d30 470#define VPP_SMOKE3_H_START_END 0x1d31 471#define VPP_SMOKE3_V_START_END 0x1d32 472#define VPP_SCO_FIFO_CTRL 0x1d33 473#define VPP_HSC_PHASE_CTRL1 0x1d34 474#define VPP_HSC_INI_PAT_CTRL 0x1d35 475#define VPP_VADJ_CTRL 0x1d40 476#define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1) 477 478#define VPP_VADJ1_Y 0x1d41 479#define VPP_VADJ1_MA_MB 0x1d42 480#define VPP_VADJ1_MC_MD 0x1d43 481#define VPP_VADJ2_Y 0x1d44 482#define VPP_VADJ2_MA_MB 0x1d45 483#define VPP_VADJ2_MC_MD 0x1d46 484#define VPP_HSHARP_CTRL 0x1d50 485#define VPP_HSHARP_LUMA_THRESH01 0x1d51 486#define VPP_HSHARP_LUMA_THRESH23 0x1d52 487#define VPP_HSHARP_CHROMA_THRESH01 0x1d53 488#define VPP_HSHARP_CHROMA_THRESH23 0x1d54 489#define VPP_HSHARP_LUMA_GAIN 0x1d55 490#define VPP_HSHARP_CHROMA_GAIN 0x1d56 491#define VPP_MATRIX_PROBE_COLOR 0x1d5c 492#define VPP_MATRIX_HL_COLOR 0x1d5d 493#define VPP_MATRIX_PROBE_POS 0x1d5e 494#define VPP_MATRIX_CTRL 0x1d5f 495#define VPP_MATRIX_COEF00_01 0x1d60 496#define VPP_MATRIX_COEF02_10 0x1d61 497#define VPP_MATRIX_COEF11_12 0x1d62 498#define VPP_MATRIX_COEF20_21 0x1d63 499#define VPP_MATRIX_COEF22 0x1d64 500#define VPP_MATRIX_OFFSET0_1 0x1d65 501#define VPP_MATRIX_OFFSET2 0x1d66 502#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 503#define VPP_MATRIX_PRE_OFFSET2 0x1d68 504#define VPP_DUMMY_DATA1 0x1d69 505#define VPP_GAINOFF_CTRL0 0x1d6a 506#define VPP_GAINOFF_CTRL1 0x1d6b 507#define VPP_GAINOFF_CTRL2 0x1d6c 508#define VPP_GAINOFF_CTRL3 0x1d6d 509#define VPP_GAINOFF_CTRL4 0x1d6e 510#define VPP_CHROMA_ADDR_PORT 0x1d70 511#define VPP_CHROMA_DATA_PORT 0x1d71 512#define VPP_GCLK_CTRL0 0x1d72 513#define VPP_GCLK_CTRL1 0x1d73 514#define VPP_SC_GCLK_CTRL 0x1d74 515#define VPP_MISC1 0x1d76 516#define VPP_BLACKEXT_CTRL 0x1d80 517#define VPP_DNLP_CTRL_00 0x1d81 518#define VPP_DNLP_CTRL_01 0x1d82 519#define VPP_DNLP_CTRL_02 0x1d83 520#define VPP_DNLP_CTRL_03 0x1d84 521#define VPP_DNLP_CTRL_04 0x1d85 522#define VPP_DNLP_CTRL_05 0x1d86 523#define VPP_DNLP_CTRL_06 0x1d87 524#define VPP_DNLP_CTRL_07 0x1d88 525#define VPP_DNLP_CTRL_08 0x1d89 526#define VPP_DNLP_CTRL_09 0x1d8a 527#define VPP_DNLP_CTRL_10 0x1d8b 528#define VPP_DNLP_CTRL_11 0x1d8c 529#define VPP_DNLP_CTRL_12 0x1d8d 530#define VPP_DNLP_CTRL_13 0x1d8e 531#define VPP_DNLP_CTRL_14 0x1d8f 532#define VPP_DNLP_CTRL_15 0x1d90 533#define VPP_PEAKING_HGAIN 0x1d91 534#define VPP_PEAKING_VGAIN 0x1d92 535#define VPP_PEAKING_NLP_1 0x1d93 536#define VPP_DOLBY_CTRL 0x1d93 537#define VPP_PPS_DUMMY_DATA_MODE (1 << 17) 538#define VPP_PEAKING_NLP_2 0x1d94 539#define VPP_PEAKING_NLP_3 0x1d95 540#define VPP_PEAKING_NLP_4 0x1d96 541#define VPP_PEAKING_NLP_5 0x1d97 542#define VPP_SHARP_LIMIT 0x1d98 543#define VPP_VLTI_CTRL 0x1d99 544#define VPP_HLTI_CTRL 0x1d9a 545#define VPP_CTI_CTRL 0x1d9b 546#define VPP_BLUE_STRETCH_1 0x1d9c 547#define VPP_BLUE_STRETCH_2 0x1d9d 548#define VPP_BLUE_STRETCH_3 0x1d9e 549#define VPP_CCORING_CTRL 0x1da0 550#define VPP_VE_ENABLE_CTRL 0x1da1 551#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 552#define VPP_VE_DEMO_CENTER_BAR 0x1da3 553#define VPP_VE_H_V_SIZE 0x1da4 554#define VPP_VDO_MEAS_CTRL 0x1da8 555#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 556#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 557#define VPP_INPUT_CTRL 0x1dab 558#define VPP_CTI_CTRL2 0x1dac 559#define VPP_PEAKING_SAT_THD1 0x1dad 560#define VPP_PEAKING_SAT_THD2 0x1dae 561#define VPP_PEAKING_SAT_THD3 0x1daf 562#define VPP_PEAKING_SAT_THD4 0x1db0 563#define VPP_PEAKING_SAT_THD5 0x1db1 564#define VPP_PEAKING_SAT_THD6 0x1db2 565#define VPP_PEAKING_SAT_THD7 0x1db3 566#define VPP_PEAKING_SAT_THD8 0x1db4 567#define VPP_PEAKING_SAT_THD9 0x1db5 568#define VPP_PEAKING_GAIN_ADD1 0x1db6 569#define VPP_PEAKING_GAIN_ADD2 0x1db7 570#define VPP_PEAKING_DNLP 0x1db8 571#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 572#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba 573#define VPP_FRONT_HLTI_CTRL 0x1dbb 574#define VPP_FRONT_CTI_CTRL 0x1dbc 575#define VPP_FRONT_CTI_CTRL2 0x1dbd 576#define VPP_OSD_VSC_PHASE_STEP 0x1dc0 577#define VPP_OSD_VSC_INI_PHASE 0x1dc1 578#define VPP_OSD_VSC_CTRL0 0x1dc2 579#define VPP_OSD_HSC_PHASE_STEP 0x1dc3 580#define VPP_OSD_HSC_INI_PHASE 0x1dc4 581#define VPP_OSD_HSC_CTRL0 0x1dc5 582#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 583#define VPP_OSD_SC_DUMMY_DATA 0x1dc7 584#define VPP_OSD_SC_CTRL0 0x1dc8 585#define VPP_OSD_SCI_WH_M1 0x1dc9 586#define VPP_OSD_SCO_H_START_END 0x1dca 587#define VPP_OSD_SCO_V_START_END 0x1dcb 588#define VPP_OSD_SCALE_COEF_IDX 0x1dcc 589#define VPP_OSD_SCALE_COEF 0x1dcd 590#define VPP_INT_LINE_NUM 0x1dce 591 592#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60 593#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61 594#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62 595#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63 596#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64 597#define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65 598#define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66 599#define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67 600#define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68 601#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69 602#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a 603#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b 604#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c 605#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d 606 607#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70 608#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71 609#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72 610#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73 611#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74 612#define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75 613#define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76 614#define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77 615#define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78 616#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79 617#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a 618#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b 619#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c 620#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d 621 622#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0 623#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1 624#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2 625#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3 626#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4 627#define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5 628#define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6 629#define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7 630#define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8 631#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9 632#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba 633#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb 634#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc 635#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd 636 637/* osd1 HDR */ 638#define OSD1_HDR2_CTRL 0x38a0 639#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN BIT(13) 640#define OSD1_HDR2_CTRL_REG_ONLY_MAT BIT(16) 641 642/* osd2 scaler */ 643#define OSD2_VSC_PHASE_STEP 0x3d00 644#define OSD2_VSC_INI_PHASE 0x3d01 645#define OSD2_VSC_CTRL0 0x3d02 646#define OSD2_HSC_PHASE_STEP 0x3d03 647#define OSD2_HSC_INI_PHASE 0x3d04 648#define OSD2_HSC_CTRL0 0x3d05 649#define OSD2_HSC_INI_PAT_CTRL 0x3d06 650#define OSD2_SC_DUMMY_DATA 0x3d07 651#define OSD2_SC_CTRL0 0x3d08 652#define OSD2_SCI_WH_M1 0x3d09 653#define OSD2_SCO_H_START_END 0x3d0a 654#define OSD2_SCO_V_START_END 0x3d0b 655#define OSD2_SCALE_COEF_IDX 0x3d18 656#define OSD2_SCALE_COEF 0x3d19 657 658/* osd34 scaler */ 659#define OSD34_SCALE_COEF_IDX 0x3d1e 660#define OSD34_SCALE_COEF 0x3d1f 661#define OSD34_VSC_PHASE_STEP 0x3d20 662#define OSD34_VSC_INI_PHASE 0x3d21 663#define OSD34_VSC_CTRL0 0x3d22 664#define OSD34_HSC_PHASE_STEP 0x3d23 665#define OSD34_HSC_INI_PHASE 0x3d24 666#define OSD34_HSC_CTRL0 0x3d25 667#define OSD34_HSC_INI_PAT_CTRL 0x3d26 668#define OSD34_SC_DUMMY_DATA 0x3d27 669#define OSD34_SC_CTRL0 0x3d28 670#define OSD34_SCI_WH_M1 0x3d29 671#define OSD34_SCO_H_START_END 0x3d2a 672#define OSD34_SCO_V_START_END 0x3d2b 673 674/* viu2 */ 675#define VIU2_ADDR_START 0x1e00 676#define VIU2_ADDR_END 0x1eff 677#define VIU2_SW_RESET 0x1e01 678#define VIU2_OSD1_CTRL_STAT 0x1e10 679#define VIU2_OSD1_CTRL_STAT2 0x1e2d 680#define VIU2_OSD1_COLOR_ADDR 0x1e11 681#define VIU2_OSD1_COLOR 0x1e12 682#define VIU2_OSD1_TCOLOR_AG0 0x1e17 683#define VIU2_OSD1_TCOLOR_AG1 0x1e18 684#define VIU2_OSD1_TCOLOR_AG2 0x1e19 685#define VIU2_OSD1_TCOLOR_AG3 0x1e1a 686#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 687#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 688#define VIU2_OSD1_BLK2_CFG_W0 0x1e23 689#define VIU2_OSD1_BLK3_CFG_W0 0x1e27 690#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 691#define VIU2_OSD1_BLK1_CFG_W1 0x1e20 692#define VIU2_OSD1_BLK2_CFG_W1 0x1e24 693#define VIU2_OSD1_BLK3_CFG_W1 0x1e28 694#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 695#define VIU2_OSD1_BLK1_CFG_W2 0x1e21 696#define VIU2_OSD1_BLK2_CFG_W2 0x1e25 697#define VIU2_OSD1_BLK3_CFG_W2 0x1e29 698#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 699#define VIU2_OSD1_BLK1_CFG_W3 0x1e22 700#define VIU2_OSD1_BLK2_CFG_W3 0x1e26 701#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 702#define VIU2_OSD1_BLK0_CFG_W4 0x1e13 703#define VIU2_OSD1_BLK1_CFG_W4 0x1e14 704#define VIU2_OSD1_BLK2_CFG_W4 0x1e15 705#define VIU2_OSD1_BLK3_CFG_W4 0x1e16 706#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 707#define VIU2_OSD1_TEST_RDDATA 0x1e2c 708#define VIU2_OSD1_PROT_CTRL 0x1e2e 709#define VIU2_OSD2_CTRL_STAT 0x1e30 710#define VIU2_OSD2_CTRL_STAT2 0x1e4d 711#define VIU2_OSD2_COLOR_ADDR 0x1e31 712#define VIU2_OSD2_COLOR 0x1e32 713#define VIU2_OSD2_HL1_H_START_END 0x1e33 714#define VIU2_OSD2_HL1_V_START_END 0x1e34 715#define VIU2_OSD2_HL2_H_START_END 0x1e35 716#define VIU2_OSD2_HL2_V_START_END 0x1e36 717#define VIU2_OSD2_TCOLOR_AG0 0x1e37 718#define VIU2_OSD2_TCOLOR_AG1 0x1e38 719#define VIU2_OSD2_TCOLOR_AG2 0x1e39 720#define VIU2_OSD2_TCOLOR_AG3 0x1e3a 721#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 722#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 723#define VIU2_OSD2_BLK2_CFG_W0 0x1e43 724#define VIU2_OSD2_BLK3_CFG_W0 0x1e47 725#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 726#define VIU2_OSD2_BLK1_CFG_W1 0x1e40 727#define VIU2_OSD2_BLK2_CFG_W1 0x1e44 728#define VIU2_OSD2_BLK3_CFG_W1 0x1e48 729#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 730#define VIU2_OSD2_BLK1_CFG_W2 0x1e41 731#define VIU2_OSD2_BLK2_CFG_W2 0x1e45 732#define VIU2_OSD2_BLK3_CFG_W2 0x1e49 733#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 734#define VIU2_OSD2_BLK1_CFG_W3 0x1e42 735#define VIU2_OSD2_BLK2_CFG_W3 0x1e46 736#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 737#define VIU2_OSD2_BLK0_CFG_W4 0x1e64 738#define VIU2_OSD2_BLK1_CFG_W4 0x1e65 739#define VIU2_OSD2_BLK2_CFG_W4 0x1e66 740#define VIU2_OSD2_BLK3_CFG_W4 0x1e67 741#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 742#define VIU2_OSD2_TEST_RDDATA 0x1e4c 743#define VIU2_OSD2_PROT_CTRL 0x1e4e 744#define VIU2_VD1_IF0_GEN_REG 0x1e50 745#define VIU2_VD1_IF0_CANVAS0 0x1e51 746#define VIU2_VD1_IF0_CANVAS1 0x1e52 747#define VIU2_VD1_IF0_LUMA_X0 0x1e53 748#define VIU2_VD1_IF0_LUMA_Y0 0x1e54 749#define VIU2_VD1_IF0_CHROMA_X0 0x1e55 750#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 751#define VIU2_VD1_IF0_LUMA_X1 0x1e57 752#define VIU2_VD1_IF0_LUMA_Y1 0x1e58 753#define VIU2_VD1_IF0_CHROMA_X1 0x1e59 754#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 755#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 756#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 757#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 758#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 759#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 760#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 761#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 762#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 763#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 764#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 765#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 766#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 767#define VIU2_VD1_IF0_GEN_REG2 0x1e6d 768#define VIU2_VD1_IF0_PROT_CNTL 0x1e6e 769#define VIU2_VD1_FMT_CTRL 0x1e68 770#define VIU2_VD1_FMT_W 0x1e69 771 772/* encode */ 773#define ENCP_VFIFO2VD_CTL 0x1b58 774#define ENCP_VFIFO2VD_PIXEL_START 0x1b59 775#define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 776#define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 777#define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 778#define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 779#define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 780#define VENC_SYNC_ROUTE 0x1b60 781#define VENC_VIDEO_EXSRC 0x1b61 782#define VENC_DVI_SETTING 0x1b62 783#define VENC_C656_CTRL 0x1b63 784#define VENC_UPSAMPLE_CTRL0 0x1b64 785#define VENC_UPSAMPLE_CTRL1 0x1b65 786#define VENC_UPSAMPLE_CTRL2 0x1b66 787#define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0) 788#define VENC_UPSAMPLE_CTRL_F1_EN BIT(5) 789#define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6) 790#define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12) 791#define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12) 792#define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12) 793#define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12) 794#define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12) 795#define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12) 796#define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12) 797#define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12) 798#define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12) 799#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12) 800#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12) 801#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12) 802#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12) 803#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12) 804#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12) 805#define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12) 806#define TCON_INVERT_CTL 0x1b67 807#define VENC_VIDEO_PROG_MODE 0x1b68 808#define VENC_ENCI_LINE 0x1b69 809#define VENC_ENCI_PIXEL 0x1b6a 810#define VENC_ENCP_LINE 0x1b6b 811#define VENC_ENCP_PIXEL 0x1b6c 812#define VENC_STATA 0x1b6d 813#define VENC_INTCTRL 0x1b6e 814#define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) 815#define VENC_INTCTRL_ENCP_LNRST_INT_EN BIT(9) 816#define VENC_INTFLAG 0x1b6f 817#define VENC_VIDEO_TST_EN 0x1b70 818#define VENC_VIDEO_TST_MDSEL 0x1b71 819#define VENC_VIDEO_TST_Y 0x1b72 820#define VENC_VIDEO_TST_CB 0x1b73 821#define VENC_VIDEO_TST_CR 0x1b74 822#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 823#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 824#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 825#define VENC_VDAC_DACSEL0 0x1b78 826#define VENC_VDAC_SEL_ATV_DMD BIT(5) 827#define VENC_VDAC_DACSEL1 0x1b79 828#define VENC_VDAC_DACSEL2 0x1b7a 829#define VENC_VDAC_DACSEL3 0x1b7b 830#define VENC_VDAC_DACSEL4 0x1b7c 831#define VENC_VDAC_DACSEL5 0x1b7d 832#define VENC_VDAC_SETTING 0x1b7e 833#define VENC_VDAC_TST_VAL 0x1b7f 834#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 835#define VENC_VDAC_DAC0_OFFSET 0x1bf1 836#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 837#define VENC_VDAC_DAC1_OFFSET 0x1bf3 838#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 839#define VENC_VDAC_DAC2_OFFSET 0x1bf5 840#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 841#define VENC_VDAC_DAC3_OFFSET 0x1bf7 842#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 843#define VENC_VDAC_DAC4_OFFSET 0x1bf9 844#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 845#define VENC_VDAC_DAC5_OFFSET 0x1bfb 846#define VENC_VDAC_FIFO_CTRL 0x1bfc 847#define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13) 848#define ENCL_TCON_INVERT_CTL 0x1bfd 849#define ENCP_VIDEO_EN 0x1b80 850#define ENCP_VIDEO_SYNC_MODE 0x1b81 851#define ENCP_MACV_EN 0x1b82 852#define ENCP_VIDEO_Y_SCL 0x1b83 853#define ENCP_VIDEO_PB_SCL 0x1b84 854#define ENCP_VIDEO_PR_SCL 0x1b85 855#define ENCP_VIDEO_SYNC_SCL 0x1b86 856#define ENCP_VIDEO_MACV_SCL 0x1b87 857#define ENCP_VIDEO_Y_OFFST 0x1b88 858#define ENCP_VIDEO_PB_OFFST 0x1b89 859#define ENCP_VIDEO_PR_OFFST 0x1b8a 860#define ENCP_VIDEO_SYNC_OFFST 0x1b8b 861#define ENCP_VIDEO_MACV_OFFST 0x1b8c 862#define ENCP_VIDEO_MODE 0x1b8d 863#define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14) 864#define ENCP_VIDEO_MODE_ADV 0x1b8e 865#define ENCP_DBG_PX_RST 0x1b90 866#define ENCP_DBG_LN_RST 0x1b91 867#define ENCP_DBG_PX_INT 0x1b92 868#define ENCP_DBG_LN_INT 0x1b93 869#define ENCP_VIDEO_YFP1_HTIME 0x1b94 870#define ENCP_VIDEO_YFP2_HTIME 0x1b95 871#define ENCP_VIDEO_YC_DLY 0x1b96 872#define ENCP_VIDEO_MAX_PXCNT 0x1b97 873#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 874#define ENCP_VIDEO_HSPULS_END 0x1b99 875#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 876#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 877#define ENCP_VIDEO_VSPULS_END 0x1b9c 878#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 879#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 880#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 881#define ENCP_VIDEO_EQPULS_END 0x1ba0 882#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 883#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 884#define ENCP_VIDEO_HAVON_END 0x1ba3 885#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 886#define ENCP_VIDEO_VAVON_ELINE 0x1baf 887#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 888#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 889#define ENCP_VIDEO_HSO_END 0x1ba8 890#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 891#define ENCP_VIDEO_VSO_END 0x1baa 892#define ENCP_VIDEO_VSO_BLINE 0x1bab 893#define ENCP_VIDEO_VSO_ELINE 0x1bac 894#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 895#define ENCP_VIDEO_MAX_LNCNT 0x1bae 896#define ENCP_VIDEO_SY_VAL 0x1bb0 897#define ENCP_VIDEO_SY2_VAL 0x1bb1 898#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 899#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 900#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 901#define ENCP_VIDEO_HOFFST 0x1bb5 902#define ENCP_VIDEO_VOFFST 0x1bb6 903#define ENCP_VIDEO_RGB_CTRL 0x1bb7 904#define ENCP_VIDEO_FILT_CTRL 0x1bb8 905#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 906#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 907#define ENCP_VIDEO_MATRIX_CB 0x1bbb 908#define ENCP_VIDEO_MATRIX_CR 0x1bbc 909#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 910#define ENCP_MACV_BLANKY_VAL 0x1bc0 911#define ENCP_MACV_MAXY_VAL 0x1bc1 912#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 913#define ENCP_MACV_PSSYNC_STRT 0x1bc3 914#define ENCP_MACV_AGC_STRT 0x1bc4 915#define ENCP_MACV_AGC_END 0x1bc5 916#define ENCP_MACV_WAVE_END 0x1bc6 917#define ENCP_MACV_STRTLINE 0x1bc7 918#define ENCP_MACV_ENDLINE 0x1bc8 919#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 920#define ENCP_MACV_TS_CNT_MAX_H 0x1bca 921#define ENCP_MACV_TIME_DOWN 0x1bcb 922#define ENCP_MACV_TIME_LO 0x1bcc 923#define ENCP_MACV_TIME_UP 0x1bcd 924#define ENCP_MACV_TIME_RST 0x1bce 925#define ENCP_VBI_CTRL 0x1bd0 926#define ENCP_VBI_SETTING 0x1bd1 927#define ENCP_VBI_BEGIN 0x1bd2 928#define ENCP_VBI_WIDTH 0x1bd3 929#define ENCP_VBI_HVAL 0x1bd4 930#define ENCP_VBI_DATA0 0x1bd5 931#define ENCP_VBI_DATA1 0x1bd6 932#define C656_HS_ST 0x1be0 933#define C656_HS_ED 0x1be1 934#define C656_VS_LNST_E 0x1be2 935#define C656_VS_LNST_O 0x1be3 936#define C656_VS_LNED_E 0x1be4 937#define C656_VS_LNED_O 0x1be5 938#define C656_FS_LNST 0x1be6 939#define C656_FS_LNED 0x1be7 940#define ENCI_VIDEO_MODE 0x1b00 941#define ENCI_VIDEO_MODE_ADV 0x1b01 942#define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3) 943#define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2) 944#define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4) 945#define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4) 946#define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4) 947#define ENCI_VIDEO_FSC_ADJ 0x1b02 948#define ENCI_VIDEO_BRIGHT 0x1b03 949#define ENCI_VIDEO_CONT 0x1b04 950#define ENCI_VIDEO_SAT 0x1b05 951#define ENCI_VIDEO_HUE 0x1b06 952#define ENCI_VIDEO_SCH 0x1b07 953#define ENCI_SYNC_MODE 0x1b08 954#define ENCI_SYNC_CTRL 0x1b09 955#define ENCI_SYNC_HSO_BEGIN 0x1b0a 956#define ENCI_SYNC_HSO_END 0x1b0b 957#define ENCI_SYNC_VSO_EVN 0x1b0c 958#define ENCI_SYNC_VSO_ODD 0x1b0d 959#define ENCI_SYNC_VSO_EVNLN 0x1b0e 960#define ENCI_SYNC_VSO_ODDLN 0x1b0f 961#define ENCI_SYNC_HOFFST 0x1b10 962#define ENCI_SYNC_VOFFST 0x1b11 963#define ENCI_SYNC_ADJ 0x1b12 964#define ENCI_RGB_SETTING 0x1b13 965#define ENCI_DE_H_BEGIN 0x1b16 966#define ENCI_DE_H_END 0x1b17 967#define ENCI_DE_V_BEGIN_EVEN 0x1b18 968#define ENCI_DE_V_END_EVEN 0x1b19 969#define ENCI_DE_V_BEGIN_ODD 0x1b1a 970#define ENCI_DE_V_END_ODD 0x1b1b 971#define ENCI_VBI_SETTING 0x1b20 972#define ENCI_VBI_CCDT_EVN 0x1b21 973#define ENCI_VBI_CCDT_ODD 0x1b22 974#define ENCI_VBI_CC525_LN 0x1b23 975#define ENCI_VBI_CC625_LN 0x1b24 976#define ENCI_VBI_WSSDT 0x1b25 977#define ENCI_VBI_WSS_LN 0x1b26 978#define ENCI_VBI_CGMSDT_L 0x1b27 979#define ENCI_VBI_CGMSDT_H 0x1b28 980#define ENCI_VBI_CGMS_LN 0x1b29 981#define ENCI_VBI_TTX_HTIME 0x1b2a 982#define ENCI_VBI_TTX_LN 0x1b2b 983#define ENCI_VBI_TTXDT0 0x1b2c 984#define ENCI_VBI_TTXDT1 0x1b2d 985#define ENCI_VBI_TTXDT2 0x1b2e 986#define ENCI_VBI_TTXDT3 0x1b2f 987#define ENCI_MACV_N0 0x1b30 988#define ENCI_MACV_N1 0x1b31 989#define ENCI_MACV_N2 0x1b32 990#define ENCI_MACV_N3 0x1b33 991#define ENCI_MACV_N4 0x1b34 992#define ENCI_MACV_N5 0x1b35 993#define ENCI_MACV_N6 0x1b36 994#define ENCI_MACV_N7 0x1b37 995#define ENCI_MACV_N8 0x1b38 996#define ENCI_MACV_N9 0x1b39 997#define ENCI_MACV_N10 0x1b3a 998#define ENCI_MACV_N11 0x1b3b 999#define ENCI_MACV_N12 0x1b3c 1000#define ENCI_MACV_N13 0x1b3d 1001#define ENCI_MACV_N14 0x1b3e 1002#define ENCI_MACV_N15 0x1b3f 1003#define ENCI_MACV_N16 0x1b40 1004#define ENCI_MACV_N17 0x1b41 1005#define ENCI_MACV_N18 0x1b42 1006#define ENCI_MACV_N19 0x1b43 1007#define ENCI_MACV_N20 0x1b44 1008#define ENCI_MACV_N21 0x1b45 1009#define ENCI_MACV_N22 0x1b46 1010#define ENCI_DBG_PX_RST 0x1b48 1011#define ENCI_DBG_FLDLN_RST 0x1b49 1012#define ENCI_DBG_PX_INT 0x1b4a 1013#define ENCI_DBG_FLDLN_INT 0x1b4b 1014#define ENCI_DBG_MAXPX 0x1b4c 1015#define ENCI_DBG_MAXLN 0x1b4d 1016#define ENCI_MACV_MAX_AMP 0x1b50 1017#define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15) 1018#define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff) 1019#define ENCI_MACV_PULSE_LO 0x1b51 1020#define ENCI_MACV_PULSE_HI 0x1b52 1021#define ENCI_MACV_BKP_MAX 0x1b53 1022#define ENCI_CFILT_CTRL 0x1b54 1023#define ENCI_CFILT_CMPT_SEL_HIGH BIT(1) 1024#define ENCI_CFILT7 0x1b55 1025#define ENCI_YC_DELAY 0x1b56 1026#define ENCI_VIDEO_EN 0x1b57 1027#define ENCI_VIDEO_EN_ENABLE BIT(0) 1028#define ENCI_DVI_HSO_BEGIN 0x1c00 1029#define ENCI_DVI_HSO_END 0x1c01 1030#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 1031#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 1032#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 1033#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 1034#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 1035#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 1036#define ENCI_DVI_VSO_END_EVN 0x1c08 1037#define ENCI_DVI_VSO_END_ODD 0x1c09 1038#define ENCI_CFILT_CTRL2 0x1c0a 1039#define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf) 1040#define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4) 1041#define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8) 1042#define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12) 1043#define ENCI_DACSEL_0 0x1c0b 1044#define ENCI_DACSEL_1 0x1c0c 1045#define ENCP_DACSEL_0 0x1c0d 1046#define ENCP_DACSEL_1 0x1c0e 1047#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 1048#define ENCI_TST_EN 0x1c10 1049#define ENCI_TST_MDSEL 0x1c11 1050#define ENCI_TST_Y 0x1c12 1051#define ENCI_TST_CB 0x1c13 1052#define ENCI_TST_CR 0x1c14 1053#define ENCI_TST_CLRBAR_STRT 0x1c15 1054#define ENCI_TST_CLRBAR_WIDTH 0x1c16 1055#define ENCI_TST_VDCNT_STSET 0x1c17 1056#define ENCI_VFIFO2VD_CTL 0x1c18 1057#define ENCI_VFIFO2VD_CTL_ENABLE BIT(0) 1058#define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8) 1059#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 1060#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 1061#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 1062#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 1063#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 1064#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 1065#define ENCI_VFIFO2VD_CTL2 0x1c1f 1066#define ENCT_VFIFO2VD_CTL 0x1c20 1067#define ENCT_VFIFO2VD_PIXEL_START 0x1c21 1068#define ENCT_VFIFO2VD_PIXEL_END 0x1c22 1069#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 1070#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 1071#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 1072#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 1073#define ENCT_VFIFO2VD_CTL2 0x1c27 1074#define ENCT_TST_EN 0x1c28 1075#define ENCT_TST_MDSEL 0x1c29 1076#define ENCT_TST_Y 0x1c2a 1077#define ENCT_TST_CB 0x1c2b 1078#define ENCT_TST_CR 0x1c2c 1079#define ENCT_TST_CLRBAR_STRT 0x1c2d 1080#define ENCT_TST_CLRBAR_WIDTH 0x1c2e 1081#define ENCT_TST_VDCNT_STSET 0x1c2f 1082#define ENCP_DVI_HSO_BEGIN 0x1c30 1083#define ENCP_DVI_HSO_END 0x1c31 1084#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 1085#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 1086#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 1087#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 1088#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 1089#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 1090#define ENCP_DVI_VSO_END_EVN 0x1c38 1091#define ENCP_DVI_VSO_END_ODD 0x1c39 1092#define ENCP_DE_H_BEGIN 0x1c3a 1093#define ENCP_DE_H_END 0x1c3b 1094#define ENCP_DE_V_BEGIN_EVEN 0x1c3c 1095#define ENCP_DE_V_END_EVEN 0x1c3d 1096#define ENCP_DE_V_BEGIN_ODD 0x1c3e 1097#define ENCP_DE_V_END_ODD 0x1c3f 1098#define ENCI_SYNC_LINE_LENGTH 0x1c40 1099#define ENCI_SYNC_PIXEL_EN 0x1c41 1100#define ENCI_SYNC_TO_LINE_EN 0x1c42 1101#define ENCI_SYNC_TO_PIXEL 0x1c43 1102#define ENCP_SYNC_LINE_LENGTH 0x1c44 1103#define ENCP_SYNC_PIXEL_EN 0x1c45 1104#define ENCP_SYNC_TO_LINE_EN 0x1c46 1105#define ENCP_SYNC_TO_PIXEL 0x1c47 1106#define ENCT_SYNC_LINE_LENGTH 0x1c48 1107#define ENCT_SYNC_PIXEL_EN 0x1c49 1108#define ENCT_SYNC_TO_LINE_EN 0x1c4a 1109#define ENCT_SYNC_TO_PIXEL 0x1c4b 1110#define ENCL_SYNC_LINE_LENGTH 0x1c4c 1111#define ENCL_SYNC_PIXEL_EN 0x1c4d 1112#define ENCL_SYNC_TO_LINE_EN 0x1c4e 1113#define ENCL_SYNC_TO_PIXEL 0x1c4f 1114#define ENCP_VFIFO2VD_CTL2 0x1c50 1115#define VENC_DVI_SETTING_MORE 0x1c51 1116#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 1117#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 1118#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 1119#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 1120#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 1121#define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0) 1122#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 1123#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 1124#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 1125#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 1126#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 1127#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 1128#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 1129#define ENCT_VIDEO_EN 0x1c60 1130#define ENCT_VIDEO_Y_SCL 0x1c61 1131#define ENCT_VIDEO_PB_SCL 0x1c62 1132#define ENCT_VIDEO_PR_SCL 0x1c63 1133#define ENCT_VIDEO_Y_OFFST 0x1c64 1134#define ENCT_VIDEO_PB_OFFST 0x1c65 1135#define ENCT_VIDEO_PR_OFFST 0x1c66 1136#define ENCT_VIDEO_MODE 0x1c67 1137#define ENCT_VIDEO_MODE_ADV 0x1c68 1138#define ENCT_DBG_PX_RST 0x1c69 1139#define ENCT_DBG_LN_RST 0x1c6a 1140#define ENCT_DBG_PX_INT 0x1c6b 1141#define ENCT_DBG_LN_INT 0x1c6c 1142#define ENCT_VIDEO_YFP1_HTIME 0x1c6d 1143#define ENCT_VIDEO_YFP2_HTIME 0x1c6e 1144#define ENCT_VIDEO_YC_DLY 0x1c6f 1145#define ENCT_VIDEO_MAX_PXCNT 0x1c70 1146#define ENCT_VIDEO_HAVON_END 0x1c71 1147#define ENCT_VIDEO_HAVON_BEGIN 0x1c72 1148#define ENCT_VIDEO_VAVON_ELINE 0x1c73 1149#define ENCT_VIDEO_VAVON_BLINE 0x1c74 1150#define ENCT_VIDEO_HSO_BEGIN 0x1c75 1151#define ENCT_VIDEO_HSO_END 0x1c76 1152#define ENCT_VIDEO_VSO_BEGIN 0x1c77 1153#define ENCT_VIDEO_VSO_END 0x1c78 1154#define ENCT_VIDEO_VSO_BLINE 0x1c79 1155#define ENCT_VIDEO_VSO_ELINE 0x1c7a 1156#define ENCT_VIDEO_MAX_LNCNT 0x1c7b 1157#define ENCT_VIDEO_BLANKY_VAL 0x1c7c 1158#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 1159#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 1160#define ENCT_VIDEO_HOFFST 0x1c7f 1161#define ENCT_VIDEO_VOFFST 0x1c80 1162#define ENCT_VIDEO_RGB_CTRL 0x1c81 1163#define ENCT_VIDEO_FILT_CTRL 0x1c82 1164#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 1165#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 1166#define ENCT_VIDEO_MATRIX_CB 0x1c85 1167#define ENCT_VIDEO_MATRIX_CR 0x1c86 1168#define ENCT_VIDEO_RGBIN_CTRL 0x1c87 1169#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 1170#define ENCT_DACSEL_0 0x1c89 1171#define ENCT_DACSEL_1 0x1c8a 1172#define ENCL_VFIFO2VD_CTL 0x1c90 1173#define ENCL_VFIFO2VD_PIXEL_START 0x1c91 1174#define ENCL_VFIFO2VD_PIXEL_END 0x1c92 1175#define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 1176#define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 1177#define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 1178#define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 1179#define ENCL_VFIFO2VD_CTL2 0x1c97 1180#define ENCL_TST_EN 0x1c98 1181#define ENCL_TST_MDSEL 0x1c99 1182#define ENCL_TST_Y 0x1c9a 1183#define ENCL_TST_CB 0x1c9b 1184#define ENCL_TST_CR 0x1c9c 1185#define ENCL_TST_CLRBAR_STRT 0x1c9d 1186#define ENCL_TST_CLRBAR_WIDTH 0x1c9e 1187#define ENCL_TST_VDCNT_STSET 0x1c9f 1188#define ENCL_VIDEO_EN 0x1ca0 1189#define ENCL_VIDEO_Y_SCL 0x1ca1 1190#define ENCL_VIDEO_PB_SCL 0x1ca2 1191#define ENCL_VIDEO_PR_SCL 0x1ca3 1192#define ENCL_VIDEO_Y_OFFST 0x1ca4 1193#define ENCL_VIDEO_PB_OFFST 0x1ca5 1194#define ENCL_VIDEO_PR_OFFST 0x1ca6 1195#define ENCL_VIDEO_MODE 0x1ca7 1196#define ENCL_PX_LN_CNT_SHADOW_EN BIT(15) 1197#define ENCL_VIDEO_MODE_ADV 0x1ca8 1198#define ENCL_VIDEO_MODE_ADV_VFIFO_EN BIT(3) 1199#define ENCL_VIDEO_MODE_ADV_GAIN_HDTV BIT(4) 1200#define ENCL_SEL_GAMMA_RGB_IN BIT(10) 1201#define ENCL_DBG_PX_RST 0x1ca9 1202#define ENCL_DBG_LN_RST 0x1caa 1203#define ENCL_DBG_PX_INT 0x1cab 1204#define ENCL_DBG_LN_INT 0x1cac 1205#define ENCL_VIDEO_YFP1_HTIME 0x1cad 1206#define ENCL_VIDEO_YFP2_HTIME 0x1cae 1207#define ENCL_VIDEO_YC_DLY 0x1caf 1208#define ENCL_VIDEO_MAX_PXCNT 0x1cb0 1209#define ENCL_VIDEO_HAVON_END 0x1cb1 1210#define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 1211#define ENCL_VIDEO_VAVON_ELINE 0x1cb3 1212#define ENCL_VIDEO_VAVON_BLINE 0x1cb4 1213#define ENCL_VIDEO_HSO_BEGIN 0x1cb5 1214#define ENCL_VIDEO_HSO_END 0x1cb6 1215#define ENCL_VIDEO_VSO_BEGIN 0x1cb7 1216#define ENCL_VIDEO_VSO_END 0x1cb8 1217#define ENCL_VIDEO_VSO_BLINE 0x1cb9 1218#define ENCL_VIDEO_VSO_ELINE 0x1cba 1219#define ENCL_VIDEO_MAX_LNCNT 0x1cbb 1220#define ENCL_VIDEO_BLANKY_VAL 0x1cbc 1221#define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 1222#define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 1223#define ENCL_VIDEO_HOFFST 0x1cbf 1224#define ENCL_VIDEO_VOFFST 0x1cc0 1225#define ENCL_VIDEO_RGB_CTRL 0x1cc1 1226#define ENCL_VIDEO_FILT_CTRL 0x1cc2 1227#define ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER BIT(12) 1228#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 1229#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 1230#define ENCL_VIDEO_MATRIX_CB 0x1cc5 1231#define ENCL_VIDEO_MATRIX_CR 0x1cc6 1232#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 1233#define ENCL_VIDEO_RGBIN_RGB BIT(0) 1234#define ENCL_VIDEO_RGBIN_ZBLK BIT(1) 1235#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 1236#define ENCL_DACSEL_0 0x1cc9 1237#define ENCL_DACSEL_1 0x1cca 1238#define RDMA_AHB_START_ADDR_MAN 0x1100 1239#define RDMA_AHB_END_ADDR_MAN 0x1101 1240#define RDMA_AHB_START_ADDR_1 0x1102 1241#define RDMA_AHB_END_ADDR_1 0x1103 1242#define RDMA_AHB_START_ADDR_2 0x1104 1243#define RDMA_AHB_END_ADDR_2 0x1105 1244#define RDMA_AHB_START_ADDR_3 0x1106 1245#define RDMA_AHB_END_ADDR_3 0x1107 1246#define RDMA_AHB_START_ADDR_4 0x1108 1247#define RDMA_AHB_END_ADDR_4 0x1109 1248#define RDMA_AHB_START_ADDR_5 0x110a 1249#define RDMA_AHB_END_ADDR_5 0x110b 1250#define RDMA_AHB_START_ADDR_6 0x110c 1251#define RDMA_AHB_END_ADDR_6 0x110d 1252#define RDMA_AHB_START_ADDR_7 0x110e 1253#define RDMA_AHB_END_ADDR_7 0x110f 1254#define RDMA_ACCESS_AUTO 0x1110 1255#define RDMA_ACCESS_TRIGGER_CHAN3 GENMASK(31, 24) 1256#define RDMA_ACCESS_TRIGGER_CHAN2 GENMASK(23, 16) 1257#define RDMA_ACCESS_TRIGGER_CHAN1 GENMASK(15, 8) 1258#define RDMA_ACCESS_TRIGGER_STOP 0 1259#define RDMA_ACCESS_TRIGGER_VSYNC 1 1260#define RDMA_ACCESS_TRIGGER_LINE 32 1261#define RDMA_ACCESS_RW_FLAG_CHAN3 BIT(7) 1262#define RDMA_ACCESS_RW_FLAG_CHAN2 BIT(6) 1263#define RDMA_ACCESS_RW_FLAG_CHAN1 BIT(5) 1264#define RDMA_ACCESS_ADDR_INC_CHAN3 BIT(3) 1265#define RDMA_ACCESS_ADDR_INC_CHAN2 BIT(2) 1266#define RDMA_ACCESS_ADDR_INC_CHAN1 BIT(1) 1267#define RDMA_ACCESS_AUTO2 0x1111 1268#define RDMA_ACCESS_RW_FLAG_CHAN7 BIT(7) 1269#define RDMA_ACCESS_RW_FLAG_CHAN6 BIT(6) 1270#define RDMA_ACCESS_RW_FLAG_CHAN5 BIT(5) 1271#define RDMA_ACCESS_RW_FLAG_CHAN4 BIT(4) 1272#define RDMA_ACCESS_ADDR_INC_CHAN7 BIT(3) 1273#define RDMA_ACCESS_ADDR_INC_CHAN6 BIT(2) 1274#define RDMA_ACCESS_ADDR_INC_CHAN5 BIT(1) 1275#define RDMA_ACCESS_ADDR_INC_CHAN4 BIT(0) 1276#define RDMA_ACCESS_AUTO3 0x1112 1277#define RDMA_ACCESS_TRIGGER_CHAN7 GENMASK(31, 24) 1278#define RDMA_ACCESS_TRIGGER_CHAN6 GENMASK(23, 16) 1279#define RDMA_ACCESS_TRIGGER_CHAN5 GENMASK(15, 8) 1280#define RDMA_ACCESS_TRIGGER_CHAN4 GENMASK(7, 0) 1281#define RDMA_ACCESS_MAN 0x1113 1282#define RDMA_ACCESS_MAN_RW_FLAG BIT(2) 1283#define RDMA_ACCESS_MAN_ADDR_INC BIT(1) 1284#define RDMA_ACCESS_MAN_START BIT(0) 1285#define RDMA_CTRL 0x1114 1286#define RDMA_IRQ_CLEAR_CHAN7 BIT(31) 1287#define RDMA_IRQ_CLEAR_CHAN6 BIT(30) 1288#define RDMA_IRQ_CLEAR_CHAN5 BIT(29) 1289#define RDMA_IRQ_CLEAR_CHAN4 BIT(28) 1290#define RDMA_IRQ_CLEAR_CHAN3 BIT(27) 1291#define RDMA_IRQ_CLEAR_CHAN2 BIT(26) 1292#define RDMA_IRQ_CLEAR_CHAN1 BIT(25) 1293#define RDMA_IRQ_CLEAR_CHAN_MAN BIT(24) 1294#define RDMA_DEFAULT_CONFIG (BIT(7) | BIT(6)) 1295#define RDMA_CTRL_AHB_WR_BURST GENMASK(5, 4) 1296#define RDMA_CTRL_AHB_RD_BURST GENMASK(3, 2) 1297#define RDMA_CTRL_SW_RESET BIT(1) 1298#define RDMA_CTRL_FREE_CLK_EN BIT(0) 1299#define RDMA_STATUS 0x1115 1300#define RDMA_IRQ_STAT_CHAN7 BIT(31) 1301#define RDMA_IRQ_STAT_CHAN6 BIT(30) 1302#define RDMA_IRQ_STAT_CHAN5 BIT(29) 1303#define RDMA_IRQ_STAT_CHAN4 BIT(28) 1304#define RDMA_IRQ_STAT_CHAN3 BIT(27) 1305#define RDMA_IRQ_STAT_CHAN2 BIT(26) 1306#define RDMA_IRQ_STAT_CHAN1 BIT(25) 1307#define RDMA_IRQ_STAT_CHAN_MAN BIT(24) 1308#define RDMA_STATUS2 0x1116 1309#define RDMA_STATUS3 0x1117 1310#define L_GAMMA_CNTL_PORT 0x1400 1311#define L_GAMMA_CNTL_PORT_VCOM_POL BIT(7) /* RW */ 1312#define L_GAMMA_CNTL_PORT_RVS_OUT BIT(6) /* RW */ 1313#define L_GAMMA_CNTL_PORT_ADR_RDY BIT(5) /* Read Only */ 1314#define L_GAMMA_CNTL_PORT_WR_RDY BIT(4) /* Read Only */ 1315#define L_GAMMA_CNTL_PORT_RD_RDY BIT(3) /* Read Only */ 1316#define L_GAMMA_CNTL_PORT_TR BIT(2) /* RW */ 1317#define L_GAMMA_CNTL_PORT_SET BIT(1) /* RW */ 1318#define L_GAMMA_CNTL_PORT_EN BIT(0) /* RW */ 1319#define L_GAMMA_DATA_PORT 0x1401 1320#define L_GAMMA_ADDR_PORT 0x1402 1321#define L_GAMMA_ADDR_PORT_RD BIT(12) 1322#define L_GAMMA_ADDR_PORT_AUTO_INC BIT(11) 1323#define L_GAMMA_ADDR_PORT_SEL_R BIT(10) 1324#define L_GAMMA_ADDR_PORT_SEL_G BIT(9) 1325#define L_GAMMA_ADDR_PORT_SEL_B BIT(8) 1326#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0) 1327#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 1328#define L_RGB_BASE_ADDR 0x1405 1329#define L_RGB_COEFF_ADDR 0x1406 1330#define L_POL_CNTL_ADDR 0x1407 1331#define L_DITH_CNTL_ADDR 0x1408 1332#define L_DITH_CNTL_DITH10_EN BIT(10) 1333#define L_GAMMA_PROBE_CTRL 0x1409 1334#define L_GAMMA_PROBE_COLOR_L 0x140a 1335#define L_GAMMA_PROBE_COLOR_H 0x140b 1336#define L_GAMMA_PROBE_HL_COLOR 0x140c 1337#define L_GAMMA_PROBE_POS_X 0x140d 1338#define L_GAMMA_PROBE_POS_Y 0x140e 1339#define L_STH1_HS_ADDR 0x1410 1340#define L_STH1_HE_ADDR 0x1411 1341#define L_STH1_VS_ADDR 0x1412 1342#define L_STH1_VE_ADDR 0x1413 1343#define L_STH2_HS_ADDR 0x1414 1344#define L_STH2_HE_ADDR 0x1415 1345#define L_STH2_VS_ADDR 0x1416 1346#define L_STH2_VE_ADDR 0x1417 1347#define L_OEH_HS_ADDR 0x1418 1348#define L_OEH_HE_ADDR 0x1419 1349#define L_OEH_VS_ADDR 0x141a 1350#define L_OEH_VE_ADDR 0x141b 1351#define L_VCOM_HSWITCH_ADDR 0x141c 1352#define L_VCOM_VS_ADDR 0x141d 1353#define L_VCOM_VE_ADDR 0x141e 1354#define L_CPV1_HS_ADDR 0x141f 1355#define L_CPV1_HE_ADDR 0x1420 1356#define L_CPV1_VS_ADDR 0x1421 1357#define L_CPV1_VE_ADDR 0x1422 1358#define L_CPV2_HS_ADDR 0x1423 1359#define L_CPV2_HE_ADDR 0x1424 1360#define L_CPV2_VS_ADDR 0x1425 1361#define L_CPV2_VE_ADDR 0x1426 1362#define L_STV1_HS_ADDR 0x1427 1363#define L_STV1_HE_ADDR 0x1428 1364#define L_STV1_VS_ADDR 0x1429 1365#define L_STV1_VE_ADDR 0x142a 1366#define L_STV2_HS_ADDR 0x142b 1367#define L_STV2_HE_ADDR 0x142c 1368#define L_STV2_VS_ADDR 0x142d 1369#define L_STV2_VE_ADDR 0x142e 1370#define L_OEV1_HS_ADDR 0x142f 1371#define L_OEV1_HE_ADDR 0x1430 1372#define L_OEV1_VS_ADDR 0x1431 1373#define L_OEV1_VE_ADDR 0x1432 1374#define L_OEV2_HS_ADDR 0x1433 1375#define L_OEV2_HE_ADDR 0x1434 1376#define L_OEV2_VS_ADDR 0x1435 1377#define L_OEV2_VE_ADDR 0x1436 1378#define L_OEV3_HS_ADDR 0x1437 1379#define L_OEV3_HE_ADDR 0x1438 1380#define L_OEV3_VS_ADDR 0x1439 1381#define L_OEV3_VE_ADDR 0x143a 1382#define L_LCD_PWR_ADDR 0x143b 1383#define L_LCD_PWM0_LO_ADDR 0x143c 1384#define L_LCD_PWM0_HI_ADDR 0x143d 1385#define L_LCD_PWM1_LO_ADDR 0x143e 1386#define L_LCD_PWM1_HI_ADDR 0x143f 1387#define L_INV_CNT_ADDR 0x1440 1388#define L_TCON_MISC_SEL_ADDR 0x1441 1389#define L_TCON_MISC_SEL_STV1 BIT(4) 1390#define L_TCON_MISC_SEL_STV2 BIT(5) 1391#define L_DUAL_PORT_CNTL_ADDR 0x1442 1392#define MLVDS_CLK_CTL1_HI 0x1443 1393#define MLVDS_CLK_CTL1_LO 0x1444 1394#define L_TCON_DOUBLE_CTL 0x1449 1395#define L_TCON_PATTERN_HI 0x144a 1396#define L_TCON_PATTERN_LO 0x144b 1397#define LDIM_BL_ADDR_PORT 0x144e 1398#define LDIM_BL_DATA_PORT 0x144f 1399#define L_DE_HS_ADDR 0x1451 1400#define L_DE_HE_ADDR 0x1452 1401#define L_DE_VS_ADDR 0x1453 1402#define L_DE_VE_ADDR 0x1454 1403#define L_HSYNC_HS_ADDR 0x1455 1404#define L_HSYNC_HE_ADDR 0x1456 1405#define L_HSYNC_VS_ADDR 0x1457 1406#define L_HSYNC_VE_ADDR 0x1458 1407#define L_VSYNC_HS_ADDR 0x1459 1408#define L_VSYNC_HE_ADDR 0x145a 1409#define L_VSYNC_VS_ADDR 0x145b 1410#define L_VSYNC_VE_ADDR 0x145c 1411#define L_LCD_MCU_CTL 0x145d 1412#define DUAL_MLVDS_CTL 0x1460 1413#define DUAL_MLVDS_LINE_START 0x1461 1414#define DUAL_MLVDS_LINE_END 0x1462 1415#define DUAL_MLVDS_PIXEL_W_START_L 0x1463 1416#define DUAL_MLVDS_PIXEL_W_END_L 0x1464 1417#define DUAL_MLVDS_PIXEL_W_START_R 0x1465 1418#define DUAL_MLVDS_PIXEL_W_END_R 0x1466 1419#define DUAL_MLVDS_PIXEL_R_START_L 0x1467 1420#define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468 1421#define DUAL_MLVDS_PIXEL_R_START_R 0x1469 1422#define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a 1423#define V_INVERSION_PIXEL 0x1470 1424#define V_INVERSION_LINE 0x1471 1425#define V_INVERSION_CONTROL 0x1472 1426#define MLVDS2_CONTROL 0x1474 1427#define MLVDS2_CONFIG_HI 0x1475 1428#define MLVDS2_CONFIG_LO 0x1476 1429#define MLVDS2_DUAL_GATE_WR_START 0x1477 1430#define MLVDS2_DUAL_GATE_WR_END 0x1478 1431#define MLVDS2_DUAL_GATE_RD_START 0x1479 1432#define MLVDS2_DUAL_GATE_RD_END 0x147a 1433#define MLVDS2_SECOND_RESET_CTL 0x147b 1434#define MLVDS2_DUAL_GATE_CTL_HI 0x147c 1435#define MLVDS2_DUAL_GATE_CTL_LO 0x147d 1436#define MLVDS2_RESET_CONFIG_HI 0x147e 1437#define MLVDS2_RESET_CONFIG_LO 0x147f 1438#define GAMMA_CNTL_PORT 0x1480 1439#define GAMMA_DATA_PORT 0x1481 1440#define GAMMA_ADDR_PORT 0x1482 1441#define GAMMA_VCOM_HSWITCH_ADDR 0x1483 1442#define RGB_BASE_ADDR 0x1485 1443#define RGB_COEFF_ADDR 0x1486 1444#define POL_CNTL_ADDR 0x1487 1445#define DITH_CNTL_ADDR 0x1488 1446#define GAMMA_PROBE_CTRL 0x1489 1447#define GAMMA_PROBE_COLOR_L 0x148a 1448#define GAMMA_PROBE_COLOR_H 0x148b 1449#define GAMMA_PROBE_HL_COLOR 0x148c 1450#define GAMMA_PROBE_POS_X 0x148d 1451#define GAMMA_PROBE_POS_Y 0x148e 1452#define STH1_HS_ADDR 0x1490 1453#define STH1_HE_ADDR 0x1491 1454#define STH1_VS_ADDR 0x1492 1455#define STH1_VE_ADDR 0x1493 1456#define STH2_HS_ADDR 0x1494 1457#define STH2_HE_ADDR 0x1495 1458#define STH2_VS_ADDR 0x1496 1459#define STH2_VE_ADDR 0x1497 1460#define OEH_HS_ADDR 0x1498 1461#define OEH_HE_ADDR 0x1499 1462#define OEH_VS_ADDR 0x149a 1463#define OEH_VE_ADDR 0x149b 1464#define VCOM_HSWITCH_ADDR 0x149c 1465#define VCOM_VS_ADDR 0x149d 1466#define VCOM_VE_ADDR 0x149e 1467#define CPV1_HS_ADDR 0x149f 1468#define CPV1_HE_ADDR 0x14a0 1469#define CPV1_VS_ADDR 0x14a1 1470#define CPV1_VE_ADDR 0x14a2 1471#define CPV2_HS_ADDR 0x14a3 1472#define CPV2_HE_ADDR 0x14a4 1473#define CPV2_VS_ADDR 0x14a5 1474#define CPV2_VE_ADDR 0x14a6 1475#define STV1_HS_ADDR 0x14a7 1476#define STV1_HE_ADDR 0x14a8 1477#define STV1_VS_ADDR 0x14a9 1478#define STV1_VE_ADDR 0x14aa 1479#define STV2_HS_ADDR 0x14ab 1480#define STV2_HE_ADDR 0x14ac 1481#define STV2_VS_ADDR 0x14ad 1482#define STV2_VE_ADDR 0x14ae 1483#define OEV1_HS_ADDR 0x14af 1484#define OEV1_HE_ADDR 0x14b0 1485#define OEV1_VS_ADDR 0x14b1 1486#define OEV1_VE_ADDR 0x14b2 1487#define OEV2_HS_ADDR 0x14b3 1488#define OEV2_HE_ADDR 0x14b4 1489#define OEV2_VS_ADDR 0x14b5 1490#define OEV2_VE_ADDR 0x14b6 1491#define OEV3_HS_ADDR 0x14b7 1492#define OEV3_HE_ADDR 0x14b8 1493#define OEV3_VS_ADDR 0x14b9 1494#define OEV3_VE_ADDR 0x14ba 1495#define LCD_PWR_ADDR 0x14bb 1496#define LCD_PWM0_LO_ADDR 0x14bc 1497#define LCD_PWM0_HI_ADDR 0x14bd 1498#define LCD_PWM1_LO_ADDR 0x14be 1499#define LCD_PWM1_HI_ADDR 0x14bf 1500#define INV_CNT_ADDR 0x14c0 1501#define TCON_MISC_SEL_ADDR 0x14c1 1502#define DUAL_PORT_CNTL_ADDR 0x14c2 1503#define MLVDS_CONTROL 0x14c3 1504#define MLVDS_RESET_PATTERN_HI 0x14c4 1505#define MLVDS_RESET_PATTERN_LO 0x14c5 1506#define MLVDS_RESET_PATTERN_EXT 0x14c6 1507#define MLVDS_CONFIG_HI 0x14c7 1508#define MLVDS_CONFIG_LO 0x14c8 1509#define TCON_DOUBLE_CTL 0x14c9 1510#define TCON_PATTERN_HI 0x14ca 1511#define TCON_PATTERN_LO 0x14cb 1512#define TCON_CONTROL_HI 0x14cc 1513#define TCON_CONTROL_LO 0x14cd 1514#define LVDS_BLANK_DATA_HI 0x14ce 1515#define LVDS_BLANK_DATA_LO 0x14cf 1516#define LVDS_PACK_CNTL_ADDR 0x14d0 1517#define DE_HS_ADDR 0x14d1 1518#define DE_HE_ADDR 0x14d2 1519#define DE_VS_ADDR 0x14d3 1520#define DE_VE_ADDR 0x14d4 1521#define HSYNC_HS_ADDR 0x14d5 1522#define HSYNC_HE_ADDR 0x14d6 1523#define HSYNC_VS_ADDR 0x14d7 1524#define HSYNC_VE_ADDR 0x14d8 1525#define VSYNC_HS_ADDR 0x14d9 1526#define VSYNC_HE_ADDR 0x14da 1527#define VSYNC_VS_ADDR 0x14db 1528#define VSYNC_VE_ADDR 0x14dc 1529#define LCD_MCU_CTL 0x14dd 1530#define LCD_MCU_DATA_0 0x14de 1531#define LCD_MCU_DATA_1 0x14df 1532#define LVDS_GEN_CNTL 0x14e0 1533#define LVDS_PHY_CNTL0 0x14e1 1534#define LVDS_PHY_CNTL1 0x14e2 1535#define LVDS_PHY_CNTL2 0x14e3 1536#define LVDS_PHY_CNTL3 0x14e4 1537#define LVDS_PHY_CNTL4 0x14e5 1538#define LVDS_PHY_CNTL5 0x14e6 1539#define LVDS_SRG_TEST 0x14e8 1540#define LVDS_BIST_MUX0 0x14e9 1541#define LVDS_BIST_MUX1 0x14ea 1542#define LVDS_BIST_FIXED0 0x14eb 1543#define LVDS_BIST_FIXED1 0x14ec 1544#define LVDS_BIST_CNTL0 0x14ed 1545#define LVDS_CLKB_CLKA 0x14ee 1546#define LVDS_PHY_CLK_CNTL 0x14ef 1547#define LVDS_SER_EN 0x14f0 1548#define LVDS_PHY_CNTL6 0x14f1 1549#define LVDS_PHY_CNTL7 0x14f2 1550#define LVDS_PHY_CNTL8 0x14f3 1551#define MLVDS_CLK_CTL0_HI 0x14f4 1552#define MLVDS_CLK_CTL0_LO 0x14f5 1553#define MLVDS_DUAL_GATE_WR_START 0x14f6 1554#define MLVDS_DUAL_GATE_WR_END 0x14f7 1555#define MLVDS_DUAL_GATE_RD_START 0x14f8 1556#define MLVDS_DUAL_GATE_RD_END 0x14f9 1557#define MLVDS_SECOND_RESET_CTL 0x14fa 1558#define MLVDS_DUAL_GATE_CTL_HI 0x14fb 1559#define MLVDS_DUAL_GATE_CTL_LO 0x14fc 1560#define MLVDS_RESET_CONFIG_HI 0x14fd 1561#define MLVDS_RESET_CONFIG_LO 0x14fe 1562#define VPU_OSD1_MMC_CTRL 0x2701 1563#define VPU_OSD2_MMC_CTRL 0x2702 1564#define VPU_VD1_MMC_CTRL 0x2703 1565#define VPU_VD2_MMC_CTRL 0x2704 1566#define VPU_DI_IF1_MMC_CTRL 0x2705 1567#define VPU_DI_MEM_MMC_CTRL 0x2706 1568#define VPU_DI_INP_MMC_CTRL 0x2707 1569#define VPU_DI_MTNRD_MMC_CTRL 0x2708 1570#define VPU_DI_CHAN2_MMC_CTRL 0x2709 1571#define VPU_DI_MTNWR_MMC_CTRL 0x270a 1572#define VPU_DI_NRWR_MMC_CTRL 0x270b 1573#define VPU_DI_DIWR_MMC_CTRL 0x270c 1574#define VPU_VDIN0_MMC_CTRL 0x270d 1575#define VPU_VDIN1_MMC_CTRL 0x270e 1576#define VPU_BT656_MMC_CTRL 0x270f 1577#define VPU_TVD3D_MMC_CTRL 0x2710 1578#define VPU_TVDVBI_MMC_CTRL 0x2711 1579#define VPU_TVDVBI_VSLATCH_ADDR 0x2712 1580#define VPU_TVDVBI_WRRSP_ADDR 0x2713 1581#define VPU_VDIN_PRE_ARB_CTRL 0x2714 1582#define VPU_VDISP_PRE_ARB_CTRL 0x2715 1583#define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 1584#define VPU_OSD3_MMC_CTRL 0x2717 1585#define VPU_OSD4_MMC_CTRL 0x2718 1586#define VPU_VD3_MMC_CTRL 0x2719 1587#define VPU_VIU_VENC_MUX_CTRL 0x271a 1588#define VIU1_SEL_VENC_MASK 0x3 1589#define VIU1_SEL_VENC_ENCL 0 1590#define VIU1_SEL_VENC_ENCI 1 1591#define VIU1_SEL_VENC_ENCP 2 1592#define VIU1_SEL_VENC_ENCT 3 1593#define VIU2_SEL_VENC_MASK 0xc 1594#define VIU2_SEL_VENC_ENCL 0 1595#define VIU2_SEL_VENC_ENCI (1 << 2) 1596#define VIU2_SEL_VENC_ENCP (2 << 2) 1597#define VIU2_SEL_VENC_ENCT (3 << 2) 1598#define VPU_HDMI_SETTING 0x271b 1599#define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0) 1600#define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1) 1601#define VPU_HDMI_INV_HSYNC BIT(2) 1602#define VPU_HDMI_INV_VSYNC BIT(3) 1603#define VPU_HDMI_OUTPUT_CRYCB (0 << 5) 1604#define VPU_HDMI_OUTPUT_YCBCR (1 << 5) 1605#define VPU_HDMI_OUTPUT_YCRCB (2 << 5) 1606#define VPU_HDMI_OUTPUT_CBCRY (3 << 5) 1607#define VPU_HDMI_OUTPUT_CBYCR (4 << 5) 1608#define VPU_HDMI_OUTPUT_CRCBY (5 << 5) 1609#define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8) 1610#define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12) 1611#define ENCI_INFO_READ 0x271c 1612#define ENCP_INFO_READ 0x271d 1613#define ENCT_INFO_READ 0x271e 1614#define ENCL_INFO_READ 0x271f 1615#define VPU_SW_RESET 0x2720 1616#define VPU_D2D3_MMC_CTRL 0x2721 1617#define VPU_CONT_MMC_CTRL 0x2722 1618#define VPU_CLK_GATE 0x2723 1619#define VPU_RDMA_MMC_CTRL 0x2724 1620#define VPU_MEM_PD_REG0 0x2725 1621#define VPU_MEM_PD_REG1 0x2726 1622#define VPU_HDMI_DATA_OVR 0x2727 1623#define VPU_PROT1_MMC_CTRL 0x2728 1624#define VPU_PROT2_MMC_CTRL 0x2729 1625#define VPU_PROT3_MMC_CTRL 0x272a 1626#define VPU_ARB4_V1_MMC_CTRL 0x272b 1627#define VPU_ARB4_V2_MMC_CTRL 0x272c 1628#define VPU_VPU_PWM_V0 0x2730 1629#define VPU_VPU_PWM_V1 0x2731 1630#define VPU_VPU_PWM_V2 0x2732 1631#define VPU_VPU_PWM_V3 0x2733 1632#define VPU_VPU_PWM_H0 0x2734 1633#define VPU_VPU_PWM_H1 0x2735 1634#define VPU_VPU_PWM_H2 0x2736 1635#define VPU_VPU_PWM_H3 0x2737 1636#define VPU_MISC_CTRL 0x2740 1637#define VPU_ISP_GCLK_CTRL0 0x2741 1638#define VPU_ISP_GCLK_CTRL1 0x2742 1639#define VPU_HDMI_FMT_CTRL 0x2743 1640#define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743 1641#define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744 1642#define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745 1643 1644#define VPU_PROT1_CLK_GATE 0x2750 1645#define VPU_PROT1_GEN_CNTL 0x2751 1646#define VPU_PROT1_X_START_END 0x2752 1647#define VPU_PROT1_Y_START_END 0x2753 1648#define VPU_PROT1_Y_LEN_STEP 0x2754 1649#define VPU_PROT1_RPT_LOOP 0x2755 1650#define VPU_PROT1_RPT_PAT 0x2756 1651#define VPU_PROT1_DDR 0x2757 1652#define VPU_PROT1_RBUF_ROOM 0x2758 1653#define VPU_PROT1_STAT_0 0x2759 1654#define VPU_PROT1_STAT_1 0x275a 1655#define VPU_PROT1_STAT_2 0x275b 1656#define VPU_PROT1_REQ_ONOFF 0x275c 1657#define VPU_PROT2_CLK_GATE 0x2760 1658#define VPU_PROT2_GEN_CNTL 0x2761 1659#define VPU_PROT2_X_START_END 0x2762 1660#define VPU_PROT2_Y_START_END 0x2763 1661#define VPU_PROT2_Y_LEN_STEP 0x2764 1662#define VPU_PROT2_RPT_LOOP 0x2765 1663#define VPU_PROT2_RPT_PAT 0x2766 1664#define VPU_PROT2_DDR 0x2767 1665#define VPU_PROT2_RBUF_ROOM 0x2768 1666#define VPU_PROT2_STAT_0 0x2769 1667#define VPU_PROT2_STAT_1 0x276a 1668#define VPU_PROT2_STAT_2 0x276b 1669#define VPU_PROT2_REQ_ONOFF 0x276c 1670#define VPU_PROT3_CLK_GATE 0x2770 1671#define VPU_PROT3_GEN_CNTL 0x2771 1672#define VPU_PROT3_X_START_END 0x2772 1673#define VPU_PROT3_Y_START_END 0x2773 1674#define VPU_PROT3_Y_LEN_STEP 0x2774 1675#define VPU_PROT3_RPT_LOOP 0x2775 1676#define VPU_PROT3_RPT_PAT 0x2776 1677#define VPU_PROT3_DDR 0x2777 1678#define VPU_PROT3_RBUF_ROOM 0x2778 1679#define VPU_PROT3_STAT_0 0x2779 1680#define VPU_PROT3_STAT_1 0x277a 1681#define VPU_PROT3_STAT_2 0x277b 1682#define VPU_PROT3_REQ_ONOFF 0x277c 1683#define VPU_RDARB_MODE_L1C1 0x2790 1684#define VPU_RDARB_MODE_L1C2 0x2799 1685#define VPU_RDARB_MODE_L2C1 0x279d 1686#define VPU_WRARB_MODE_L2C1 0x27a2 1687#define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc)) 1688 1689/* osd super scale */ 1690#define OSDSR_HV_SIZEIN 0x3130 1691#define OSDSR_CTRL_MODE 0x3131 1692#define OSDSR_ABIC_HCOEF 0x3132 1693#define OSDSR_YBIC_HCOEF 0x3133 1694#define OSDSR_CBIC_HCOEF 0x3134 1695#define OSDSR_ABIC_VCOEF 0x3135 1696#define OSDSR_YBIC_VCOEF 0x3136 1697#define OSDSR_CBIC_VCOEF 0x3137 1698#define OSDSR_VAR_PARA 0x3138 1699#define OSDSR_CONST_PARA 0x3139 1700#define OSDSR_RKE_EXTWIN 0x313a 1701#define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b 1702#define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c 1703#define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d 1704#define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e 1705#define OSDSR_UK_BST_GAIN 0x313f 1706#define OSDSR_HVBLEND_TH 0x3140 1707#define OSDSR_DEMO_WIND_TB 0x3141 1708#define OSDSR_DEMO_WIND_LR 0x3142 1709#define OSDSR_INT_BLANK_NUM 0x3143 1710#define OSDSR_FRM_END_STAT 0x3144 1711#define OSDSR_ABIC_HCOEF0 0x3145 1712#define OSDSR_YBIC_HCOEF0 0x3146 1713#define OSDSR_CBIC_HCOEF0 0x3147 1714#define OSDSR_ABIC_VCOEF0 0x3148 1715#define OSDSR_YBIC_VCOEF0 0x3149 1716#define OSDSR_CBIC_VCOEF0 0x314a 1717 1718/* osd afbcd on gxtvbb */ 1719#define OSD1_AFBCD_ENABLE 0x31a0 1720#define OSD1_AFBCD_ID_FIFO_THRD GENMASK(15, 9) 1721#define OSD1_AFBCD_DEC_ENABLE BIT(8) 1722#define OSD1_AFBCD_FRM_START BIT(0) 1723#define OSD1_AFBCD_MODE 0x31a1 1724#define OSD1_AFBCD_SOFT_RESET BIT(31) 1725#define OSD1_AFBCD_AXI_REORDER_MODE BIT(28) 1726#define OSD1_AFBCD_MIF_URGENT GENMASK(25, 24) 1727#define OSD1_AFBCD_HOLD_LINE_NUM GENMASK(22, 16) 1728#define OSD1_AFBCD_RGBA_EXCHAN_CTRL GENMASK(15, 8) 1729#define OSD1_AFBCD_HREG_BLOCK_SPLIT BIT(6) 1730#define OSD1_AFBCD_HREG_HALF_BLOCK BIT(5) 1731#define OSD1_AFBCD_HREG_PIXEL_PACKING_FMT GENMASK(4, 0) 1732#define OSD1_AFBCD_SIZE_IN 0x31a2 1733#define OSD1_AFBCD_HREG_VSIZE_IN GENMASK(31, 16) 1734#define OSD1_AFBCD_HREG_HSIZE_IN GENMASK(15, 0) 1735#define OSD1_AFBCD_HDR_PTR 0x31a3 1736#define OSD1_AFBCD_FRAME_PTR 0x31a4 1737#define OSD1_AFBCD_CHROMA_PTR 0x31a5 1738#define OSD1_AFBCD_CONV_CTRL 0x31a6 1739#define OSD1_AFBCD_CONV_LBUF_LEN GENMASK(15, 0) 1740#define OSD1_AFBCD_STATUS 0x31a8 1741#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9 1742#define OSD1_AFBCD_DEC_PIXEL_BGN_H GENMASK(31, 16) 1743#define OSD1_AFBCD_DEC_PIXEL_END_H GENMASK(15, 0) 1744#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa 1745#define OSD1_AFBCD_DEC_PIXEL_BGN_V GENMASK(31, 16) 1746#define OSD1_AFBCD_DEC_PIXEL_END_V GENMASK(15, 0) 1747 1748/* add for gxm and 962e dv core2 */ 1749#define DOLBY_CORE2A_SWAP_CTRL1 0x3434 1750#define DOLBY_CORE2A_SWAP_CTRL2 0x3435 1751 1752/* osd afbc on g12a */ 1753#define VPU_MAFBC_BLOCK_ID 0x3a00 1754#define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01 1755#define VPU_MAFBC_IRQ_CLEAR 0x3a02 1756#define VPU_MAFBC_IRQ_MASK 0x3a03 1757#define VPU_MAFBC_IRQ_STATUS 0x3a04 1758#define VPU_MAFBC_IRQ_SECURE_ID_ERROR BIT(5) 1759#define VPU_MAFBC_IRQ_AXI_ERROR BIT(4) 1760#define VPU_MAFBC_IRQ_DETILING_ERROR BIT(3) 1761#define VPU_MAFBC_IRQ_DECODE_ERROR BIT(2) 1762#define VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED BIT(1) 1763#define VPU_MAFBC_IRQ_SURFACES_COMPLETED BIT(0) 1764#define VPU_MAFBC_COMMAND 0x3a05 1765#define VPU_MAFBC_PENDING_SWAP BIT(1) 1766#define VPU_MAFBC_DIRECT_SWAP BIT(0) 1767#define VPU_MAFBC_STATUS 0x3a06 1768#define VPU_MAFBC_ERROR BIT(2) 1769#define VPU_MAFBC_SWAPPING BIT(1) 1770#define VPU_MAFBC_ACTIVE BIT(0) 1771#define VPU_MAFBC_SURFACE_CFG 0x3a07 1772#define VPU_MAFBC_CONTINUOUS_DECODING_ENABLE BIT(16) 1773#define VPU_MAFBC_S3_ENABLE BIT(3) 1774#define VPU_MAFBC_S2_ENABLE BIT(2) 1775#define VPU_MAFBC_S1_ENABLE BIT(1) 1776#define VPU_MAFBC_S0_ENABLE BIT(0) 1777#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10 1778#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11 1779#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12 1780#define VPU_MAFBC_PAYLOAD_LIMIT_EN BIT(19) 1781#define VPU_MAFBC_TILED_HEADER_EN BIT(18) 1782#define VPU_MAFBC_SUPER_BLOCK_ASPECT GENMASK(17, 16) 1783#define VPU_MAFBC_BLOCK_SPLIT BIT(9) 1784#define VPU_MAFBC_YUV_TRANSFORM BIT(8) 1785#define VPU_MAFBC_PIXEL_FORMAT GENMASK(3, 0) 1786#define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13 1787#define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14 1788#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15 1789#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16 1790#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17 1791#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18 1792#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19 1793#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a 1794#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b 1795#define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c 1796#define VPU_MAFBC_PREFETCH_READ_DIRECTION_Y BIT(1) 1797#define VPU_MAFBC_PREFETCH_READ_DIRECTION_X BIT(0) 1798 1799#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30 1800#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31 1801#define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32 1802#define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33 1803#define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34 1804#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35 1805#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36 1806#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37 1807#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38 1808#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39 1809#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a 1810#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b 1811#define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c 1812 1813#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50 1814#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51 1815#define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52 1816#define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53 1817#define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54 1818#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55 1819#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56 1820#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57 1821#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58 1822#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59 1823#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a 1824#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b 1825#define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c 1826 1827#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70 1828#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71 1829#define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72 1830#define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73 1831#define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74 1832#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75 1833#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76 1834#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77 1835#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78 1836#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79 1837#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a 1838#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b 1839#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c 1840 1841#define DOLBY_PATH_CTRL 0x1a0c 1842#define DOLBY_BYPASS_EN(val) (val & 0xf) 1843#define OSD_PATH_MISC_CTRL 0x1a0e 1844#define OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD BIT(4) 1845#define OSD_PATH_OSD_AXI_SEL_OSD2_AFBCD BIT(5) 1846#define OSD_PATH_OSD_AXI_SEL_OSD3_AFBCD BIT(6) 1847#define MALI_AFBCD_TOP_CTRL 0x1a0f 1848#define MALI_AFBCD_MANUAL_RESET BIT(23) 1849 1850#define VIU_OSD_BLEND_CTRL 0x39b0 1851#define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4)) 1852#define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20) 1853#define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24) 1854#define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25) 1855#define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26) 1856#define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27) 1857#define VIU_OSD_BLEND_HOLD_LINES(lines) ((lines & 0x7) << 29) 1858#define VIU_OSD_BLEND_CTRL1 0x39c0 1859#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1 1860#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2 1861#define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3 1862#define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4 1863#define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5 1864#define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6 1865#define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7 1866#define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8 1867#define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9 1868#define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba 1869#define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb 1870#define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc 1871#define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf 1872 1873#define VPP_OUT_H_V_SIZE 0x1da5 1874 1875#define VPP_VD2_HDR_IN_SIZE 0x1df0 1876#define VPP_OSD1_IN_SIZE 0x1df1 1877#define VPP_GCLK_CTRL2 0x1df2 1878#define VD2_PPS_DUMMY_DATA 0x1df4 1879#define VPP_OSD1_BLD_H_SCOPE 0x1df5 1880#define VPP_OSD1_BLD_V_SCOPE 0x1df6 1881#define VPP_OSD2_BLD_H_SCOPE 0x1df7 1882#define VPP_OSD2_BLD_V_SCOPE 0x1df8 1883#define VPP_WRBAK_CTRL 0x1df9 1884#define VPP_SLEEP_CTRL 0x1dfa 1885#define VD1_BLEND_SRC_CTRL 0x1dfb 1886#define VD2_BLEND_SRC_CTRL 0x1dfc 1887#define VD_BLEND_PREBLD_SRC_VD1 (1 << 0) 1888#define VD_BLEND_PREBLD_SRC_VD2 (2 << 0) 1889#define VD_BLEND_PREBLD_SRC_OSD1 (3 << 0) 1890#define VD_BLEND_PREBLD_SRC_OSD2 (4 << 0) 1891#define VD_BLEND_PREBLD_PREMULT_EN BIT(4) 1892#define VD_BLEND_POSTBLD_SRC_VD1 (1 << 8) 1893#define VD_BLEND_POSTBLD_SRC_VD2 (2 << 8) 1894#define VD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) 1895#define VD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) 1896#define VD_BLEND_POSTBLD_PREMULT_EN BIT(16) 1897#define OSD1_BLEND_SRC_CTRL 0x1dfd 1898#define OSD2_BLEND_SRC_CTRL 0x1dfe 1899#define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8) 1900#define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8) 1901#define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) 1902#define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) 1903#define OSD_BLEND_PATH_SEL_ENABLE BIT(20) 1904 1905#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968 1906#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969 1907#define VPP_RDARB_MODE 0x3978 1908#define VPP_RDARB_REQEN_SLV 0x3979 1909 1910#endif /* __MESON_REGISTERS_H */ 1911