1// SPDX-License-Identifier: MIT
2/*
3 * Copyright �� 2021 Intel Corporation
4 */
5
6#include <drm/drm_cache.h>
7#include <linux/string_helpers.h>
8
9#include "i915_drv.h"
10#include "i915_reg.h"
11#include "intel_guc_slpc.h"
12#include "intel_guc_print.h"
13#include "intel_mchbar_regs.h"
14#include "gt/intel_gt.h"
15#include "gt/intel_gt_regs.h"
16#include "gt/intel_rps.h"
17
18static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
19{
20	return container_of(slpc, struct intel_guc, slpc);
21}
22
23static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
24{
25	return guc_to_gt(slpc_to_guc(slpc));
26}
27
28static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc *slpc)
29{
30	return slpc_to_gt(slpc)->i915;
31}
32
33static bool __detect_slpc_supported(struct intel_guc *guc)
34{
35	/* GuC SLPC is unavailable for pre-Gen12 */
36	return guc->submission_supported &&
37		GRAPHICS_VER(guc_to_i915(guc)) >= 12;
38}
39
40static bool __guc_slpc_selected(struct intel_guc *guc)
41{
42	if (!intel_guc_slpc_is_supported(guc))
43		return false;
44
45	return guc->submission_selected;
46}
47
48void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
49{
50	struct intel_guc *guc = slpc_to_guc(slpc);
51
52	slpc->supported = __detect_slpc_supported(guc);
53	slpc->selected = __guc_slpc_selected(guc);
54}
55
56static void slpc_mem_set_param(struct slpc_shared_data *data,
57			       u32 id, u32 value)
58{
59	GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
60	/*
61	 * When the flag bit is set, corresponding value will be read
62	 * and applied by SLPC.
63	 */
64	data->override_params.bits[id >> 5] |= (1 << (id % 32));
65	data->override_params.values[id] = value;
66}
67
68static void slpc_mem_set_enabled(struct slpc_shared_data *data,
69				 u8 enable_id, u8 disable_id)
70{
71	/*
72	 * Enabling a param involves setting the enable_id
73	 * to 1 and disable_id to 0.
74	 */
75	slpc_mem_set_param(data, enable_id, 1);
76	slpc_mem_set_param(data, disable_id, 0);
77}
78
79static void slpc_mem_set_disabled(struct slpc_shared_data *data,
80				  u8 enable_id, u8 disable_id)
81{
82	/*
83	 * Disabling a param involves setting the enable_id
84	 * to 0 and disable_id to 1.
85	 */
86	slpc_mem_set_param(data, disable_id, 1);
87	slpc_mem_set_param(data, enable_id, 0);
88}
89
90static u32 slpc_get_state(struct intel_guc_slpc *slpc)
91{
92	struct slpc_shared_data *data;
93
94	GEM_BUG_ON(!slpc->vma);
95
96	drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
97	data = slpc->vaddr;
98
99	return data->header.global_state;
100}
101
102static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value)
103{
104	u32 request[] = {
105		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
106		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
107		id,
108		value,
109	};
110	int ret;
111
112	ret = intel_guc_send_nb(guc, request, ARRAY_SIZE(request), 0);
113
114	return ret > 0 ? -EPROTO : ret;
115}
116
117static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)
118{
119	struct intel_guc *guc = slpc_to_guc(slpc);
120
121	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
122
123	return guc_action_slpc_set_param_nb(guc, id, value);
124}
125
126static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
127{
128	u32 request[] = {
129		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
130		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
131		id,
132		value,
133	};
134	int ret;
135
136	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
137
138	return ret > 0 ? -EPROTO : ret;
139}
140
141static bool slpc_is_running(struct intel_guc_slpc *slpc)
142{
143	return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
144}
145
146static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
147{
148	u32 request[] = {
149		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
150		SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
151		offset,
152		0,
153	};
154	int ret;
155
156	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
157
158	return ret > 0 ? -EPROTO : ret;
159}
160
161static int slpc_query_task_state(struct intel_guc_slpc *slpc)
162{
163	struct intel_guc *guc = slpc_to_guc(slpc);
164	u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
165	int ret;
166
167	ret = guc_action_slpc_query(guc, offset);
168	if (unlikely(ret))
169		guc_probe_error(guc, "Failed to query task state: %pe\n", ERR_PTR(ret));
170
171	drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
172
173	return ret;
174}
175
176static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
177{
178	struct intel_guc *guc = slpc_to_guc(slpc);
179	int ret;
180
181	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
182
183	ret = guc_action_slpc_set_param(guc, id, value);
184	if (ret)
185		guc_probe_error(guc, "Failed to set param %d to %u: %pe\n",
186				id, value, ERR_PTR(ret));
187
188	return ret;
189}
190
191static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
192{
193	struct intel_guc *guc = slpc_to_guc(slpc);
194	struct drm_i915_private *i915 = slpc_to_i915(slpc);
195	intel_wakeref_t wakeref;
196	int ret = 0;
197
198	lockdep_assert_held(&slpc->lock);
199
200	if (!intel_guc_is_ready(guc))
201		return -ENODEV;
202
203	/*
204	 * This function is a little different as compared to
205	 * intel_guc_slpc_set_min_freq(). Softlimit will not be updated
206	 * here since this is used to temporarily change min freq,
207	 * for example, during a waitboost. Caller is responsible for
208	 * checking bounds.
209	 */
210
211	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
212		/* Non-blocking request will avoid stalls */
213		ret = slpc_set_param_nb(slpc,
214					SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
215					freq);
216		if (ret)
217			guc_notice(guc, "Failed to send set_param for min freq(%d): %pe\n",
218				   freq, ERR_PTR(ret));
219	}
220
221	return ret;
222}
223
224static void slpc_boost_work(struct work_struct *work)
225{
226	struct intel_guc_slpc *slpc = container_of(work, typeof(*slpc), boost_work);
227	int err;
228
229	/*
230	 * Raise min freq to boost. It's possible that
231	 * this is greater than current max. But it will
232	 * certainly be limited by RP0. An error setting
233	 * the min param is not fatal.
234	 */
235	mutex_lock(&slpc->lock);
236	if (atomic_read(&slpc->num_waiters)) {
237		err = slpc_force_min_freq(slpc, slpc->boost_freq);
238		if (!err)
239			slpc->num_boosts++;
240	}
241	mutex_unlock(&slpc->lock);
242}
243
244int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
245{
246	struct intel_guc *guc = slpc_to_guc(slpc);
247	u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
248	int err;
249
250	GEM_BUG_ON(slpc->vma);
251
252	err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
253	if (unlikely(err)) {
254		guc_probe_error(guc, "Failed to allocate SLPC struct: %pe\n", ERR_PTR(err));
255		return err;
256	}
257
258	slpc->max_freq_softlimit = 0;
259	slpc->min_freq_softlimit = 0;
260	slpc->ignore_eff_freq = false;
261	slpc->min_is_rpmax = false;
262
263	slpc->boost_freq = 0;
264	atomic_set(&slpc->num_waiters, 0);
265	slpc->num_boosts = 0;
266	slpc->media_ratio_mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
267
268	mutex_init(&slpc->lock);
269	INIT_WORK(&slpc->boost_work, slpc_boost_work);
270
271	return err;
272}
273
274static const char *slpc_global_state_to_string(enum slpc_global_state state)
275{
276	switch (state) {
277	case SLPC_GLOBAL_STATE_NOT_RUNNING:
278		return "not running";
279	case SLPC_GLOBAL_STATE_INITIALIZING:
280		return "initializing";
281	case SLPC_GLOBAL_STATE_RESETTING:
282		return "resetting";
283	case SLPC_GLOBAL_STATE_RUNNING:
284		return "running";
285	case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
286		return "shutting down";
287	case SLPC_GLOBAL_STATE_ERROR:
288		return "error";
289	default:
290		return "unknown";
291	}
292}
293
294static const char *slpc_get_state_string(struct intel_guc_slpc *slpc)
295{
296	return slpc_global_state_to_string(slpc_get_state(slpc));
297}
298
299static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
300{
301	u32 request[] = {
302		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
303		SLPC_EVENT(SLPC_EVENT_RESET, 2),
304		offset,
305		0,
306	};
307	int ret;
308
309	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
310
311	return ret > 0 ? -EPROTO : ret;
312}
313
314static int slpc_reset(struct intel_guc_slpc *slpc)
315{
316	struct intel_guc *guc = slpc_to_guc(slpc);
317	u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
318	int ret;
319
320	ret = guc_action_slpc_reset(guc, offset);
321
322	if (unlikely(ret < 0)) {
323		guc_probe_error(guc, "SLPC reset action failed: %pe\n", ERR_PTR(ret));
324		return ret;
325	}
326
327	if (!ret) {
328		if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
329			guc_probe_error(guc, "SLPC not enabled! State = %s\n",
330					slpc_get_state_string(slpc));
331			return -EIO;
332		}
333	}
334
335	return 0;
336}
337
338static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
339{
340	struct slpc_shared_data *data = slpc->vaddr;
341
342	GEM_BUG_ON(!slpc->vma);
343
344	return	DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
345				  data->task_state_data.freq) *
346				  GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
347}
348
349static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
350{
351	struct slpc_shared_data *data = slpc->vaddr;
352
353	GEM_BUG_ON(!slpc->vma);
354
355	return	DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
356				  data->task_state_data.freq) *
357				  GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
358}
359
360static void slpc_shared_data_reset(struct slpc_shared_data *data)
361{
362	memset(data, 0, sizeof(struct slpc_shared_data));
363
364	data->header.size = sizeof(struct slpc_shared_data);
365
366	/* Enable only GTPERF task, disable others */
367	slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
368			     SLPC_PARAM_TASK_DISABLE_GTPERF);
369
370	slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
371			      SLPC_PARAM_TASK_DISABLE_BALANCER);
372
373	slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
374			      SLPC_PARAM_TASK_DISABLE_DCC);
375}
376
377/**
378 * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
379 * @slpc: pointer to intel_guc_slpc.
380 * @val: frequency (MHz)
381 *
382 * This function will invoke GuC SLPC action to update the max frequency
383 * limit for unslice.
384 *
385 * Return: 0 on success, non-zero error code on failure.
386 */
387int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
388{
389	struct drm_i915_private *i915 = slpc_to_i915(slpc);
390	intel_wakeref_t wakeref;
391	int ret;
392
393	if (val < slpc->min_freq ||
394	    val > slpc->rp0_freq ||
395	    val < slpc->min_freq_softlimit)
396		return -EINVAL;
397
398	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
399		ret = slpc_set_param(slpc,
400				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
401				     val);
402
403		/* Return standardized err code for sysfs calls */
404		if (ret)
405			ret = -EIO;
406	}
407
408	if (!ret)
409		slpc->max_freq_softlimit = val;
410
411	return ret;
412}
413
414/**
415 * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
416 * @slpc: pointer to intel_guc_slpc.
417 * @val: pointer to val which will hold max frequency (MHz)
418 *
419 * This function will invoke GuC SLPC action to read the max frequency
420 * limit for unslice.
421 *
422 * Return: 0 on success, non-zero error code on failure.
423 */
424int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
425{
426	struct drm_i915_private *i915 = slpc_to_i915(slpc);
427	intel_wakeref_t wakeref;
428	int ret = 0;
429
430	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
431		/* Force GuC to update task data */
432		ret = slpc_query_task_state(slpc);
433
434		if (!ret)
435			*val = slpc_decode_max_freq(slpc);
436	}
437
438	return ret;
439}
440
441int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
442{
443	struct drm_i915_private *i915 = slpc_to_i915(slpc);
444	intel_wakeref_t wakeref;
445	int ret;
446
447	mutex_lock(&slpc->lock);
448	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
449
450	ret = slpc_set_param(slpc,
451			     SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
452			     val);
453	if (ret) {
454		guc_probe_error(slpc_to_guc(slpc), "Failed to set efficient freq(%d): %pe\n",
455				val, ERR_PTR(ret));
456	} else {
457		slpc->ignore_eff_freq = val;
458
459		/* Set min to RPn when we disable efficient freq */
460		if (val)
461			ret = slpc_set_param(slpc,
462					     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
463					     slpc->min_freq);
464	}
465
466	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
467	mutex_unlock(&slpc->lock);
468	return ret;
469}
470
471/**
472 * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
473 * @slpc: pointer to intel_guc_slpc.
474 * @val: frequency (MHz)
475 *
476 * This function will invoke GuC SLPC action to update the min unslice
477 * frequency.
478 *
479 * Return: 0 on success, non-zero error code on failure.
480 */
481int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
482{
483	struct drm_i915_private *i915 = slpc_to_i915(slpc);
484	intel_wakeref_t wakeref;
485	int ret;
486
487	if (val < slpc->min_freq ||
488	    val > slpc->rp0_freq ||
489	    val > slpc->max_freq_softlimit)
490		return -EINVAL;
491
492	/* Need a lock now since waitboost can be modifying min as well */
493	mutex_lock(&slpc->lock);
494	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
495
496	ret = slpc_set_param(slpc,
497			     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
498			     val);
499
500	if (!ret)
501		slpc->min_freq_softlimit = val;
502
503	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
504	mutex_unlock(&slpc->lock);
505
506	/* Return standardized err code for sysfs calls */
507	if (ret)
508		ret = -EIO;
509
510	return ret;
511}
512
513/**
514 * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
515 * @slpc: pointer to intel_guc_slpc.
516 * @val: pointer to val which will hold min frequency (MHz)
517 *
518 * This function will invoke GuC SLPC action to read the min frequency
519 * limit for unslice.
520 *
521 * Return: 0 on success, non-zero error code on failure.
522 */
523int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
524{
525	struct drm_i915_private *i915 = slpc_to_i915(slpc);
526	intel_wakeref_t wakeref;
527	int ret = 0;
528
529	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
530		/* Force GuC to update task data */
531		ret = slpc_query_task_state(slpc);
532
533		if (!ret)
534			*val = slpc_decode_min_freq(slpc);
535	}
536
537	return ret;
538}
539
540int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)
541{
542	struct drm_i915_private *i915 = slpc_to_i915(slpc);
543	intel_wakeref_t wakeref;
544	int ret = 0;
545
546	if (!HAS_MEDIA_RATIO_MODE(i915))
547		return -ENODEV;
548
549	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
550		ret = slpc_set_param(slpc,
551				     SLPC_PARAM_MEDIA_FF_RATIO_MODE,
552				     val);
553	return ret;
554}
555
556void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
557{
558	u32 pm_intrmsk_mbz = 0;
559
560	/*
561	 * Allow GuC to receive ARAT timer expiry event.
562	 * This interrupt register is setup by RPS code
563	 * when host based Turbo is enabled.
564	 */
565	pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
566
567	intel_uncore_rmw(gt->uncore,
568			 GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
569}
570
571static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
572{
573	int ret = 0;
574
575	/*
576	 * Softlimits are initially equivalent to platform limits
577	 * unless they have deviated from defaults, in which case,
578	 * we retain the values and set min/max accordingly.
579	 */
580	if (!slpc->max_freq_softlimit) {
581		slpc->max_freq_softlimit = slpc->rp0_freq;
582		slpc_to_gt(slpc)->defaults.max_freq = slpc->max_freq_softlimit;
583	} else if (slpc->max_freq_softlimit != slpc->rp0_freq) {
584		ret = intel_guc_slpc_set_max_freq(slpc,
585						  slpc->max_freq_softlimit);
586	}
587
588	if (unlikely(ret))
589		return ret;
590
591	if (!slpc->min_freq_softlimit) {
592		/* Min softlimit is initialized to RPn */
593		slpc->min_freq_softlimit = slpc->min_freq;
594		slpc_to_gt(slpc)->defaults.min_freq = slpc->min_freq_softlimit;
595	} else {
596		return intel_guc_slpc_set_min_freq(slpc,
597						   slpc->min_freq_softlimit);
598	}
599
600	return 0;
601}
602
603static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
604{
605	int slpc_min_freq;
606	int ret;
607
608	ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
609	if (ret) {
610		guc_err(slpc_to_guc(slpc), "Failed to get min freq: %pe\n", ERR_PTR(ret));
611		return false;
612	}
613
614	if (slpc_min_freq == SLPC_MAX_FREQ_MHZ)
615		return true;
616	else
617		return false;
618}
619
620static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
621{
622	/* For server parts, SLPC min will be at RPMax.
623	 * Use min softlimit to clamp it to RP0 instead.
624	 */
625	if (!slpc->min_freq_softlimit &&
626	    is_slpc_min_freq_rpmax(slpc)) {
627		slpc->min_is_rpmax = true;
628		slpc->min_freq_softlimit = slpc->rp0_freq;
629		(slpc_to_gt(slpc))->defaults.min_freq = slpc->min_freq_softlimit;
630	}
631}
632
633static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
634{
635	/* Force SLPC to used platform rp0 */
636	return slpc_set_param(slpc,
637			      SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
638			      slpc->rp0_freq);
639}
640
641static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
642{
643	struct intel_rps *rps = &slpc_to_gt(slpc)->rps;
644	struct intel_rps_freq_caps caps;
645
646	gen6_rps_get_freq_caps(rps, &caps);
647	slpc->rp0_freq = intel_gpu_freq(rps, caps.rp0_freq);
648	slpc->rp1_freq = intel_gpu_freq(rps, caps.rp1_freq);
649	slpc->min_freq = intel_gpu_freq(rps, caps.min_freq);
650
651	if (!slpc->boost_freq)
652		slpc->boost_freq = slpc->rp0_freq;
653}
654
655/*
656 * intel_guc_slpc_enable() - Start SLPC
657 * @slpc: pointer to intel_guc_slpc.
658 *
659 * SLPC is enabled by setting up the shared data structure and
660 * sending reset event to GuC SLPC. Initial data is setup in
661 * intel_guc_slpc_init. Here we send the reset event. We do
662 * not currently need a slpc_disable since this is taken care
663 * of automatically when a reset/suspend occurs and the GuC
664 * CTB is destroyed.
665 *
666 * Return: 0 on success, non-zero error code on failure.
667 */
668int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
669{
670	struct intel_guc *guc = slpc_to_guc(slpc);
671	int ret;
672
673	GEM_BUG_ON(!slpc->vma);
674
675	slpc_shared_data_reset(slpc->vaddr);
676
677	ret = slpc_reset(slpc);
678	if (unlikely(ret < 0)) {
679		guc_probe_error(guc, "SLPC Reset event returned: %pe\n", ERR_PTR(ret));
680		return ret;
681	}
682
683	ret = slpc_query_task_state(slpc);
684	if (unlikely(ret < 0))
685		return ret;
686
687	intel_guc_pm_intrmsk_enable(slpc_to_gt(slpc));
688
689	slpc_get_rp_values(slpc);
690
691	/* Handle the case where min=max=RPmax */
692	update_server_min_softlimit(slpc);
693
694	/* Set SLPC max limit to RP0 */
695	ret = slpc_use_fused_rp0(slpc);
696	if (unlikely(ret)) {
697		guc_probe_error(guc, "Failed to set SLPC max to RP0: %pe\n", ERR_PTR(ret));
698		return ret;
699	}
700
701	/* Set cached value of ignore efficient freq */
702	intel_guc_slpc_set_ignore_eff_freq(slpc, slpc->ignore_eff_freq);
703
704	/* Revert SLPC min/max to softlimits if necessary */
705	ret = slpc_set_softlimits(slpc);
706	if (unlikely(ret)) {
707		guc_probe_error(guc, "Failed to set SLPC softlimits: %pe\n", ERR_PTR(ret));
708		return ret;
709	}
710
711	/* Set cached media freq ratio mode */
712	intel_guc_slpc_set_media_ratio_mode(slpc, slpc->media_ratio_mode);
713
714	return 0;
715}
716
717int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val)
718{
719	int ret = 0;
720
721	if (val < slpc->min_freq || val > slpc->rp0_freq)
722		return -EINVAL;
723
724	mutex_lock(&slpc->lock);
725
726	if (slpc->boost_freq != val) {
727		/* Apply only if there are active waiters */
728		if (atomic_read(&slpc->num_waiters)) {
729			ret = slpc_force_min_freq(slpc, val);
730			if (ret) {
731				ret = -EIO;
732				goto done;
733			}
734		}
735
736		slpc->boost_freq = val;
737	}
738
739done:
740	mutex_unlock(&slpc->lock);
741	return ret;
742}
743
744void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
745{
746	/*
747	 * Return min back to the softlimit.
748	 * This is called during request retire,
749	 * so we don't need to fail that if the
750	 * set_param fails.
751	 */
752	mutex_lock(&slpc->lock);
753	if (atomic_dec_and_test(&slpc->num_waiters))
754		slpc_force_min_freq(slpc, slpc->min_freq_softlimit);
755	mutex_unlock(&slpc->lock);
756}
757
758int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
759{
760	struct drm_i915_private *i915 = slpc_to_i915(slpc);
761	struct slpc_shared_data *data = slpc->vaddr;
762	struct slpc_task_state_data *slpc_tasks;
763	intel_wakeref_t wakeref;
764	int ret = 0;
765
766	GEM_BUG_ON(!slpc->vma);
767
768	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
769		ret = slpc_query_task_state(slpc);
770
771		if (!ret) {
772			slpc_tasks = &data->task_state_data;
773
774			drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
775			drm_printf(p, "\tGTPERF task active: %s\n",
776				   str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
777			drm_printf(p, "\tMax freq: %u MHz\n",
778				   slpc_decode_max_freq(slpc));
779			drm_printf(p, "\tMin freq: %u MHz\n",
780				   slpc_decode_min_freq(slpc));
781			drm_printf(p, "\twaitboosts: %u\n",
782				   slpc->num_boosts);
783			drm_printf(p, "\tBoosts outstanding: %u\n",
784				   atomic_read(&slpc->num_waiters));
785		}
786	}
787
788	return ret;
789}
790
791void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
792{
793	if (!slpc->vma)
794		return;
795
796	i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
797}
798