1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2014-2019 Intel Corporation 4 * 5 * Authors: 6 * Vinit Azad <vinit.azad@intel.com> 7 * Ben Widawsky <ben@bwidawsk.net> 8 * Dave Gordon <david.s.gordon@intel.com> 9 * Alex Dai <yu.dai@intel.com> 10 */ 11 12#include "gt/intel_gt.h" 13#include "gt/intel_gt_mcr.h" 14#include "gt/intel_gt_regs.h" 15#include "gt/intel_rps.h" 16#include "intel_guc_fw.h" 17#include "intel_guc_print.h" 18#include "i915_drv.h" 19 20static void guc_prepare_xfer(struct intel_gt *gt) 21{ 22 struct intel_uncore *uncore = gt->uncore; 23 24 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 25 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 26 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 27 GUC_ENABLE_MIA_CLOCK_GATING; 28 29 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50)) 30 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 31 GUC_ENABLE_MIA_CACHING; 32 33 /* Must program this register before loading the ucode with DMA */ 34 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); 35 36 if (IS_GEN9_LP(uncore->i915)) 37 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); 38 else 39 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); 40 41 if (GRAPHICS_VER(uncore->i915) == 9) { 42 /* DOP Clock Gating Enable for GuC clocks */ 43 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0, 44 GEN8_DOP_CLOCK_GATE_GUC_ENABLE); 45 46 /* allows for 5us (in 10ns units) before GT can go to RC6 */ 47 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); 48 } 49} 50 51static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw, 52 struct intel_uncore *uncore) 53{ 54 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 55 size_t copied; 56 int i; 57 58 copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa)); 59 if (copied < sizeof(rsa)) 60 return -ENOMEM; 61 62 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 63 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]); 64 65 return 0; 66} 67 68static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw, 69 struct intel_uncore *uncore) 70{ 71 struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw); 72 73 intel_uncore_write(uncore, UOS_RSA_SCRATCH(0), 74 intel_guc_ggtt_offset(guc, guc_fw->rsa_data)); 75 76 return 0; 77} 78 79/* Copy RSA signature from the fw image to HW for verification */ 80static int guc_xfer_rsa(struct intel_uc_fw *guc_fw, 81 struct intel_uncore *uncore) 82{ 83 if (guc_fw->rsa_data) 84 return guc_xfer_rsa_vma(guc_fw, uncore); 85 else 86 return guc_xfer_rsa_mmio(guc_fw, uncore); 87} 88 89/* 90 * Read the GuC status register (GUC_STATUS) and store it in the 91 * specified location; then return a boolean indicating whether 92 * the value matches either completion or a known failure code. 93 * 94 * This is used for polling the GuC status in a wait_for() 95 * loop below. 96 */ 97static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool *success) 98{ 99 u32 val = intel_uncore_read(uncore, GUC_STATUS); 100 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val); 101 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val); 102 103 *status = val; 104 switch (uk_val) { 105 case INTEL_GUC_LOAD_STATUS_READY: 106 *success = true; 107 return true; 108 109 case INTEL_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 110 case INTEL_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 111 case INTEL_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 112 case INTEL_GUC_LOAD_STATUS_HWCONFIG_ERROR: 113 case INTEL_GUC_LOAD_STATUS_DPC_ERROR: 114 case INTEL_GUC_LOAD_STATUS_EXCEPTION: 115 case INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID: 116 case INTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID: 117 case INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 118 *success = false; 119 return true; 120 } 121 122 switch (br_val) { 123 case INTEL_BOOTROM_STATUS_NO_KEY_FOUND: 124 case INTEL_BOOTROM_STATUS_RSA_FAILED: 125 case INTEL_BOOTROM_STATUS_PAVPC_FAILED: 126 case INTEL_BOOTROM_STATUS_WOPCM_FAILED: 127 case INTEL_BOOTROM_STATUS_LOADLOC_FAILED: 128 case INTEL_BOOTROM_STATUS_JUMP_FAILED: 129 case INTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 130 case INTEL_BOOTROM_STATUS_MPUMAP_INCORRECT: 131 case INTEL_BOOTROM_STATUS_EXCEPTION: 132 case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 133 *success = false; 134 return true; 135 } 136 137 return false; 138} 139 140/* 141 * Use a longer timeout for debug builds so that problems can be detected 142 * and analysed. But a shorter timeout for releases so that user's don't 143 * wait forever to find out there is a problem. Note that the only reason 144 * an end user should hit the timeout is in case of extreme thermal throttling. 145 * And a system that is that hot during boot is probably dead anyway! 146 */ 147#if defined(CONFIG_DRM_I915_DEBUG_GEM) 148#define GUC_LOAD_RETRY_LIMIT 20 149#else 150#define GUC_LOAD_RETRY_LIMIT 3 151#endif 152 153static int guc_wait_ucode(struct intel_guc *guc) 154{ 155 struct intel_gt *gt = guc_to_gt(guc); 156 struct intel_uncore *uncore = gt->uncore; 157 ktime_t before, after, delta; 158 bool success; 159 u32 status; 160 int ret, count; 161 u64 delta_ms; 162 u32 before_freq; 163 164 /* 165 * Wait for the GuC to start up. 166 * 167 * Measurements indicate this should take no more than 20ms 168 * (assuming the GT clock is at maximum frequency). So, a 169 * timeout here indicates that the GuC has failed and is unusable. 170 * (Higher levels of the driver may decide to reset the GuC and 171 * attempt the ucode load again if this happens.) 172 * 173 * FIXME: There is a known (but exceedingly unlikely) race condition 174 * where the asynchronous frequency management code could reduce 175 * the GT clock while a GuC reload is in progress (during a full 176 * GT reset). A fix is in progress but there are complex locking 177 * issues to be resolved. In the meantime bump the timeout to 178 * 200ms. Even at slowest clock, this should be sufficient. And 179 * in the working case, a larger timeout makes no difference. 180 * 181 * IFWI updates have also been seen to cause sporadic failures due to 182 * the requested frequency not being granted and thus the firmware 183 * load is attempted at minimum frequency. That can lead to load times 184 * in the seconds range. However, there is a limit on how long an 185 * individual wait_for() can wait. So wrap it in a loop. 186 */ 187 before_freq = intel_rps_read_actual_frequency(>->rps); 188 before = ktime_get(); 189 for (count = 0; count < GUC_LOAD_RETRY_LIMIT; count++) { 190 ret = wait_for(guc_load_done(uncore, &status, &success), 1000); 191 if (!ret || !success) 192 break; 193 194 guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz, status = 0x%08X [0x%02X/%02X]\n", 195 count, intel_rps_read_actual_frequency(>->rps), status, 196 REG_FIELD_GET(GS_BOOTROM_MASK, status), 197 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 198 } 199 after = ktime_get(); 200 delta = ktime_sub(after, before); 201 delta_ms = ktime_to_ms(delta); 202 if (ret || !success) { 203 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 204 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 205 206 guc_info(guc, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz, ret = %d\n", 207 status, delta_ms, intel_rps_read_actual_frequency(>->rps), ret); 208 guc_info(guc, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 209 REG_FIELD_GET(GS_MIA_IN_RESET, status), 210 bootrom, ukernel, 211 REG_FIELD_GET(GS_MIA_MASK, status), 212 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 213 214 switch (bootrom) { 215 case INTEL_BOOTROM_STATUS_NO_KEY_FOUND: 216 guc_info(guc, "invalid key requested, header = 0x%08X\n", 217 intel_uncore_read(uncore, GUC_HEADER_INFO)); 218 ret = -ENOEXEC; 219 break; 220 221 case INTEL_BOOTROM_STATUS_RSA_FAILED: 222 guc_info(guc, "firmware signature verification failed\n"); 223 ret = -ENOEXEC; 224 break; 225 226 case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 227 guc_info(guc, "firmware production part check failure\n"); 228 ret = -ENOEXEC; 229 break; 230 } 231 232 switch (ukernel) { 233 case INTEL_GUC_LOAD_STATUS_EXCEPTION: 234 guc_info(guc, "firmware exception. EIP: %#x\n", 235 intel_uncore_read(uncore, SOFT_SCRATCH(13))); 236 ret = -ENXIO; 237 break; 238 239 case INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 240 guc_info(guc, "illegal register in save/restore workaround list\n"); 241 ret = -EPERM; 242 break; 243 244 case INTEL_GUC_LOAD_STATUS_HWCONFIG_START: 245 guc_info(guc, "still extracting hwconfig table.\n"); 246 ret = -ETIMEDOUT; 247 break; 248 } 249 250 /* Uncommon/unexpected error, see earlier status code print for details */ 251 if (ret == 0) 252 ret = -ENXIO; 253 } else if (delta_ms > 200) { 254 guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n", 255 delta_ms, status, count, ret); 256 guc_warn(guc, "excessive init time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n", 257 intel_rps_read_actual_frequency(>->rps), before_freq, 258 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt))); 259 } else { 260 guc_dbg(guc, "init took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n", 261 delta_ms, intel_rps_read_actual_frequency(>->rps), 262 before_freq, status, count, ret); 263 } 264 265 return ret; 266} 267 268/** 269 * intel_guc_fw_upload() - load GuC uCode to device 270 * @guc: intel_guc structure 271 * 272 * Called from intel_uc_init_hw() during driver load, resume from sleep and 273 * after a GPU reset. 274 * 275 * The firmware image should have already been fetched into memory, so only 276 * check that fetch succeeded, and then transfer the image to the h/w. 277 * 278 * Return: non-zero code on error 279 */ 280int intel_guc_fw_upload(struct intel_guc *guc) 281{ 282 struct intel_gt *gt = guc_to_gt(guc); 283 struct intel_uncore *uncore = gt->uncore; 284 int ret; 285 286 guc_prepare_xfer(gt); 287 288 /* 289 * Note that GuC needs the CSS header plus uKernel code to be copied 290 * by the DMA engine in one operation, whereas the RSA signature is 291 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 292 * register (if key size <= 256) or through a ggtt-pinned vma (if key 293 * size > 256). The RSA size and therefore the way we provide it to the 294 * HW is fixed for each platform and hard-coded in the bootrom. 295 */ 296 ret = guc_xfer_rsa(&guc->fw, uncore); 297 if (ret) 298 goto out; 299 300 /* 301 * Current uCode expects the code to be loaded at 8k; locations below 302 * this are used for the stack. 303 */ 304 ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 305 if (ret) 306 goto out; 307 308 ret = guc_wait_ucode(guc); 309 if (ret) 310 goto out; 311 312 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING); 313 return 0; 314 315out: 316 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL); 317 return ret; 318} 319