1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright �� 2022 Intel Corporation
4 */
5
6#ifndef __INTEL_DVO_REGS_H__
7#define __INTEL_DVO_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11#define _DVOA			0x61120
12#define _DVOB			0x61140
13#define _DVOC			0x61160
14#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
15#define   DVO_ENABLE				REG_BIT(31)
16#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
17#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
18#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
19#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
20#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
21#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
22#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
23#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
24#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
25#define   DVO_USE_VGA_SYNC			REG_BIT(15)
26#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
27#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
28#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
29#define   DVO_VSYNC_DISABLE			REG_BIT(11)
30#define   DVO_HSYNC_DISABLE			REG_BIT(10)
31#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
32#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
33#define   DVO_BORDER_ENABLE			REG_BIT(7)
34#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
35#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
36#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
37#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
38#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
39#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
40#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
41#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
42#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
43#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
44
45#define _DVOA_SRCDIM		0x61124
46#define _DVOB_SRCDIM		0x61144
47#define _DVOC_SRCDIM		0x61164
48#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
49#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
50#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
51#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
52#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
53
54#endif /* __INTEL_DVO_REGS_H__ */
55