1/* 2 * Copyright �� 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28#include "intel_display_types.h" 29#include "intel_dvo_dev.h" 30 31#define CH7017_TV_DISPLAY_MODE 0x00 32#define CH7017_FLICKER_FILTER 0x01 33#define CH7017_VIDEO_BANDWIDTH 0x02 34#define CH7017_TEXT_ENHANCEMENT 0x03 35#define CH7017_START_ACTIVE_VIDEO 0x04 36#define CH7017_HORIZONTAL_POSITION 0x05 37#define CH7017_VERTICAL_POSITION 0x06 38#define CH7017_BLACK_LEVEL 0x07 39#define CH7017_CONTRAST_ENHANCEMENT 0x08 40#define CH7017_TV_PLL 0x09 41#define CH7017_TV_PLL_M 0x0a 42#define CH7017_TV_PLL_N 0x0b 43#define CH7017_SUB_CARRIER_0 0x0c 44#define CH7017_CIV_CONTROL 0x10 45#define CH7017_CIV_0 0x11 46#define CH7017_CHROMA_BOOST 0x14 47#define CH7017_CLOCK_MODE 0x1c 48#define CH7017_INPUT_CLOCK 0x1d 49#define CH7017_GPIO_CONTROL 0x1e 50#define CH7017_INPUT_DATA_FORMAT 0x1f 51#define CH7017_CONNECTION_DETECT 0x20 52#define CH7017_DAC_CONTROL 0x21 53#define CH7017_BUFFERED_CLOCK_OUTPUT 0x22 54#define CH7017_DEFEAT_VSYNC 0x47 55#define CH7017_TEST_PATTERN 0x48 56 57#define CH7017_POWER_MANAGEMENT 0x49 58/** Enables the TV output path. */ 59#define CH7017_TV_EN (1 << 0) 60#define CH7017_DAC0_POWER_DOWN (1 << 1) 61#define CH7017_DAC1_POWER_DOWN (1 << 2) 62#define CH7017_DAC2_POWER_DOWN (1 << 3) 63#define CH7017_DAC3_POWER_DOWN (1 << 4) 64/** Powers down the TV out block, and DAC0-3 */ 65#define CH7017_TV_POWER_DOWN_EN (1 << 5) 66 67#define CH7017_VERSION_ID 0x4a 68 69#define CH7017_DEVICE_ID 0x4b 70#define CH7017_DEVICE_ID_VALUE 0x1b 71#define CH7018_DEVICE_ID_VALUE 0x1a 72#define CH7019_DEVICE_ID_VALUE 0x19 73 74#define CH7017_XCLK_D2_ADJUST 0x53 75#define CH7017_UP_SCALER_COEFF_0 0x55 76#define CH7017_UP_SCALER_COEFF_1 0x56 77#define CH7017_UP_SCALER_COEFF_2 0x57 78#define CH7017_UP_SCALER_COEFF_3 0x58 79#define CH7017_UP_SCALER_COEFF_4 0x59 80#define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a 81#define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b 82#define CH7017_GPIO_INVERT 0x5c 83#define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d 84#define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e 85 86#define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f 87/**< Low bits of horizontal active pixel input */ 88 89#define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60 90/** High bits of horizontal active pixel input */ 91#define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0) 92/** High bits of vertical active line output */ 93#define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3) 94 95#define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61 96/**< Low bits of vertical active line output */ 97 98#define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62 99/**< Low bits of horizontal active pixel output */ 100 101#define CH7017_LVDS_POWER_DOWN 0x63 102/** High bits of horizontal active pixel output */ 103#define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0) 104/** Enables the LVDS power down state transition */ 105#define CH7017_LVDS_POWER_DOWN_EN (1 << 6) 106/** Enables the LVDS upscaler */ 107#define CH7017_LVDS_UPSCALER_EN (1 << 7) 108#define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08 109 110#define CH7017_LVDS_ENCODING 0x64 111#define CH7017_LVDS_DITHER_2D (1 << 2) 112#define CH7017_LVDS_DITHER_DIS (1 << 3) 113#define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4) 114#define CH7017_LVDS_24_BIT (1 << 5) 115 116#define CH7017_LVDS_ENCODING_2 0x65 117 118#define CH7017_LVDS_PLL_CONTROL 0x66 119/** Enables the LVDS panel output path */ 120#define CH7017_LVDS_PANEN (1 << 0) 121/** Enables the LVDS panel backlight */ 122#define CH7017_LVDS_BKLEN (1 << 3) 123 124#define CH7017_POWER_SEQUENCING_T1 0x67 125#define CH7017_POWER_SEQUENCING_T2 0x68 126#define CH7017_POWER_SEQUENCING_T3 0x69 127#define CH7017_POWER_SEQUENCING_T4 0x6a 128#define CH7017_POWER_SEQUENCING_T5 0x6b 129#define CH7017_GPIO_DRIVER_TYPE 0x6c 130#define CH7017_GPIO_DATA 0x6d 131#define CH7017_GPIO_DIRECTION_CONTROL 0x6e 132 133#define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71 134# define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4 135# define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0 136# define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80 137 138#define CH7017_LVDS_PLL_VCO_CONTROL 0x72 139# define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80 140# define CH7017_LVDS_PLL_VCO_SHIFT 4 141# define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0 142 143#define CH7017_OUTPUTS_ENABLE 0x73 144# define CH7017_CHARGE_PUMP_LOW 0x0 145# define CH7017_CHARGE_PUMP_HIGH 0x3 146# define CH7017_LVDS_CHANNEL_A (1 << 3) 147# define CH7017_LVDS_CHANNEL_B (1 << 4) 148# define CH7017_TV_DAC_A (1 << 5) 149# define CH7017_TV_DAC_B (1 << 6) 150# define CH7017_DDC_SELECT_DC2 (1 << 7) 151 152#define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74 153#define CH7017_LVDS_PLL_EMI_REDUCTION 0x75 154#define CH7017_LVDS_POWER_DOWN_FLICKER 0x76 155 156#define CH7017_LVDS_CONTROL_2 0x78 157# define CH7017_LOOP_FILTER_SHIFT 5 158# define CH7017_PHASE_DETECTOR_SHIFT 0 159 160#define CH7017_BANG_LIMIT_CONTROL 0x7f 161 162struct ch7017_priv { 163 u8 dummy; 164}; 165 166static void ch7017_dump_regs(struct intel_dvo_device *dvo); 167static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable); 168 169static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val) 170{ 171 struct i2c_msg msgs[] = { 172 { 173 .addr = dvo->slave_addr, 174 .flags = 0, 175 .len = 1, 176 .buf = &addr, 177 }, 178 { 179 .addr = dvo->slave_addr, 180 .flags = I2C_M_RD, 181 .len = 1, 182 .buf = val, 183 } 184 }; 185 return i2c_transfer(dvo->i2c_bus, msgs, 2) == 2; 186} 187 188static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val) 189{ 190 u8 buf[2] = { addr, val }; 191 struct i2c_msg msg = { 192 .addr = dvo->slave_addr, 193 .flags = 0, 194 .len = 2, 195 .buf = buf, 196 }; 197 return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1; 198} 199 200/** Probes for a CH7017 on the given bus and slave address. */ 201static bool ch7017_init(struct intel_dvo_device *dvo, 202 struct i2c_adapter *adapter) 203{ 204 struct ch7017_priv *priv; 205 const char *str; 206 u8 val; 207 208 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 209 if (priv == NULL) 210 return false; 211 212 dvo->i2c_bus = adapter; 213 dvo->dev_priv = priv; 214 215 if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val)) 216 goto fail; 217 218 switch (val) { 219 case CH7017_DEVICE_ID_VALUE: 220 str = "ch7017"; 221 break; 222 case CH7018_DEVICE_ID_VALUE: 223 str = "ch7018"; 224 break; 225 case CH7019_DEVICE_ID_VALUE: 226 str = "ch7019"; 227 break; 228 default: 229 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s " 230 "slave %d.\n", 231 val, adapter->name, dvo->slave_addr); 232 goto fail; 233 } 234 235 DRM_DEBUG_KMS("%s detected on %s, addr %d\n", 236 str, adapter->name, dvo->slave_addr); 237 return true; 238 239fail: 240 kfree(priv); 241 return false; 242} 243 244static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo) 245{ 246 return connector_status_connected; 247} 248 249static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo, 250 struct drm_display_mode *mode) 251{ 252 if (mode->clock > 160000) 253 return MODE_CLOCK_HIGH; 254 255 return MODE_OK; 256} 257 258static void ch7017_mode_set(struct intel_dvo_device *dvo, 259 const struct drm_display_mode *mode, 260 const struct drm_display_mode *adjusted_mode) 261{ 262 u8 lvds_pll_feedback_div, lvds_pll_vco_control; 263 u8 outputs_enable, lvds_control_2, lvds_power_down; 264 u8 horizontal_active_pixel_input; 265 u8 horizontal_active_pixel_output, vertical_active_line_output; 266 u8 active_input_line_output; 267 268 DRM_DEBUG_KMS("Registers before mode setting\n"); 269 ch7017_dump_regs(dvo); 270 271 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/ 272 if (mode->clock < 100000) { 273 outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_LOW; 274 lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED | 275 (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) | 276 (13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT); 277 lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | 278 (2 << CH7017_LVDS_PLL_VCO_SHIFT) | 279 (3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); 280 lvds_control_2 = (1 << CH7017_LOOP_FILTER_SHIFT) | 281 (0 << CH7017_PHASE_DETECTOR_SHIFT); 282 } else { 283 outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH; 284 lvds_pll_feedback_div = 285 CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED | 286 (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) | 287 (3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT); 288 lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) | 289 (0 << CH7017_PHASE_DETECTOR_SHIFT); 290 if (1) { /* XXX: dual channel panel detection. Assume yes for now. */ 291 outputs_enable |= CH7017_LVDS_CHANNEL_B; 292 lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | 293 (2 << CH7017_LVDS_PLL_VCO_SHIFT) | 294 (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); 295 } else { 296 lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | 297 (1 << CH7017_LVDS_PLL_VCO_SHIFT) | 298 (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); 299 } 300 } 301 302 horizontal_active_pixel_input = mode->hdisplay & 0x00ff; 303 304 vertical_active_line_output = mode->vdisplay & 0x00ff; 305 horizontal_active_pixel_output = mode->hdisplay & 0x00ff; 306 307 active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) | 308 (((mode->vdisplay & 0x0700) >> 8) << 3); 309 310 lvds_power_down = CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED | 311 (mode->hdisplay & 0x0700) >> 8; 312 313 ch7017_dpms(dvo, false); 314 ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, 315 horizontal_active_pixel_input); 316 ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT, 317 horizontal_active_pixel_output); 318 ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, 319 vertical_active_line_output); 320 ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, 321 active_input_line_output); 322 ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control); 323 ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div); 324 ch7017_write(dvo, CH7017_LVDS_CONTROL_2, lvds_control_2); 325 ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, outputs_enable); 326 327 /* Turn the LVDS back on with new settings. */ 328 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); 329 330 DRM_DEBUG_KMS("Registers after mode setting\n"); 331 ch7017_dump_regs(dvo); 332} 333 334/* set the CH7017 power state */ 335static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable) 336{ 337 u8 val; 338 339 ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); 340 341 /* Turn off TV/VGA, and never turn it on since we don't support it. */ 342 ch7017_write(dvo, CH7017_POWER_MANAGEMENT, 343 CH7017_DAC0_POWER_DOWN | 344 CH7017_DAC1_POWER_DOWN | 345 CH7017_DAC2_POWER_DOWN | 346 CH7017_DAC3_POWER_DOWN | 347 CH7017_TV_POWER_DOWN_EN); 348 349 if (enable) { 350 /* Turn on the LVDS */ 351 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, 352 val & ~CH7017_LVDS_POWER_DOWN_EN); 353 } else { 354 /* Turn off the LVDS */ 355 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, 356 val | CH7017_LVDS_POWER_DOWN_EN); 357 } 358 359 /* XXX: Should actually wait for update power status somehow */ 360 msleep(20); 361} 362 363static bool ch7017_get_hw_state(struct intel_dvo_device *dvo) 364{ 365 u8 val; 366 367 ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); 368 369 if (val & CH7017_LVDS_POWER_DOWN_EN) 370 return false; 371 else 372 return true; 373} 374 375static void ch7017_dump_regs(struct intel_dvo_device *dvo) 376{ 377 u8 val; 378 379#define DUMP(reg) \ 380do { \ 381 ch7017_read(dvo, reg, &val); \ 382 DRM_DEBUG_KMS(#reg ": %02x\n", val); \ 383} while (0) 384 385 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT); 386 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT); 387 DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT); 388 DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT); 389 DUMP(CH7017_LVDS_PLL_VCO_CONTROL); 390 DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV); 391 DUMP(CH7017_LVDS_CONTROL_2); 392 DUMP(CH7017_OUTPUTS_ENABLE); 393 DUMP(CH7017_LVDS_POWER_DOWN); 394} 395 396static void ch7017_destroy(struct intel_dvo_device *dvo) 397{ 398 struct ch7017_priv *priv = dvo->dev_priv; 399 400 if (priv) { 401 kfree(priv); 402 dvo->dev_priv = NULL; 403 } 404} 405 406const struct intel_dvo_dev_ops ch7017_ops = { 407 .init = ch7017_init, 408 .detect = ch7017_detect, 409 .mode_valid = ch7017_mode_valid, 410 .mode_set = ch7017_mode_set, 411 .dpms = ch7017_dpms, 412 .get_hw_state = ch7017_get_hw_state, 413 .dump_regs = ch7017_dump_regs, 414 .destroy = ch7017_destroy, 415}; 416