1/* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __SMU_V14_0_0_PMFW_H__ 25#define __SMU_V14_0_0_PMFW_H__ 26 27#include "smu14_driver_if_v14_0_0.h" 28 29#pragma pack(push, 1) 30 31#define ENABLE_DEBUG_FEATURES 32 33// Firmware features 34// Feature Control Defines 35#define FEATURE_CCLK_DPM_BIT 0 36#define FEATURE_FAN_CONTROLLER_BIT 1 37#define FEATURE_DATA_CALCULATION_BIT 2 38#define FEATURE_PPT_BIT 3 39#define FEATURE_TDC_BIT 4 40#define FEATURE_THERMAL_BIT 5 41#define FEATURE_FIT_BIT 6 42#define FEATURE_EDC_BIT 7 43#define FEATURE_PLL_POWER_DOWN_BIT 8 44#define FEATURE_VDDOFF_BIT 9 45#define FEATURE_VCN_DPM_BIT 10 /* this is for both VCN0 and VCN1 */ 46#define FEATURE_DS_MPM_BIT 11 47#define FEATURE_FCLK_DPM_BIT 12 48#define FEATURE_SOCCLK_DPM_BIT 13 49#define FEATURE_DS_MPIO_BIT 14 50#define FEATURE_LCLK_DPM_BIT 15 51#define FEATURE_SHUBCLK_DPM_BIT 16 52#define FEATURE_DCFCLK_DPM_BIT 17 53#define FEATURE_ISP_DPM_BIT 18 54#define FEATURE_IPU_DPM_BIT 19 55#define FEATURE_GFX_DPM_BIT 20 56#define FEATURE_DS_GFXCLK_BIT 21 57#define FEATURE_DS_SOCCLK_BIT 22 58#define FEATURE_DS_LCLK_BIT 23 59#define FEATURE_LOW_POWER_DCNCLKS_BIT 24 60#define FEATURE_DS_SHUBCLK_BIT 25 61#define FEATURE_RESERVED0_BIT 26 62#define FEATURE_ZSTATES_BIT 27 63#define FEATURE_IOMMUL2_PG_BIT 28 64#define FEATURE_DS_FCLK_BIT 29 65#define FEATURE_DS_SMNCLK_BIT 30 66#define FEATURE_DS_MP1CLK_BIT 31 67#define FEATURE_WHISPER_MODE_BIT 32 68#define FEATURE_SMU_LOW_POWER_BIT 33 69#define FEATURE_RESERVED1_BIT 34 /* v14_0_0 SMART_L3_RINSER; v14_0_1 RESERVED1 */ 70#define FEATURE_GFX_DEM_BIT 35 /* v14_0_0 SPARE; v14_0_1 GFX_DEM */ 71#define FEATURE_PSI_BIT 36 72#define FEATURE_PROCHOT_BIT 37 73#define FEATURE_CPUOFF_BIT 38 74#define FEATURE_STAPM_BIT 39 75#define FEATURE_S0I3_BIT 40 76#define FEATURE_DF_LIGHT_CSTATE 41 77#define FEATURE_PERF_LIMIT_BIT 42 78#define FEATURE_CORE_DLDO_BIT 43 79#define FEATURE_DVO_BIT 44 80#define FEATURE_DS_VCN_BIT 45 /* v14_0_1 this is for both VCN0 and VCN1 */ 81#define FEATURE_CPPC_BIT 46 82#define FEATURE_CPPC_PREFERRED_CORES 47 83#define FEATURE_DF_CSTATES_BIT 48 84#define FEATURE_FAST_PSTATE_CLDO_BIT 49 /* v14_0_0 SPARE */ 85#define FEATURE_ATHUB_PG_BIT 50 86#define FEATURE_VDDOFF_ECO_BIT 51 87#define FEATURE_ZSTATES_ECO_BIT 52 88#define FEATURE_CC6_BIT 53 89#define FEATURE_DS_UMCCLK_BIT 54 90#define FEATURE_DS_ISPCLK_BIT 55 91#define FEATURE_DS_HSPCLK_BIT 56 92#define FEATURE_P3T_BIT 57 93#define FEATURE_DS_IPUCLK_BIT 58 94#define FEATURE_DS_VPECLK_BIT 59 95#define FEATURE_VPE_DPM_BIT 60 96#define FEATURE_SMART_L3_RINSER_BIT 61 /* v14_0_0 SPARE*/ 97#define FEATURE_PCC_BIT 62 /* v14_0_0 FP_DIDT v14_0_1 PCC_BIT */ 98#define NUM_FEATURES 63 99 100// Firmware Header/Footer 101struct SMU14_Firmware_Footer { 102 uint32_t Signature; 103}; 104typedef struct SMU14_Firmware_Footer SMU14_Firmware_Footer; 105 106// PSP3.0 Header Definition 107typedef struct { 108 uint32_t ImageVersion; 109 uint32_t ImageVersion2; // This is repeated because DW0 cannot be written in SRAM due to HW bug. 110 uint32_t Padding0[3]; 111 uint32_t SizeFWSigned; 112 uint32_t Padding1[25]; 113 uint32_t FirmwareType; 114 uint32_t Filler[32]; 115} SMU_Firmware_Header; 116 117typedef struct { 118 // MP1_EXT_SCRATCH0 119 uint32_t DpmHandlerID : 8; 120 uint32_t ActivityMonitorID : 8; 121 uint32_t DpmTimerID : 8; 122 uint32_t DpmHubID : 4; 123 uint32_t DpmHubTask : 4; 124 // MP1_EXT_SCRATCH1 125 uint32_t CclkSyncStatus : 8; 126 uint32_t Ccx0CpuOff : 2; 127 uint32_t Ccx1CpuOff : 2; 128 uint32_t GfxOffStatus : 2; 129 uint32_t VddOff : 1; 130 uint32_t InWhisperMode : 1; 131 uint32_t ZstateStatus : 4; 132 uint32_t spare0 : 4; 133 uint32_t DstateFun : 4; 134 uint32_t DstateDev : 4; 135 // MP1_EXT_SCRATCH2 136 uint32_t P2JobHandler :24; 137 uint32_t RsmuPmiP2PendingCnt : 8; 138 // MP1_EXT_SCRATCH3 139 uint32_t PostCode :32; 140 // MP1_EXT_SCRATCH4 141 uint32_t MsgPortBusy :24; 142 uint32_t RsmuPmiP1Pending : 1; 143 uint32_t DfCstateExitPending : 1; 144 uint32_t Ccx0Pc6ExitPending : 1; 145 uint32_t Ccx1Pc6ExitPending : 1; 146 uint32_t WarmResetPending : 1; 147 uint32_t spare1 : 3; 148 // MP1_EXT_SCRATCH5 149 uint32_t IdleMask :32; 150 // MP1_EXT_SCRATCH6 = RTOS threads' status 151 // MP1_EXT_SCRATCH7 = RTOS Current Job 152} FwStatus_t; 153 154typedef struct { 155 // MP1_EXT_SCRATCH0 156 uint32_t DpmHandlerID : 8; 157 uint32_t ActivityMonitorID : 8; 158 uint32_t DpmTimerID : 8; 159 uint32_t DpmHubID : 4; 160 uint32_t DpmHubTask : 4; 161 // MP1_EXT_SCRATCH1 162 uint32_t CclkSyncStatus : 8; 163 uint32_t ZstateStatus : 4; 164 uint32_t Cpu1VddOff : 4; 165 uint32_t DstateFun : 4; 166 uint32_t DstateDev : 4; 167 uint32_t GfxOffStatus : 2; 168 uint32_t Cpu0Off : 2; 169 uint32_t Cpu1Off : 2; 170 uint32_t Cpu0VddOff : 2; 171 // MP1_EXT_SCRATCH2 172 uint32_t P2JobHandler :32; 173 // MP1_EXT_SCRATCH3 174 uint32_t PostCode :32; 175 // MP1_EXT_SCRATCH4 176 uint32_t MsgPortBusy :15; 177 uint32_t RsmuPmiP1Pending : 1; 178 uint32_t RsmuPmiP2PendingCnt : 8; 179 uint32_t DfCstateExitPending : 1; 180 uint32_t Pc6EntryPending : 1; 181 uint32_t Pc6ExitPending : 1; 182 uint32_t WarmResetPending : 1; 183 uint32_t Mp0ClkPending : 1; 184 uint32_t InWhisperMode : 1; 185 uint32_t spare2 : 2; 186 // MP1_EXT_SCRATCH5 187 uint32_t IdleMask :32; 188 // MP1_EXT_SCRATCH6 = RTOS threads' status 189 // MP1_EXT_SCRATCH7 = RTOS Current Job 190} FwStatus_t_v14_0_1; 191 192#pragma pack(pop) 193 194#endif 195