1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef SMU_13_0_6_DRIVER_IF_H
24#define SMU_13_0_6_DRIVER_IF_H
25
26// *** IMPORTANT ***
27// PMFW TEAM: Always increment the interface version if
28// anything is changed in this file
29#define SMU13_0_6_DRIVER_IF_VERSION 0x08042024
30
31//I2C Interface
32#define NUM_I2C_CONTROLLERS                8
33#define I2C_CONTROLLER_ENABLED             1
34#define I2C_CONTROLLER_DISABLED            0
35
36#define MAX_SW_I2C_COMMANDS                24
37
38typedef enum {
39  I2C_CONTROLLER_PORT_0, //CKSVII2C0
40  I2C_CONTROLLER_PORT_1, //CKSVII2C1
41  I2C_CONTROLLER_PORT_COUNT,
42} I2cControllerPort_e;
43
44typedef enum {
45  UNSUPPORTED_1,              //50  Kbits/s not supported anymore!
46  I2C_SPEED_STANDARD_100K,    //100 Kbits/s
47  I2C_SPEED_FAST_400K,        //400 Kbits/s
48  I2C_SPEED_FAST_PLUS_1M,     //1   Mbits/s (in fast mode)
49  UNSUPPORTED_2,              //1   Mbits/s (in high speed mode)  not supported anymore!
50  UNSUPPORTED_3,              //2.3 Mbits/s  not supported anymore!
51  I2C_SPEED_COUNT,
52} I2cSpeed_e;
53
54typedef enum {
55  I2C_CMD_READ,
56  I2C_CMD_WRITE,
57  I2C_CMD_COUNT,
58} I2cCmdType_e;
59
60#define CMDCONFIG_STOP_BIT             0
61#define CMDCONFIG_RESTART_BIT          1
62#define CMDCONFIG_READWRITE_BIT        2 //bit should be 0 for read, 1 for write
63
64#define CMDCONFIG_STOP_MASK           (1 << CMDCONFIG_STOP_BIT)
65#define CMDCONFIG_RESTART_MASK        (1 << CMDCONFIG_RESTART_BIT)
66#define CMDCONFIG_READWRITE_MASK      (1 << CMDCONFIG_READWRITE_BIT)
67
68typedef enum {
69  // MMHUB
70  CODE_DAGB0,
71  CODE_EA0 = 5,
72  CODE_UTCL2_ROUTER = 10,
73  CODE_VML2,
74  CODE_VML2_WALKER,
75  CODE_MMCANE,
76
77  // VCN
78  // VCN VCPU
79  CODE_VIDD,
80  CODE_VIDV,
81  // VCN JPEG
82  CODE_JPEG0S,
83  CODE_JPEG0D,
84  CODE_JPEG1S,
85  CODE_JPEG1D,
86  CODE_JPEG2S,
87  CODE_JPEG2D,
88  CODE_JPEG3S,
89  CODE_JPEG3D,
90  CODE_JPEG4S,
91  CODE_JPEG4D,
92  CODE_JPEG5S,
93  CODE_JPEG5D,
94  CODE_JPEG6S,
95  CODE_JPEG6D,
96  CODE_JPEG7S,
97  CODE_JPEG7D,
98  // VCN MMSCH
99  CODE_MMSCHD,
100
101  // SDMA
102  CODE_SDMA0,
103  CODE_SDMA1,
104  CODE_SDMA2,
105  CODE_SDMA3,
106
107  // SOC
108  CODE_HDP,
109  CODE_ATHUB,
110  CODE_IH,
111  CODE_XHUB_POISON,
112  CODE_SMN_SLVERR = 40,
113  CODE_WDT,
114
115  CODE_UNKNOWN = 42,
116  CODE_COUNT,
117} ERR_CODE_e;
118
119typedef enum {
120  // SH POISON FED
121  SH_FED_CODE,
122  // GCEA Pin UE_ERR regs
123  GCEA_CODE,
124  SQ_CODE,
125  LDS_CODE,
126  GDS_CODE,
127  SP0_CODE,
128  SP1_CODE,
129  TCC_CODE,
130  TCA_CODE,
131  TCX_CODE,
132  CPC_CODE,
133  CPF_CODE,
134  CPG_CODE,
135  SPI_CODE,
136  RLC_CODE,
137  // GCEA Pin, UE_EDC regs
138  SQC_CODE,
139  TA_CODE,
140  TD_CODE,
141  TCP_CODE,
142  TCI_CODE,
143  // GC Router
144  GC_ROUTER_CODE,
145  VML2_CODE,
146  VML2_WALKER_CODE,
147  ATCL2_CODE,
148  GC_CANE_CODE,
149
150  // SOC error codes 40-42 are common with ERR_CODE_e
151  MP5_CODE_SMN_SLVERR = 40,
152  MP5_CODE_UNKNOWN = 42,
153} GC_ERROR_CODE_e;
154
155
156typedef struct {
157  uint8_t ReadWriteData;  //Return data for read. Data to send for write
158  uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
159} SwI2cCmd_t; //SW I2C Command Table
160
161typedef struct {
162  uint8_t    I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
163  uint8_t    I2CSpeed;          //Use I2cSpeed_e to indicate speed to select
164  uint8_t    SlaveAddress;      //Slave address of device
165  uint8_t    NumCmds;           //Number of commands
166  SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
167} SwI2cRequest_t; // SW I2C Request Table
168
169typedef struct {
170  SwI2cRequest_t SwI2cRequest;
171  uint32_t       Spare[8];
172  uint32_t       MmHubPadding[8]; // SMU internal use
173} SwI2cRequestExternal_t;
174
175typedef enum {
176  PPCLK_VCLK,
177  PPCLK_DCLK,
178  PPCLK_SOCCLK,
179  PPCLK_UCLK,
180  PPCLK_FCLK,
181  PPCLK_LCLK,
182  PPCLK_COUNT,
183} PPCLK_e;
184
185typedef enum {
186  GPIO_INT_POLARITY_ACTIVE_LOW,
187  GPIO_INT_POLARITY_ACTIVE_HIGH,
188} GpioIntPolarity_e;
189
190//TODO confirm if this is used in SMU_13_0_6 PPSMC_MSG_SetUclkDpmMode
191typedef enum {
192  UCLK_DPM_MODE_BANDWIDTH,
193  UCLK_DPM_MODE_LATENCY,
194} UCLK_DPM_MODE_e;
195
196typedef struct {
197  //0-23 SOC, 24-26 SOCIO, 27-29 SOC
198  uint16_t avgPsmCount[30];
199  uint16_t minPsmCount[30];
200  float    avgPsmVoltage[30];
201  float    minPsmVoltage[30];
202} AvfsDebugTableAid_t;
203
204typedef struct {
205  //0-27 GFX, 28-29 SOC
206  uint16_t avgPsmCount[30];
207  uint16_t minPsmCount[30];
208  float    avgPsmVoltage[30];
209  float    minPsmVoltage[30];
210} AvfsDebugTableXcd_t;
211
212// Defines used for IH-based thermal interrupts to GFX driver - A/X only
213#define IH_INTERRUPT_ID_TO_DRIVER                   0xFE
214#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
215
216//thermal over-temp mask defines for IH interrupt to host
217#define THROTTLER_PROCHOT_BIT           0
218#define THROTTLER_PPT_BIT               1
219#define THROTTLER_THERMAL_SOCKET_BIT    2//AID, XCD, CCD throttling
220#define THROTTLER_THERMAL_VR_BIT        3//VRHOT
221#define THROTTLER_THERMAL_HBM_BIT       4
222
223#define ClearMcaOnRead_UE_FLAG_MASK              0x1
224#define ClearMcaOnRead_CE_POLL_MASK              0x2
225
226// These defines are used with the following messages:
227// SMC_MSG_TransferTableDram2Smu
228// SMC_MSG_TransferTableSmu2Dram
229// #define TABLE_PPTABLE                 0
230// #define TABLE_AVFS_PSM_DEBUG          1
231// #define TABLE_AVFS_FUSE_OVERRIDE      2
232// #define TABLE_PMSTATUSLOG             3
233// #define TABLE_SMU_METRICS             4
234// #define TABLE_DRIVER_SMU_CONFIG       5
235// #define TABLE_I2C_COMMANDS            6
236// #define TABLE_COUNT                   7
237
238// // Table transfer status
239// #define TABLE_TRANSFER_OK         0x0
240// #define TABLE_TRANSFER_FAILED     0xFF
241// #define TABLE_TRANSFER_PENDING    0xAB
242
243#endif
244