1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef __SMU11_DRIVER_IF_NAVI10_H__ 24#define __SMU11_DRIVER_IF_NAVI10_H__ 25 26// *** IMPORTANT *** 27// SMU TEAM: Always increment the interface version if 28// any structure is changed in this file 29// Be aware of that the version should be updated in 30// smu_v11_0.h, maybe rename is also needed. 31// #define SMU11_DRIVER_IF_VERSION 0x33 32 33#define PPTABLE_NV10_SMU_VERSION 8 34 35#define NUM_GFXCLK_DPM_LEVELS 16 36#define NUM_SMNCLK_DPM_LEVELS 2 37#define NUM_SOCCLK_DPM_LEVELS 8 38#define NUM_MP0CLK_DPM_LEVELS 2 39#define NUM_DCLK_DPM_LEVELS 8 40#define NUM_VCLK_DPM_LEVELS 8 41#define NUM_DCEFCLK_DPM_LEVELS 8 42#define NUM_PHYCLK_DPM_LEVELS 8 43#define NUM_DISPCLK_DPM_LEVELS 8 44#define NUM_PIXCLK_DPM_LEVELS 8 45#define NUM_UCLK_DPM_LEVELS 4 46#define NUM_MP1CLK_DPM_LEVELS 2 47#define NUM_LINK_LEVELS 2 48 49 50#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 51#define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 52#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 53#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 54#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 55#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 56#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 57#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 58#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 59#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 60#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 61#define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 62#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 63 64//Gemini Modes 65#define PPSMC_GeminiModeNone 0 //Single GPU board 66#define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 67#define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 68 69// Feature Control Defines 70// DPM 71#define FEATURE_DPM_PREFETCHER_BIT 0 72#define FEATURE_DPM_GFXCLK_BIT 1 73#define FEATURE_DPM_GFX_PACE_BIT 2 74#define FEATURE_DPM_UCLK_BIT 3 75#define FEATURE_DPM_SOCCLK_BIT 4 76#define FEATURE_DPM_MP0CLK_BIT 5 77#define FEATURE_DPM_LINK_BIT 6 78#define FEATURE_DPM_DCEFCLK_BIT 7 79#define FEATURE_MEM_VDDCI_SCALING_BIT 8 80#define FEATURE_MEM_MVDD_SCALING_BIT 9 81 82//Idle 83#define FEATURE_DS_GFXCLK_BIT 10 84#define FEATURE_DS_SOCCLK_BIT 11 85#define FEATURE_DS_LCLK_BIT 12 86#define FEATURE_DS_DCEFCLK_BIT 13 87#define FEATURE_DS_UCLK_BIT 14 88#define FEATURE_GFX_ULV_BIT 15 89#define FEATURE_FW_DSTATE_BIT 16 90#define FEATURE_GFXOFF_BIT 17 91#define FEATURE_BACO_BIT 18 92#define FEATURE_VCN_PG_BIT 19 93#define FEATURE_JPEG_PG_BIT 20 94#define FEATURE_USB_PG_BIT 21 95#define FEATURE_RSMU_SMN_CG_BIT 22 96//Throttler/Response 97#define FEATURE_PPT_BIT 23 98#define FEATURE_TDC_BIT 24 99#define FEATURE_GFX_EDC_BIT 25 100#define FEATURE_APCC_PLUS_BIT 26 101#define FEATURE_GTHR_BIT 27 102#define FEATURE_ACDC_BIT 28 103#define FEATURE_VR0HOT_BIT 29 104#define FEATURE_VR1HOT_BIT 30 105#define FEATURE_FW_CTF_BIT 31 106#define FEATURE_FAN_CONTROL_BIT 32 107#define FEATURE_THERMAL_BIT 33 108#define FEATURE_GFX_DCS_BIT 34 109//VF 110#define FEATURE_RM_BIT 35 111#define FEATURE_LED_DISPLAY_BIT 36 112//Other 113#define FEATURE_GFX_SS_BIT 37 114#define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 115#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 116 117#define FEATURE_MMHUB_PG_BIT 40 118#define FEATURE_ATHUB_PG_BIT 41 119#define FEATURE_APCC_DFLL_BIT 42 120#define FEATURE_SPARE_43_BIT 43 121#define FEATURE_SPARE_44_BIT 44 122#define FEATURE_SPARE_45_BIT 45 123#define FEATURE_SPARE_46_BIT 46 124#define FEATURE_SPARE_47_BIT 47 125#define FEATURE_SPARE_48_BIT 48 126#define FEATURE_SPARE_49_BIT 49 127#define FEATURE_SPARE_50_BIT 50 128#define FEATURE_SPARE_51_BIT 51 129#define FEATURE_SPARE_52_BIT 52 130#define FEATURE_SPARE_53_BIT 53 131#define FEATURE_SPARE_54_BIT 54 132#define FEATURE_SPARE_55_BIT 55 133#define FEATURE_SPARE_56_BIT 56 134#define FEATURE_SPARE_57_BIT 57 135#define FEATURE_SPARE_58_BIT 58 136#define FEATURE_SPARE_59_BIT 59 137#define FEATURE_SPARE_60_BIT 60 138#define FEATURE_SPARE_61_BIT 61 139#define FEATURE_SPARE_62_BIT 62 140#define FEATURE_SPARE_63_BIT 63 141#define NUM_FEATURES 64 142 143// Debug Overrides Bitmask 144#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 145#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 146#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_SOCCLK 0x00000004 147#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000008 148#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000010 149#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 150#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 151#define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_SOCCLK 0x00000080 152#define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 153#define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 154#define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 155 156// VR Mapping Bit Defines 157#define VR_MAPPING_VR_SELECT_MASK 0x01 158#define VR_MAPPING_VR_SELECT_SHIFT 0x00 159 160#define VR_MAPPING_PLANE_SELECT_MASK 0x02 161#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 162 163// PSI Bit Defines 164#define PSI_SEL_VR0_PLANE0_PSI0 0x01 165#define PSI_SEL_VR0_PLANE0_PSI1 0x02 166#define PSI_SEL_VR0_PLANE1_PSI0 0x04 167#define PSI_SEL_VR0_PLANE1_PSI1 0x08 168#define PSI_SEL_VR1_PLANE0_PSI0 0x10 169#define PSI_SEL_VR1_PLANE0_PSI1 0x20 170#define PSI_SEL_VR1_PLANE1_PSI0 0x40 171#define PSI_SEL_VR1_PLANE1_PSI1 0x80 172 173// Throttler Control/Status Bits 174#define THROTTLER_PADDING_BIT 0 175#define THROTTLER_TEMP_EDGE_BIT 1 176#define THROTTLER_TEMP_HOTSPOT_BIT 2 177#define THROTTLER_TEMP_MEM_BIT 3 178#define THROTTLER_TEMP_VR_GFX_BIT 4 179#define THROTTLER_TEMP_VR_MEM0_BIT 5 180#define THROTTLER_TEMP_VR_MEM1_BIT 6 181#define THROTTLER_TEMP_VR_SOC_BIT 7 182#define THROTTLER_TEMP_LIQUID0_BIT 8 183#define THROTTLER_TEMP_LIQUID1_BIT 9 184#define THROTTLER_TEMP_PLX_BIT 10 185#define THROTTLER_TEMP_SKIN_BIT 11 186#define THROTTLER_TDC_GFX_BIT 12 187#define THROTTLER_TDC_SOC_BIT 13 188#define THROTTLER_PPT0_BIT 14 189#define THROTTLER_PPT1_BIT 15 190#define THROTTLER_PPT2_BIT 16 191#define THROTTLER_PPT3_BIT 17 192#define THROTTLER_FIT_BIT 18 193#define THROTTLER_PPM_BIT 19 194#define THROTTLER_APCC_BIT 20 195 196// FW DState Features Control Bits 197#define FW_DSTATE_SOC_ULV_BIT 0 198#define FW_DSTATE_G6_HSR_BIT 1 199#define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 200#define FW_DSTATE_MP0_DS_BIT 3 201#define FW_DSTATE_SMN_DS_BIT 4 202#define FW_DSTATE_MP1_DS_BIT 5 203#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 204#define FW_DSTATE_LIV_MIN_BIT 7 205#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 206 207#define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 208#define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 209#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 210#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 211#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 212#define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 213#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 214#define FW_DSTATE_LIV_MIN_MASK (1 << FW_DSTATE_LIV_MIN_BIT ) 215#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 216 217//I2C Interface 218 219#define NUM_I2C_CONTROLLERS 8 220 221#define I2C_CONTROLLER_ENABLED 1 222#define I2C_CONTROLLER_DISABLED 0 223 224#define MAX_SW_I2C_COMMANDS 8 225 226typedef enum { 227 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 228 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 229 I2C_CONTROLLER_PORT_COUNT, 230} I2cControllerPort_e; 231 232typedef enum { 233 I2C_CONTROLLER_NAME_VR_GFX = 0, 234 I2C_CONTROLLER_NAME_VR_SOC, 235 I2C_CONTROLLER_NAME_VR_VDDCI, 236 I2C_CONTROLLER_NAME_VR_MVDD, 237 I2C_CONTROLLER_NAME_LIQUID0, 238 I2C_CONTROLLER_NAME_LIQUID1, 239 I2C_CONTROLLER_NAME_PLX, 240 I2C_CONTROLLER_NAME_SPARE, 241 I2C_CONTROLLER_NAME_COUNT, 242} I2cControllerName_e; 243 244typedef enum { 245 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 246 I2C_CONTROLLER_THROTTLER_VR_GFX, 247 I2C_CONTROLLER_THROTTLER_VR_SOC, 248 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 249 I2C_CONTROLLER_THROTTLER_VR_MVDD, 250 I2C_CONTROLLER_THROTTLER_LIQUID0, 251 I2C_CONTROLLER_THROTTLER_LIQUID1, 252 I2C_CONTROLLER_THROTTLER_PLX, 253 I2C_CONTROLLER_THROTTLER_COUNT, 254} I2cControllerThrottler_e; 255 256typedef enum { 257 I2C_CONTROLLER_PROTOCOL_VR_0, 258 I2C_CONTROLLER_PROTOCOL_VR_1, 259 I2C_CONTROLLER_PROTOCOL_TMP_0, 260 I2C_CONTROLLER_PROTOCOL_TMP_1, 261 I2C_CONTROLLER_PROTOCOL_SPARE_0, 262 I2C_CONTROLLER_PROTOCOL_SPARE_1, 263 I2C_CONTROLLER_PROTOCOL_COUNT, 264} I2cControllerProtocol_e; 265 266typedef struct { 267 uint8_t Enabled; 268 uint8_t Speed; 269 uint8_t Padding[2]; 270 uint32_t SlaveAddress; 271 uint8_t ControllerPort; 272 uint8_t ControllerName; 273 uint8_t ThermalThrotter; 274 uint8_t I2cProtocol; 275} I2cControllerConfig_t; 276 277typedef enum { 278 I2C_PORT_SVD_SCL = 0, 279 I2C_PORT_GPIO, 280} I2cPort_e; 281 282typedef enum { 283 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 284 I2C_SPEED_FAST_100K, //100 Kbits/s 285 I2C_SPEED_FAST_400K, //400 Kbits/s 286 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 287 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 288 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 289 I2C_SPEED_COUNT, 290} I2cSpeed_e; 291 292typedef enum { 293 I2C_CMD_READ = 0, 294 I2C_CMD_WRITE, 295 I2C_CMD_COUNT, 296} I2cCmdType_e; 297 298#define CMDCONFIG_STOP_BIT 0 299#define CMDCONFIG_RESTART_BIT 1 300 301#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 302#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 303 304typedef struct { 305 uint8_t RegisterAddr; ////only valid for write, ignored for read 306 uint8_t Cmd; //Read(0) or Write(1) 307 uint8_t Data; //Return data for read. Data to send for write 308 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command 309} SwI2cCmd_t; //SW I2C Command Table 310 311typedef struct { 312 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 313 uint8_t I2CSpeed; //Slow(0) or Fast(1) 314 uint16_t SlaveAddress; 315 uint8_t NumCmds; //Number of commands 316 uint8_t Padding[3]; 317 318 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 319 320 uint32_t MmHubPadding[8]; // SMU internal use 321 322} SwI2cRequest_t; // SW I2C Request Table 323 324//D3HOT sequences 325typedef enum { 326 BACO_SEQUENCE, 327 MSR_SEQUENCE, 328 BAMACO_SEQUENCE, 329 ULPS_SEQUENCE, 330 D3HOT_SEQUENCE_COUNT, 331}D3HOTSequence_e; 332 333//THis is aligned with RSMU PGFSM Register Mapping 334typedef enum { 335 PG_DYNAMIC_MODE = 0, 336 PG_STATIC_MODE, 337} PowerGatingMode_e; 338 339//This is aligned with RSMU PGFSM Register Mapping 340typedef enum { 341 PG_POWER_DOWN = 0, 342 PG_POWER_UP, 343} PowerGatingSettings_e; 344 345typedef struct { 346 uint32_t a; // store in IEEE float format in this variable 347 uint32_t b; // store in IEEE float format in this variable 348 uint32_t c; // store in IEEE float format in this variable 349} QuadraticInt_t; 350 351typedef struct { 352 uint32_t m; // store in IEEE float format in this variable 353 uint32_t b; // store in IEEE float format in this variable 354} LinearInt_t; 355 356typedef struct { 357 uint32_t a; // store in IEEE float format in this variable 358 uint32_t b; // store in IEEE float format in this variable 359 uint32_t c; // store in IEEE float format in this variable 360} DroopInt_t; 361 362typedef enum { 363 GFXCLK_SOURCE_PLL = 0, 364 GFXCLK_SOURCE_DFLL, 365 GFXCLK_SOURCE_COUNT, 366} GfxclkSrc_e; 367 368//Only Clks that have DPM descriptors are listed here 369typedef enum { 370 PPCLK_GFXCLK = 0, 371 PPCLK_SOCCLK, 372 PPCLK_UCLK, 373 PPCLK_DCLK, 374 PPCLK_VCLK, 375 PPCLK_DCEFCLK, 376 PPCLK_DISPCLK, 377 PPCLK_PIXCLK, 378 PPCLK_PHYCLK, 379 PPCLK_COUNT, 380} PPCLK_e; 381 382typedef enum { 383 POWER_SOURCE_AC, 384 POWER_SOURCE_DC, 385 POWER_SOURCE_COUNT, 386} POWER_SOURCE_e; 387 388typedef enum { 389 PPT_THROTTLER_PPT0, 390 PPT_THROTTLER_PPT1, 391 PPT_THROTTLER_PPT2, 392 PPT_THROTTLER_PPT3, 393 PPT_THROTTLER_COUNT 394} PPT_THROTTLER_e; 395 396typedef enum { 397 VOLTAGE_MODE_AVFS = 0, 398 VOLTAGE_MODE_AVFS_SS, 399 VOLTAGE_MODE_SS, 400 VOLTAGE_MODE_COUNT, 401} VOLTAGE_MODE_e; 402 403 404typedef enum { 405 AVFS_VOLTAGE_GFX = 0, 406 AVFS_VOLTAGE_SOC, 407 AVFS_VOLTAGE_COUNT, 408} AVFS_VOLTAGE_TYPE_e; 409 410typedef enum { 411 UCLK_DIV_BY_1 = 0, 412 UCLK_DIV_BY_2, 413 UCLK_DIV_BY_4, 414 UCLK_DIV_BY_8, 415} UCLK_DIV_e; 416 417typedef enum { 418 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 419 GPIO_INT_POLARITY_ACTIVE_HIGH, 420} GpioIntPolarity_e; 421 422typedef enum { 423 MEMORY_TYPE_GDDR6 = 0, 424 MEMORY_TYPE_HBM, 425} MemoryType_e; 426 427typedef enum { 428 PWR_CONFIG_TDP = 0, 429 PWR_CONFIG_TGP, 430 PWR_CONFIG_TCP_ESTIMATED, 431 PWR_CONFIG_TCP_MEASURED, 432} PwrConfig_e; 433 434typedef struct { 435 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 436 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 437 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 438 uint8_t Padding; 439 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 440 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 441} DpmDescriptor_t; 442 443typedef enum { 444 TEMP_EDGE, 445 TEMP_HOTSPOT, 446 TEMP_MEM, 447 TEMP_VR_GFX, 448 TEMP_VR_MEM0, 449 TEMP_VR_MEM1, 450 TEMP_VR_SOC, 451 TEMP_LIQUID0, 452 TEMP_LIQUID1, 453 TEMP_PLX, 454 TEMP_COUNT 455} TEMP_e; 456 457//Out of band monitor status defines 458//see SPEC //gpu/doc/soc_arch/spec/feature/SMBUS/SMBUS.xlsx 459#define POWER_MANAGER_CONTROLLER_NOT_RUNNING 0 460#define POWER_MANAGER_CONTROLLER_RUNNING 1 461 462#define POWER_MANAGER_CONTROLLER_BIT 0 463#define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT 8 464#define GPU_DIE_TEMPERATURE_THROTTLING_BIT 9 465#define HBM_DIE_TEMPERATURE_THROTTLING_BIT 10 466#define TGP_THROTTLING_BIT 11 467#define PCC_THROTTLING_BIT 12 468#define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT 13 469#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT 14 470 471#define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT ) 472#define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_MASK (1 << MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT ) 473#define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT ) 474#define HBM_DIE_TEMPERATURE_THROTTLING_MASK (1 << HBM_DIE_TEMPERATURE_THROTTLING_BIT ) 475#define TGP_THROTTLING_MASK (1 << TGP_THROTTLING_BIT ) 476#define PCC_THROTTLING_MASK (1 << PCC_THROTTLING_BIT ) 477#define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_MASK (1 << HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT ) 478#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT) 479 480//This structure to be DMA to SMBUS Config register space 481typedef struct { 482 uint8_t MinorInfoVersion; 483 uint8_t MajorInfoVersion; 484 uint8_t TableSize; 485 uint8_t Reserved; 486 487 uint8_t Reserved1; 488 uint8_t RevID; 489 uint16_t DeviceID; 490 491 uint16_t DieTemperatureLimit; 492 uint16_t FanTargetTemperature; 493 494 uint16_t MemoryTemperatureLimit; 495 uint16_t MemoryTemperatureLimit1; 496 497 uint16_t TGP; 498 uint16_t CardPower; 499 500 uint32_t DieTemperatureRegisterOffset; 501 502 uint32_t Reserved2; 503 504 uint32_t Reserved3; 505 506 uint32_t Status; 507 508 uint16_t DieTemperature; 509 uint16_t CurrentMemoryTemperature; 510 511 uint16_t MemoryTemperature; 512 uint8_t MemoryHotspotPosition; 513 uint8_t Reserved4; 514 515 uint32_t BoardLevelEnergyAccumulator; 516} OutOfBandMonitor_t; 517 518#pragma pack(push, 1) 519typedef struct { 520 uint32_t Version; 521 522 // SECTION: Feature Enablement 523 uint32_t FeaturesToRun[2]; 524 525 // SECTION: Infrastructure Limits 526 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; 527 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; 528 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; 529 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; 530 531 uint16_t TdcLimitSoc; // Amps 532 uint16_t TdcLimitSocTau; // Time constant of LPF in ms 533 uint16_t TdcLimitGfx; // Amps 534 uint16_t TdcLimitGfxTau; // Time constant of LPF in ms 535 536 uint16_t TedgeLimit; // Celcius 537 uint16_t ThotspotLimit; // Celcius 538 uint16_t TmemLimit; // Celcius 539 uint16_t Tvr_gfxLimit; // Celcius 540 uint16_t Tvr_mem0Limit; // Celcius 541 uint16_t Tvr_mem1Limit; // Celcius 542 uint16_t Tvr_socLimit; // Celcius 543 uint16_t Tliquid0Limit; // Celcius 544 uint16_t Tliquid1Limit; // Celcius 545 uint16_t TplxLimit; // Celcius 546 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 547 548 uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold 549 uint16_t PpmTemperatureThreshold; 550 551 // SECTION: Throttler settings 552 uint32_t ThrottlerControlMask; // See Throtter masks defines 553 554 // SECTION: FW DSTATE Settings 555 uint32_t FwDStateMask; // See FW DState masks defines 556 557 // SECTION: ULV Settings 558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 560 561 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls delay for GFX SDP port disconnection during idle events 562 uint8_t paddingRlcUlvParams[3]; 563 564 uint8_t UlvSmnclkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. 565 uint8_t UlvMp1clkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. 566 uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV 567 uint8_t Padding234; 568 569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 571 572 573 // SECTION: Voltage Control Parameters 574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 577 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 578 579 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 580 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 581 582 //SECTION: DPM Config 1 583 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 584 585 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 586 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 587 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 588 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 589 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 590 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 591 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 592 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 593 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 594 uint32_t Paddingclks[16]; 595 596 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 597 uint16_t Padding8_Clks; 598 599 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 600 601 // SECTION: DPM Config 2 602 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 603 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 604 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 605 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 606 // GFXCLK DPM 607 uint16_t GfxclkFgfxoffEntry; // in Mhz 608 uint16_t GfxclkFinit; // in Mhz 609 uint16_t GfxclkFidle; // in MHz 610 uint16_t GfxclkSlewRate; // for PLL babystepping??? 611 uint16_t GfxclkFopt; // in Mhz 612 uint8_t Padding567[2]; 613 uint16_t GfxclkDsMaxFreq; // in MHz 614 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 615 uint8_t Padding456; 616 617 // UCLK section 618 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 619 uint8_t paddingUclk[3]; 620 621 uint8_t MemoryType; // 0-GDDR6, 1-HBM 622 uint8_t MemoryChannels; 623 uint8_t PaddingMem[2]; 624 625 // Link DPM Settings 626 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 627 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 628 uint16_t LclkFreq[NUM_LINK_LEVELS]; 629 630 // GFXCLK Thermal DPM (formerly 'Boost' Settings) 631 uint16_t EnableTdpm; 632 uint16_t TdpmHighHystTemperature; 633 uint16_t TdpmLowHystTemperature; 634 uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. 635 636 // SECTION: Fan Control 637 uint16_t FanStopTemp; //Celcius 638 uint16_t FanStartTemp; //Celcius 639 640 uint16_t FanGainEdge; 641 uint16_t FanGainHotspot; 642 uint16_t FanGainLiquid0; 643 uint16_t FanGainLiquid1; 644 uint16_t FanGainVrGfx; 645 uint16_t FanGainVrSoc; 646 uint16_t FanGainVrMem0; 647 uint16_t FanGainVrMem1; 648 uint16_t FanGainPlx; 649 uint16_t FanGainMem; 650 uint16_t FanPwmMin; 651 uint16_t FanAcousticLimitRpm; 652 uint16_t FanThrottlingRpm; 653 uint16_t FanMaximumRpm; 654 uint16_t FanTargetTemperature; 655 uint16_t FanTargetGfxclk; 656 uint8_t FanTempInputSelect; 657 uint8_t FanPadding; 658 uint8_t FanZeroRpmEnable; 659 uint8_t FanTachEdgePerRev; 660 //uint8_t padding8_Fan[2]; 661 662 // The following are AFC override parameters. Leave at 0 to use FW defaults. 663 int16_t FuzzyFan_ErrorSetDelta; 664 int16_t FuzzyFan_ErrorRateSetDelta; 665 int16_t FuzzyFan_PwmSetDelta; 666 uint16_t FuzzyFan_Reserved; 667 668 669 // SECTION: AVFS 670 // Overrides 671 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 672 uint8_t Padding8_Avfs[2]; 673 674 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 675 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 676 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 677 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 678 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 679 680 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 681 682 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 683 684 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 685 uint8_t Padding8_GfxBtc[2]; 686 687 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 688 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 689 690 // SECTION: Advanced Options 691 uint32_t DebugOverrides; 692 QuadraticInt_t ReservedEquation0; 693 QuadraticInt_t ReservedEquation1; 694 QuadraticInt_t ReservedEquation2; 695 QuadraticInt_t ReservedEquation3; 696 697 // Total Power configuration, use defines from PwrConfig_e 698 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured 699 uint8_t TotalPowerSpare1; 700 uint16_t TotalPowerSpare2; 701 702 // APCC Settings 703 uint16_t PccThresholdLow; 704 uint16_t PccThresholdHigh; 705 uint32_t MGpuFanBoostLimitRpm; 706 uint32_t PaddingAPCC[5]; 707 708 // Temperature Dependent Vmin 709 uint16_t VDDGFX_TVmin; //Celcius 710 uint16_t VDDSOC_TVmin; //Celcius 711 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 712 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 713 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 714 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 715 716 uint16_t VDDGFX_TVminHystersis; // Celcius 717 uint16_t VDDSOC_TVminHystersis; // Celcius 718 719 // BTC Setting 720 uint32_t BtcConfig; 721 722 uint16_t SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2 723 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; 724 725 // SECTION: Board Reserved 726 uint32_t Reserved[8]; 727 728 // SECTION: BOARD PARAMETERS 729 // I2C Control 730 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 731 732 // SVI2 Board Parameters 733 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 734 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 735 736 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 737 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 738 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 739 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 740 741 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 742 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 743 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 744 uint8_t Padding8_V; 745 746 // Telemetry Settings 747 uint16_t GfxMaxCurrent; // in Amps 748 int8_t GfxOffset; // in Amps 749 uint8_t Padding_TelemetryGfx; 750 751 uint16_t SocMaxCurrent; // in Amps 752 int8_t SocOffset; // in Amps 753 uint8_t Padding_TelemetrySoc; 754 755 uint16_t Mem0MaxCurrent; // in Amps 756 int8_t Mem0Offset; // in Amps 757 uint8_t Padding_TelemetryMem0; 758 759 uint16_t Mem1MaxCurrent; // in Amps 760 int8_t Mem1Offset; // in Amps 761 uint8_t Padding_TelemetryMem1; 762 763 // GPIO Settings 764 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 765 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 766 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 767 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 768 769 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 770 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 771 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 772 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 773 774 // LED Display Settings 775 uint8_t LedPin0; // GPIO number for LedPin[0] 776 uint8_t LedPin1; // GPIO number for LedPin[1] 777 uint8_t LedPin2; // GPIO number for LedPin[2] 778 uint8_t padding8_4; 779 780 // GFXCLK PLL Spread Spectrum 781 uint8_t PllGfxclkSpreadEnabled; // on or off 782 uint8_t PllGfxclkSpreadPercent; // Q4.4 783 uint16_t PllGfxclkSpreadFreq; // kHz 784 785 // GFXCLK DFLL Spread Spectrum 786 uint8_t DfllGfxclkSpreadEnabled; // on or off 787 uint8_t DfllGfxclkSpreadPercent; // Q4.4 788 uint16_t DfllGfxclkSpreadFreq; // kHz 789 790 // UCLK Spread Spectrum 791 uint8_t UclkSpreadEnabled; // on or off 792 uint8_t UclkSpreadPercent; // Q4.4 793 uint16_t UclkSpreadFreq; // kHz 794 795 // SOCCLK Spread Spectrum 796 uint8_t SoclkSpreadEnabled; // on or off 797 uint8_t SocclkSpreadPercent; // Q4.4 798 uint16_t SocclkSpreadFreq; // kHz 799 800 // Total board power 801 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 802 uint16_t BoardPadding; 803 804 // Mvdd Svi2 Div Ratio Setting 805 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 806 807 uint8_t RenesesLoadLineEnabled; 808 uint8_t GfxLoadlineResistance; 809 uint8_t SocLoadlineResistance; 810 uint8_t Padding8_Loadline; 811 812 uint32_t BoardReserved[8]; 813 814 // Padding for MMHUB - do not modify this 815 uint32_t MmHubPadding[8]; // SMU internal use 816 817} PPTable_t; 818#pragma pack(pop) 819 820typedef struct { 821 // Time constant parameters for clock averages in ms 822 uint16_t GfxclkAverageLpfTau; 823 uint16_t SocclkAverageLpfTau; 824 uint16_t UclkAverageLpfTau; 825 uint16_t GfxActivityLpfTau; 826 uint16_t UclkActivityLpfTau; 827 uint16_t SocketPowerLpfTau; 828 829 // Padding - ignore 830 uint32_t MmHubPadding[8]; // SMU internal use 831} DriverSmuConfig_t; 832 833typedef struct { 834 835 uint16_t GfxclkFmin; // MHz 836 uint16_t GfxclkFmax; // MHz 837 uint16_t GfxclkFreq1; // MHz 838 uint16_t GfxclkVolt1; // mV (Q2) 839 uint16_t GfxclkFreq2; // MHz 840 uint16_t GfxclkVolt2; // mV (Q2) 841 uint16_t GfxclkFreq3; // MHz 842 uint16_t GfxclkVolt3; // mV (Q2) 843 uint16_t UclkFmax; // MHz 844 int16_t OverDrivePct; // % 845 uint16_t FanMaximumRpm; 846 uint16_t FanMinimumPwm; 847 uint16_t FanTargetTemperature; // Degree Celcius 848 uint16_t FanMode; 849 uint16_t FanMaxPwm; 850 uint16_t FanMinPwm; 851 uint16_t FanMaxTemp; // Degree Celcius 852 uint16_t FanMinTemp; // Degree Celcius 853 uint16_t MaxOpTemp; // Degree Celcius 854 uint16_t FanZeroRpmEnable; 855 856 uint32_t MmHubPadding[6]; // SMU internal use 857 858} OverDriveTable_t; 859 860typedef struct { 861 uint16_t CurrClock[PPCLK_COUNT]; 862 uint16_t AverageGfxclkFrequency; 863 uint16_t AverageSocclkFrequency; 864 uint16_t AverageUclkFrequency ; 865 uint16_t AverageGfxActivity ; 866 uint16_t AverageUclkActivity ; 867 uint8_t CurrSocVoltageOffset ; 868 uint8_t CurrGfxVoltageOffset ; 869 uint8_t CurrMemVidOffset ; 870 uint8_t Padding8 ; 871 uint16_t AverageSocketPower ; 872 uint16_t TemperatureEdge ; 873 uint16_t TemperatureHotspot ; 874 uint16_t TemperatureMem ; 875 uint16_t TemperatureVrGfx ; 876 uint16_t TemperatureVrMem0 ; 877 uint16_t TemperatureVrMem1 ; 878 uint16_t TemperatureVrSoc ; 879 uint16_t TemperatureLiquid0 ; 880 uint16_t TemperatureLiquid1 ; 881 uint16_t TemperaturePlx ; 882 uint16_t Padding16 ; 883 uint32_t ThrottlerStatus ; 884 885 uint8_t LinkDpmLevel; 886 uint8_t Padding8_2; 887 uint16_t CurrFanSpeed; 888 889 // Padding - ignore 890 uint32_t MmHubPadding[8]; // SMU internal use 891} SmuMetrics_legacy_t; 892 893typedef struct { 894 uint16_t CurrClock[PPCLK_COUNT]; 895 uint16_t AverageGfxclkFrequencyPostDs; 896 uint16_t AverageSocclkFrequency; 897 uint16_t AverageUclkFrequencyPostDs; 898 uint16_t AverageGfxActivity ; 899 uint16_t AverageUclkActivity ; 900 uint8_t CurrSocVoltageOffset ; 901 uint8_t CurrGfxVoltageOffset ; 902 uint8_t CurrMemVidOffset ; 903 uint8_t Padding8 ; 904 uint16_t AverageSocketPower ; 905 uint16_t TemperatureEdge ; 906 uint16_t TemperatureHotspot ; 907 uint16_t TemperatureMem ; 908 uint16_t TemperatureVrGfx ; 909 uint16_t TemperatureVrMem0 ; 910 uint16_t TemperatureVrMem1 ; 911 uint16_t TemperatureVrSoc ; 912 uint16_t TemperatureLiquid0 ; 913 uint16_t TemperatureLiquid1 ; 914 uint16_t TemperaturePlx ; 915 uint16_t Padding16 ; 916 uint32_t ThrottlerStatus ; 917 918 uint8_t LinkDpmLevel; 919 uint8_t Padding8_2; 920 uint16_t CurrFanSpeed; 921 922 uint16_t AverageGfxclkFrequencyPreDs; 923 uint16_t AverageUclkFrequencyPreDs; 924 uint8_t PcieRate; 925 uint8_t PcieWidth; 926 uint8_t Padding8_3[2]; 927 928 // Padding - ignore 929 uint32_t MmHubPadding[8]; // SMU internal use 930} SmuMetrics_t; 931 932typedef struct { 933 uint16_t CurrClock[PPCLK_COUNT]; 934 uint16_t AverageGfxclkFrequency; 935 uint16_t AverageSocclkFrequency; 936 uint16_t AverageUclkFrequency ; 937 uint16_t AverageGfxActivity ; 938 uint16_t AverageUclkActivity ; 939 uint8_t CurrSocVoltageOffset ; 940 uint8_t CurrGfxVoltageOffset ; 941 uint8_t CurrMemVidOffset ; 942 uint8_t Padding8 ; 943 uint16_t AverageSocketPower ; 944 uint16_t TemperatureEdge ; 945 uint16_t TemperatureHotspot ; 946 uint16_t TemperatureMem ; 947 uint16_t TemperatureVrGfx ; 948 uint16_t TemperatureVrMem0 ; 949 uint16_t TemperatureVrMem1 ; 950 uint16_t TemperatureVrSoc ; 951 uint16_t TemperatureLiquid0 ; 952 uint16_t TemperatureLiquid1 ; 953 uint16_t TemperaturePlx ; 954 uint16_t Padding16 ; 955 uint32_t ThrottlerStatus ; 956 957 uint8_t LinkDpmLevel; 958 uint8_t Padding8_2; 959 uint16_t CurrFanSpeed; 960 961 uint32_t EnergyAccumulator; 962 uint16_t AverageVclkFrequency ; 963 uint16_t AverageDclkFrequency ; 964 uint16_t VcnActivityPercentage ; 965 uint16_t padding16_2; 966 967 // Padding - ignore 968 uint32_t MmHubPadding[8]; // SMU internal use 969} SmuMetrics_NV12_legacy_t; 970 971typedef struct { 972 uint16_t CurrClock[PPCLK_COUNT]; 973 uint16_t AverageGfxclkFrequencyPostDs; 974 uint16_t AverageSocclkFrequency; 975 uint16_t AverageUclkFrequencyPostDs; 976 uint16_t AverageGfxActivity ; 977 uint16_t AverageUclkActivity ; 978 uint8_t CurrSocVoltageOffset ; 979 uint8_t CurrGfxVoltageOffset ; 980 uint8_t CurrMemVidOffset ; 981 uint8_t Padding8 ; 982 uint16_t AverageSocketPower ; 983 uint16_t TemperatureEdge ; 984 uint16_t TemperatureHotspot ; 985 uint16_t TemperatureMem ; 986 uint16_t TemperatureVrGfx ; 987 uint16_t TemperatureVrMem0 ; 988 uint16_t TemperatureVrMem1 ; 989 uint16_t TemperatureVrSoc ; 990 uint16_t TemperatureLiquid0 ; 991 uint16_t TemperatureLiquid1 ; 992 uint16_t TemperaturePlx ; 993 uint16_t Padding16 ; 994 uint32_t ThrottlerStatus ; 995 996 uint8_t LinkDpmLevel; 997 uint8_t Padding8_2; 998 uint16_t CurrFanSpeed; 999 1000 uint16_t AverageVclkFrequency ; 1001 uint16_t AverageDclkFrequency ; 1002 uint16_t VcnActivityPercentage ; 1003 uint16_t AverageGfxclkFrequencyPreDs; 1004 uint16_t AverageUclkFrequencyPreDs; 1005 uint8_t PcieRate; 1006 uint8_t PcieWidth; 1007 1008 uint32_t Padding32_1; 1009 uint64_t EnergyAccumulator; 1010 1011 // Padding - ignore 1012 uint32_t MmHubPadding[8]; // SMU internal use 1013} SmuMetrics_NV12_t; 1014 1015typedef union SmuMetrics { 1016 SmuMetrics_legacy_t nv10_legacy_metrics; 1017 SmuMetrics_t nv10_metrics; 1018 SmuMetrics_NV12_legacy_t nv12_legacy_metrics; 1019 SmuMetrics_NV12_t nv12_metrics; 1020} SmuMetrics_NV1X_t; 1021 1022typedef struct { 1023 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1024 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1025 uint16_t MinUclk; 1026 uint16_t MaxUclk; 1027 1028 uint8_t WmSetting; 1029 uint8_t Padding[3]; 1030 1031 uint32_t MmHubPadding[8]; // SMU internal use 1032} WatermarkRowGeneric_t; 1033 1034#define NUM_WM_RANGES 4 1035 1036typedef enum { 1037 WM_SOCCLK = 0, 1038 WM_DCEFCLK, 1039 WM_COUNT, 1040} WM_CLOCK_e; 1041 1042typedef struct { 1043 // Watermarks 1044 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1045 1046 uint32_t MmHubPadding[8]; // SMU internal use 1047} Watermarks_t; 1048 1049typedef struct { 1050 uint16_t avgPsmCount[28]; 1051 uint16_t minPsmCount[28]; 1052 float avgPsmVoltage[28]; 1053 float minPsmVoltage[28]; 1054 1055 uint32_t MmHubPadding[32]; // SMU internal use 1056} AvfsDebugTable_t_NV14; 1057 1058typedef struct { 1059 uint16_t avgPsmCount[36]; 1060 uint16_t minPsmCount[36]; 1061 float avgPsmVoltage[36]; 1062 float minPsmVoltage[36]; 1063 1064 uint32_t MmHubPadding[8]; // SMU internal use 1065} AvfsDebugTable_t_NV10; 1066 1067typedef struct { 1068 uint8_t AvfsVersion; 1069 uint8_t Padding; 1070 1071 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1072 1073 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1074 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1075 1076 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1077 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1078 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1079 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1080 1081 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1082 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1083 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1084 1085 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1086 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1087 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1088 1089 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1090 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1091 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1092 1093 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1094 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1095 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1096 1097 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1098 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1099 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1100 1101 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1102 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1103 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1104 1105 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1106 1107 1108 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1109 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1110 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1111 1112 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1113 1114 uint32_t EnabledAvfsModules[2]; //NV10 - 36 AVFS modules 1115 1116 uint32_t MmHubPadding[8]; // SMU internal use 1117} AvfsFuseOverride_t; 1118 1119typedef struct { 1120 1121 uint8_t Gfx_ActiveHystLimit; 1122 uint8_t Gfx_IdleHystLimit; 1123 uint8_t Gfx_FPS; 1124 uint8_t Gfx_MinActiveFreqType; 1125 uint8_t Gfx_BoosterFreqType; 1126 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1127 uint16_t Gfx_MinActiveFreq; // MHz 1128 uint16_t Gfx_BoosterFreq; // MHz 1129 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1130 uint32_t Gfx_PD_Data_limit_a; // Q16 1131 uint32_t Gfx_PD_Data_limit_b; // Q16 1132 uint32_t Gfx_PD_Data_limit_c; // Q16 1133 uint32_t Gfx_PD_Data_error_coeff; // Q16 1134 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1135 1136 uint8_t Soc_ActiveHystLimit; 1137 uint8_t Soc_IdleHystLimit; 1138 uint8_t Soc_FPS; 1139 uint8_t Soc_MinActiveFreqType; 1140 uint8_t Soc_BoosterFreqType; 1141 uint8_t Soc_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1142 uint16_t Soc_MinActiveFreq; // MHz 1143 uint16_t Soc_BoosterFreq; // MHz 1144 uint16_t Soc_PD_Data_time_constant; // Time constant of PD controller in ms 1145 uint32_t Soc_PD_Data_limit_a; // Q16 1146 uint32_t Soc_PD_Data_limit_b; // Q16 1147 uint32_t Soc_PD_Data_limit_c; // Q16 1148 uint32_t Soc_PD_Data_error_coeff; // Q16 1149 uint32_t Soc_PD_Data_error_rate_coeff; // Q16 1150 1151 uint8_t Mem_ActiveHystLimit; 1152 uint8_t Mem_IdleHystLimit; 1153 uint8_t Mem_FPS; 1154 uint8_t Mem_MinActiveFreqType; 1155 uint8_t Mem_BoosterFreqType; 1156 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1157 uint16_t Mem_MinActiveFreq; // MHz 1158 uint16_t Mem_BoosterFreq; // MHz 1159 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1160 uint32_t Mem_PD_Data_limit_a; // Q16 1161 uint32_t Mem_PD_Data_limit_b; // Q16 1162 uint32_t Mem_PD_Data_limit_c; // Q16 1163 uint32_t Mem_PD_Data_error_coeff; // Q16 1164 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1165 1166 uint32_t Mem_UpThreshold_Limit; // Q16 1167 uint8_t Mem_UpHystLimit; 1168 uint8_t Mem_DownHystLimit; 1169 uint16_t Mem_Fps; 1170 1171 uint32_t MmHubPadding[8]; // SMU internal use 1172 1173} DpmActivityMonitorCoeffInt_t; 1174 1175 1176// Workload bits 1177#define WORKLOAD_PPLIB_DEFAULT_BIT 0 1178#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1179#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1180#define WORKLOAD_PPLIB_VIDEO_BIT 3 1181#define WORKLOAD_PPLIB_VR_BIT 4 1182#define WORKLOAD_PPLIB_COMPUTE_BIT 5 1183#define WORKLOAD_PPLIB_CUSTOM_BIT 6 1184#define WORKLOAD_PPLIB_COUNT 7 1185 1186 1187// These defines are used with the following messages: 1188// SMC_MSG_TransferTableDram2Smu 1189// SMC_MSG_TransferTableSmu2Dram 1190 1191// Table transfer status 1192#define TABLE_TRANSFER_OK 0x0 1193#define TABLE_TRANSFER_FAILED 0xFF 1194 1195// Table types 1196#define TABLE_PPTABLE 0 1197#define TABLE_WATERMARKS 1 1198#define TABLE_AVFS 2 1199#define TABLE_AVFS_PSM_DEBUG 3 1200#define TABLE_AVFS_FUSE_OVERRIDE 4 1201#define TABLE_PMSTATUSLOG 5 1202#define TABLE_SMU_METRICS 6 1203#define TABLE_DRIVER_SMU_CONFIG 7 1204#define TABLE_ACTIVITY_MONITOR_COEFF 8 1205#define TABLE_OVERDRIVE 9 1206#define TABLE_I2C_COMMANDS 10 1207#define TABLE_PACE 11 1208#define TABLE_COUNT 12 1209 1210//RLC Pace Table total number of levels 1211#define RLC_PACE_TABLE_NUM_LEVELS 16 1212 1213typedef struct { 1214 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1215 1216 uint32_t MmHubPadding[8]; // SMU internal use 1217} RlcPaceFlopsPerByteOverride_t; 1218 1219// These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1220#define UCLK_SWITCH_SLOW 0 1221#define UCLK_SWITCH_FAST 1 1222#endif 1223