1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef VEGA12_SMU9_DRIVER_IF_H
25#define VEGA12_SMU9_DRIVER_IF_H
26
27/**** IMPORTANT ***
28 * SMU TEAM: Always increment the interface version if
29 * any structure is changed in this file
30 */
31#define SMU9_DRIVER_IF_VERSION 0x10
32
33#define PPTABLE_V12_SMU_VERSION 1
34
35#define NUM_GFXCLK_DPM_LEVELS  16
36#define NUM_VCLK_DPM_LEVELS    8
37#define NUM_DCLK_DPM_LEVELS    8
38#define NUM_ECLK_DPM_LEVELS    8
39#define NUM_MP0CLK_DPM_LEVELS  2
40#define NUM_UCLK_DPM_LEVELS    4
41#define NUM_SOCCLK_DPM_LEVELS  8
42#define NUM_DCEFCLK_DPM_LEVELS 8
43#define NUM_DISPCLK_DPM_LEVELS 8
44#define NUM_PIXCLK_DPM_LEVELS  8
45#define NUM_PHYCLK_DPM_LEVELS  8
46#define NUM_LINK_LEVELS        2
47
48#define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
49#define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
50#define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
51#define MAX_ECLK_DPM_LEVEL    (NUM_ECLK_DPM_LEVELS    - 1)
52#define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
53#define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
54#define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
55#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
56#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
57#define MAX_PIXCLK_DPM_LEVEL  (NUM_PIXCLK_DPM_LEVELS  - 1)
58#define MAX_PHYCLK_DPM_LEVEL  (NUM_PHYCLK_DPM_LEVELS  - 1)
59#define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
60
61
62#define PPSMC_GeminiModeNone   0
63#define PPSMC_GeminiModeMaster 1
64#define PPSMC_GeminiModeSlave  2
65
66
67#define FEATURE_DPM_PREFETCHER_BIT      0
68#define FEATURE_DPM_GFXCLK_BIT          1
69#define FEATURE_DPM_UCLK_BIT            2
70#define FEATURE_DPM_SOCCLK_BIT          3
71#define FEATURE_DPM_UVD_BIT             4
72#define FEATURE_DPM_VCE_BIT             5
73#define FEATURE_ULV_BIT                 6
74#define FEATURE_DPM_MP0CLK_BIT          7
75#define FEATURE_DPM_LINK_BIT            8
76#define FEATURE_DPM_DCEFCLK_BIT         9
77#define FEATURE_DS_GFXCLK_BIT           10
78#define FEATURE_DS_SOCCLK_BIT           11
79#define FEATURE_DS_LCLK_BIT             12
80#define FEATURE_PPT_BIT                 13
81#define FEATURE_TDC_BIT                 14
82#define FEATURE_THERMAL_BIT             15
83#define FEATURE_GFX_PER_CU_CG_BIT       16
84#define FEATURE_RM_BIT                  17
85#define FEATURE_DS_DCEFCLK_BIT          18
86#define FEATURE_ACDC_BIT                19
87#define FEATURE_VR0HOT_BIT              20
88#define FEATURE_VR1HOT_BIT              21
89#define FEATURE_FW_CTF_BIT              22
90#define FEATURE_LED_DISPLAY_BIT         23
91#define FEATURE_FAN_CONTROL_BIT         24
92#define FEATURE_GFX_EDC_BIT             25
93#define FEATURE_GFXOFF_BIT              26
94#define FEATURE_CG_BIT                  27
95#define FEATURE_ACG_BIT                 28
96#define FEATURE_SPARE_29_BIT            29
97#define FEATURE_SPARE_30_BIT            30
98#define FEATURE_SPARE_31_BIT            31
99
100#define NUM_FEATURES                    32
101
102#define FEATURE_DPM_PREFETCHER_MASK     (1 << FEATURE_DPM_PREFETCHER_BIT     )
103#define FEATURE_DPM_GFXCLK_MASK         (1 << FEATURE_DPM_GFXCLK_BIT         )
104#define FEATURE_DPM_UCLK_MASK           (1 << FEATURE_DPM_UCLK_BIT           )
105#define FEATURE_DPM_SOCCLK_MASK         (1 << FEATURE_DPM_SOCCLK_BIT         )
106#define FEATURE_DPM_UVD_MASK            (1 << FEATURE_DPM_UVD_BIT            )
107#define FEATURE_DPM_VCE_MASK            (1 << FEATURE_DPM_VCE_BIT            )
108#define FEATURE_ULV_MASK                (1 << FEATURE_ULV_BIT                )
109#define FEATURE_DPM_MP0CLK_MASK         (1 << FEATURE_DPM_MP0CLK_BIT         )
110#define FEATURE_DPM_LINK_MASK           (1 << FEATURE_DPM_LINK_BIT           )
111#define FEATURE_DPM_DCEFCLK_MASK        (1 << FEATURE_DPM_DCEFCLK_BIT        )
112#define FEATURE_DS_GFXCLK_MASK          (1 << FEATURE_DS_GFXCLK_BIT          )
113#define FEATURE_DS_SOCCLK_MASK          (1 << FEATURE_DS_SOCCLK_BIT          )
114#define FEATURE_DS_LCLK_MASK            (1 << FEATURE_DS_LCLK_BIT            )
115#define FEATURE_PPT_MASK                (1 << FEATURE_PPT_BIT                )
116#define FEATURE_TDC_MASK                (1 << FEATURE_TDC_BIT                )
117#define FEATURE_THERMAL_MASK            (1 << FEATURE_THERMAL_BIT            )
118#define FEATURE_GFX_PER_CU_CG_MASK      (1 << FEATURE_GFX_PER_CU_CG_BIT      )
119#define FEATURE_RM_MASK                 (1 << FEATURE_RM_BIT                 )
120#define FEATURE_DS_DCEFCLK_MASK         (1 << FEATURE_DS_DCEFCLK_BIT         )
121#define FEATURE_ACDC_MASK               (1 << FEATURE_ACDC_BIT               )
122#define FEATURE_VR0HOT_MASK             (1 << FEATURE_VR0HOT_BIT             )
123#define FEATURE_VR1HOT_MASK             (1 << FEATURE_VR1HOT_BIT             )
124#define FEATURE_FW_CTF_MASK             (1 << FEATURE_FW_CTF_BIT             )
125#define FEATURE_LED_DISPLAY_MASK        (1 << FEATURE_LED_DISPLAY_BIT        )
126#define FEATURE_FAN_CONTROL_MASK        (1 << FEATURE_FAN_CONTROL_BIT        )
127#define FEATURE_GFX_EDC_MASK            (1 << FEATURE_GFX_EDC_BIT            )
128#define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
129#define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
130#define FEATURE_ACG_MASK          (1 << FEATURE_ACG_BIT)
131#define FEATURE_SPARE_29_MASK           (1 << FEATURE_SPARE_29_BIT           )
132#define FEATURE_SPARE_30_MASK           (1 << FEATURE_SPARE_30_BIT           )
133#define FEATURE_SPARE_31_MASK           (1 << FEATURE_SPARE_31_BIT           )
134
135
136#define DPM_OVERRIDE_DISABLE_SOCCLK_PID             0x00000001
137#define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000002
138#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK    0x00000004
139#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK      0x00000008
140#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK   0x00000010
141#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK     0x00000020
142#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK   0x00000040
143#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK     0x00000080
144#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK    0x00000100
145#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK      0x00000200
146#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK   0x00000400
147#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK     0x00000800
148#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
149#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK   0x00002000
150#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH    0x00004000
151#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH    0x00008000
152#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH      0x00010000
153
154
155#define VR_MAPPING_VR_SELECT_MASK  0x01
156#define VR_MAPPING_VR_SELECT_SHIFT 0x00
157
158#define VR_MAPPING_PLANE_SELECT_MASK  0x02
159#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
160
161
162#define PSI_SEL_VR0_PLANE0_PSI0  0x01
163#define PSI_SEL_VR0_PLANE0_PSI1  0x02
164#define PSI_SEL_VR0_PLANE1_PSI0  0x04
165#define PSI_SEL_VR0_PLANE1_PSI1  0x08
166#define PSI_SEL_VR1_PLANE0_PSI0  0x10
167#define PSI_SEL_VR1_PLANE0_PSI1  0x20
168#define PSI_SEL_VR1_PLANE1_PSI0  0x40
169#define PSI_SEL_VR1_PLANE1_PSI1  0x80
170
171
172#define THROTTLER_STATUS_PADDING_BIT      0
173#define THROTTLER_STATUS_TEMP_EDGE_BIT    1
174#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
175#define THROTTLER_STATUS_TEMP_HBM_BIT     3
176#define THROTTLER_STATUS_TEMP_VR_GFX_BIT  4
177#define THROTTLER_STATUS_TEMP_VR_MEM_BIT  5
178#define THROTTLER_STATUS_TEMP_LIQUID_BIT  6
179#define THROTTLER_STATUS_TEMP_PLX_BIT     7
180#define THROTTLER_STATUS_TEMP_SKIN_BIT    8
181#define THROTTLER_STATUS_TDC_GFX_BIT      9
182#define THROTTLER_STATUS_TDC_SOC_BIT      10
183#define THROTTLER_STATUS_PPT_BIT          11
184#define THROTTLER_STATUS_FIT_BIT          12
185#define THROTTLER_STATUS_PPM_BIT          13
186
187
188#define TABLE_TRANSFER_OK         0x0
189#define TABLE_TRANSFER_FAILED     0xFF
190
191
192#define WORKLOAD_DEFAULT_BIT              0
193#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
194#define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
195#define WORKLOAD_PPLIB_VIDEO_BIT          3
196#define WORKLOAD_PPLIB_VR_BIT             4
197#define WORKLOAD_PPLIB_COMPUTE_BIT        5
198#define WORKLOAD_PPLIB_CUSTOM_BIT         6
199#define WORKLOAD_PPLIB_COUNT              7
200
201typedef struct {
202  uint32_t a;
203  uint32_t b;
204  uint32_t c;
205} QuadraticInt_t;
206
207typedef struct {
208  uint32_t m;
209  uint32_t b;
210} LinearInt_t;
211
212typedef struct {
213  uint32_t a;
214  uint32_t b;
215  uint32_t c;
216} DroopInt_t;
217
218typedef enum {
219  PPCLK_GFXCLK,
220  PPCLK_VCLK,
221  PPCLK_DCLK,
222  PPCLK_ECLK,
223  PPCLK_SOCCLK,
224  PPCLK_UCLK,
225  PPCLK_DCEFCLK,
226  PPCLK_DISPCLK,
227  PPCLK_PIXCLK,
228  PPCLK_PHYCLK,
229  PPCLK_COUNT,
230} PPCLK_e;
231
232enum {
233  VOLTAGE_MODE_AVFS,
234  VOLTAGE_MODE_AVFS_SS,
235  VOLTAGE_MODE_SS,
236  VOLTAGE_MODE_COUNT,
237};
238
239typedef struct {
240  uint8_t        VoltageMode;
241  uint8_t        SnapToDiscrete;
242  uint8_t        NumDiscreteLevels;
243  uint8_t        padding;
244  LinearInt_t    ConversionToAvfsClk;
245  QuadraticInt_t SsCurve;
246} DpmDescriptor_t;
247
248#pragma pack(push, 1)
249typedef struct {
250  uint32_t Version;
251
252
253  uint32_t FeaturesToRun[2];
254
255
256  uint16_t SocketPowerLimitAc0;
257  uint16_t SocketPowerLimitAc0Tau;
258  uint16_t SocketPowerLimitAc1;
259  uint16_t SocketPowerLimitAc1Tau;
260  uint16_t SocketPowerLimitAc2;
261  uint16_t SocketPowerLimitAc2Tau;
262  uint16_t SocketPowerLimitAc3;
263  uint16_t SocketPowerLimitAc3Tau;
264  uint16_t SocketPowerLimitDc;
265  uint16_t SocketPowerLimitDcTau;
266  uint16_t TdcLimitSoc;
267  uint16_t TdcLimitSocTau;
268  uint16_t TdcLimitGfx;
269  uint16_t TdcLimitGfxTau;
270
271  uint16_t TedgeLimit;
272  uint16_t ThotspotLimit;
273  uint16_t ThbmLimit;
274  uint16_t Tvr_gfxLimit;
275  uint16_t Tvr_memLimit;
276  uint16_t Tliquid1Limit;
277  uint16_t Tliquid2Limit;
278  uint16_t TplxLimit;
279  uint32_t FitLimit;
280
281  uint16_t PpmPowerLimit;
282  uint16_t PpmTemperatureThreshold;
283
284  uint8_t  MemoryOnPackage;
285  uint8_t  padding8_limits[3];
286
287
288  uint16_t  UlvVoltageOffsetSoc;
289  uint16_t  UlvVoltageOffsetGfx;
290
291  uint8_t  UlvSmnclkDid;
292  uint8_t  UlvMp1clkDid;
293  uint8_t  UlvGfxclkBypass;
294  uint8_t  Padding234;
295
296
297  uint16_t     MinVoltageGfx;
298  uint16_t     MinVoltageSoc;
299  uint16_t     MaxVoltageGfx;
300  uint16_t     MaxVoltageSoc;
301
302  uint16_t     LoadLineResistance;
303  uint16_t     LoadLine_padding;
304
305
306  DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
307
308  uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];
309  uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];
310  uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];
311  uint16_t       FreqTableEclk     [NUM_ECLK_DPM_LEVELS    ];
312  uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];
313  uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];
314  uint16_t       FreqTableDcefclk  [NUM_DCEFCLK_DPM_LEVELS ];
315  uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];
316  uint16_t       FreqTablePixclk   [NUM_PIXCLK_DPM_LEVELS  ];
317  uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];
318
319  uint16_t       DcModeMaxFreq     [PPCLK_COUNT            ];
320
321
322  uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];
323  uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];
324
325
326  uint16_t        GfxclkFidle;
327  uint16_t        GfxclkSlewRate;
328  uint16_t        CksEnableFreq;
329  uint16_t        Padding789;
330  QuadraticInt_t  CksVoltageOffset;
331  uint16_t        AcgThresholdFreqHigh;
332  uint16_t        AcgThresholdFreqLow;
333  uint16_t        GfxclkDsMaxFreq;
334  uint8_t         Padding456[2];
335
336
337  uint8_t      LowestUclkReservedForUlv;
338  uint8_t      Padding8_Uclk[3];
339
340
341  uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
342  uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
343  uint16_t     LclkFreq[NUM_LINK_LEVELS];
344
345
346  uint16_t     EnableTdpm;
347  uint16_t     TdpmHighHystTemperature;
348  uint16_t     TdpmLowHystTemperature;
349  uint16_t     GfxclkFreqHighTempLimit;
350
351
352  uint16_t     FanStopTemp;
353  uint16_t     FanStartTemp;
354
355  uint16_t     FanGainEdge;
356  uint16_t     FanGainHotspot;
357  uint16_t     FanGainLiquid;
358  uint16_t     FanGainVrVddc;
359  uint16_t     FanGainVrMvdd;
360  uint16_t     FanGainPlx;
361  uint16_t     FanGainHbm;
362  uint16_t     FanPwmMin;
363  uint16_t     FanAcousticLimitRpm;
364  uint16_t     FanThrottlingRpm;
365  uint16_t     FanMaximumRpm;
366  uint16_t     FanTargetTemperature;
367  uint16_t     FanTargetGfxclk;
368  uint8_t      FanZeroRpmEnable;
369  uint8_t      FanTachEdgePerRev;
370
371
372
373  int16_t      FuzzyFan_ErrorSetDelta;
374  int16_t      FuzzyFan_ErrorRateSetDelta;
375  int16_t      FuzzyFan_PwmSetDelta;
376  uint16_t     FuzzyFan_Reserved;
377
378
379
380
381  uint8_t           OverrideAvfsGb;
382  uint8_t           Padding8_Avfs[3];
383
384  QuadraticInt_t    qAvfsGb;
385  DroopInt_t        dBtcGbGfxCksOn;
386  DroopInt_t        dBtcGbGfxCksOff;
387  DroopInt_t        dBtcGbGfxAcg;
388  DroopInt_t        dBtcGbSoc;
389  LinearInt_t       qAgingGbGfx;
390  LinearInt_t       qAgingGbSoc;
391
392  QuadraticInt_t    qStaticVoltageOffsetGfx;
393  QuadraticInt_t    qStaticVoltageOffsetSoc;
394
395  uint16_t          DcTolGfx;
396  uint16_t          DcTolSoc;
397
398  uint8_t           DcBtcGfxEnabled;
399  uint8_t           DcBtcSocEnabled;
400  uint8_t           Padding8_GfxBtc[2];
401
402  uint16_t          DcBtcGfxMin;
403  uint16_t          DcBtcGfxMax;
404
405  uint16_t          DcBtcSocMin;
406  uint16_t          DcBtcSocMax;
407
408
409
410  uint32_t          DebugOverrides;
411  QuadraticInt_t    ReservedEquation0;
412  QuadraticInt_t    ReservedEquation1;
413  QuadraticInt_t    ReservedEquation2;
414  QuadraticInt_t    ReservedEquation3;
415
416  uint16_t     MinVoltageUlvGfx;
417  uint16_t     MinVoltageUlvSoc;
418
419  uint32_t     Reserved[14];
420
421
422
423  uint8_t      Liquid1_I2C_address;
424  uint8_t      Liquid2_I2C_address;
425  uint8_t      Vr_I2C_address;
426  uint8_t      Plx_I2C_address;
427
428  uint8_t      Liquid_I2C_LineSCL;
429  uint8_t      Liquid_I2C_LineSDA;
430  uint8_t      Vr_I2C_LineSCL;
431  uint8_t      Vr_I2C_LineSDA;
432
433  uint8_t      Plx_I2C_LineSCL;
434  uint8_t      Plx_I2C_LineSDA;
435  uint8_t      VrSensorPresent;
436  uint8_t      LiquidSensorPresent;
437
438  uint16_t     MaxVoltageStepGfx;
439  uint16_t     MaxVoltageStepSoc;
440
441  uint8_t      VddGfxVrMapping;
442  uint8_t      VddSocVrMapping;
443  uint8_t      VddMem0VrMapping;
444  uint8_t      VddMem1VrMapping;
445
446  uint8_t      GfxUlvPhaseSheddingMask;
447  uint8_t      SocUlvPhaseSheddingMask;
448  uint8_t      ExternalSensorPresent;
449  uint8_t      Padding8_V;
450
451
452  uint16_t     GfxMaxCurrent;
453  int8_t       GfxOffset;
454  uint8_t      Padding_TelemetryGfx;
455
456  uint16_t     SocMaxCurrent;
457  int8_t       SocOffset;
458  uint8_t      Padding_TelemetrySoc;
459
460  uint16_t     Mem0MaxCurrent;
461  int8_t       Mem0Offset;
462  uint8_t      Padding_TelemetryMem0;
463
464  uint16_t     Mem1MaxCurrent;
465  int8_t       Mem1Offset;
466  uint8_t      Padding_TelemetryMem1;
467
468
469  uint8_t      AcDcGpio;
470  uint8_t      AcDcPolarity;
471  uint8_t      VR0HotGpio;
472  uint8_t      VR0HotPolarity;
473
474  uint8_t      VR1HotGpio;
475  uint8_t      VR1HotPolarity;
476  uint8_t      Padding1;
477  uint8_t      Padding2;
478
479
480
481  uint8_t      LedPin0;
482  uint8_t      LedPin1;
483  uint8_t      LedPin2;
484  uint8_t      padding8_4;
485
486
487  uint8_t      PllGfxclkSpreadEnabled;
488  uint8_t      PllGfxclkSpreadPercent;
489  uint16_t     PllGfxclkSpreadFreq;
490
491  uint8_t      UclkSpreadEnabled;
492  uint8_t      UclkSpreadPercent;
493  uint16_t     UclkSpreadFreq;
494
495  uint8_t      SocclkSpreadEnabled;
496  uint8_t      SocclkSpreadPercent;
497  uint16_t     SocclkSpreadFreq;
498
499  uint8_t      AcgGfxclkSpreadEnabled;
500  uint8_t      AcgGfxclkSpreadPercent;
501  uint16_t     AcgGfxclkSpreadFreq;
502
503  uint8_t      Vr2_I2C_address;
504  uint8_t      padding_vr2[3];
505
506  uint32_t     BoardReserved[9];
507
508
509  uint32_t     MmHubPadding[7];
510
511} PPTable_t;
512#pragma pack(pop)
513
514typedef struct {
515
516  uint16_t     GfxclkAverageLpfTau;
517  uint16_t     SocclkAverageLpfTau;
518  uint16_t     UclkAverageLpfTau;
519  uint16_t     GfxActivityLpfTau;
520  uint16_t     UclkActivityLpfTau;
521
522
523  uint32_t     MmHubPadding[7];
524} DriverSmuConfig_t;
525
526typedef struct {
527
528  uint16_t      GfxclkFmin;
529  uint16_t      GfxclkFmax;
530  uint16_t      GfxclkFreq1;
531  uint16_t      GfxclkOffsetVolt1;
532  uint16_t      GfxclkFreq2;
533  uint16_t      GfxclkOffsetVolt2;
534  uint16_t      GfxclkFreq3;
535  uint16_t      GfxclkOffsetVolt3;
536  uint16_t      UclkFmax;
537  int16_t       OverDrivePct;
538  uint16_t      FanMaximumRpm;
539  uint16_t      FanMinimumPwm;
540  uint16_t      FanTargetTemperature;
541  uint16_t      MaxOpTemp;
542
543} OverDriveTable_t;
544
545typedef struct {
546  uint16_t CurrClock[PPCLK_COUNT];
547  uint16_t AverageGfxclkFrequency;
548  uint16_t AverageSocclkFrequency;
549  uint16_t AverageUclkFrequency  ;
550  uint16_t AverageGfxActivity    ;
551  uint16_t AverageUclkActivity   ;
552  uint8_t  CurrSocVoltageOffset  ;
553  uint8_t  CurrGfxVoltageOffset  ;
554  uint8_t  CurrMemVidOffset      ;
555  uint8_t  Padding8              ;
556  uint16_t CurrSocketPower       ;
557  uint16_t TemperatureEdge       ;
558  uint16_t TemperatureHotspot    ;
559  uint16_t TemperatureHBM        ;
560  uint16_t TemperatureVrGfx      ;
561  uint16_t TemperatureVrMem      ;
562  uint16_t TemperatureLiquid     ;
563  uint16_t TemperaturePlx        ;
564  uint32_t ThrottlerStatus       ;
565
566  uint8_t  LinkDpmLevel;
567  uint8_t  Padding[3];
568
569
570  uint32_t     MmHubPadding[7];
571} SmuMetrics_t;
572
573typedef struct {
574  uint16_t MinClock;
575  uint16_t MaxClock;
576  uint16_t MinUclk;
577  uint16_t MaxUclk;
578
579  uint8_t  WmSetting;
580  uint8_t  Padding[3];
581} WatermarkRowGeneric_t;
582
583#define NUM_WM_RANGES 4
584
585typedef enum {
586  WM_SOCCLK = 0,
587  WM_DCEFCLK,
588  WM_COUNT_PP,
589} WM_CLOCK_e;
590
591typedef struct {
592
593  WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
594
595  uint32_t     MmHubPadding[7];
596} Watermarks_t;
597
598typedef struct {
599  uint16_t avgPsmCount[30];
600  uint16_t minPsmCount[30];
601  float    avgPsmVoltage[30];
602  float    minPsmVoltage[30];
603
604  uint32_t MmHubPadding[7];
605} AvfsDebugTable_t;
606
607typedef struct {
608  uint8_t  AvfsEn;
609  uint8_t  AvfsVersion;
610  uint8_t  OverrideVFT;
611  uint8_t  OverrideAvfsGb;
612
613  uint8_t  OverrideTemperatures;
614  uint8_t  OverrideVInversion;
615  uint8_t  OverrideP2V;
616  uint8_t  OverrideP2VCharzFreq;
617
618  int32_t VFT0_m1;
619  int32_t VFT0_m2;
620  int32_t VFT0_b;
621
622  int32_t VFT1_m1;
623  int32_t VFT1_m2;
624  int32_t VFT1_b;
625
626  int32_t VFT2_m1;
627  int32_t VFT2_m2;
628  int32_t VFT2_b;
629
630  int32_t AvfsGb0_m1;
631  int32_t AvfsGb0_m2;
632  int32_t AvfsGb0_b;
633
634  int32_t AcBtcGb_m1;
635  int32_t AcBtcGb_m2;
636  int32_t AcBtcGb_b;
637
638  uint32_t AvfsTempCold;
639  uint32_t AvfsTempMid;
640  uint32_t AvfsTempHot;
641
642  uint32_t GfxVInversion;
643  uint32_t SocVInversion;
644
645  int32_t P2V_m1;
646  int32_t P2V_m2;
647  int32_t P2V_b;
648
649  uint32_t P2VCharzFreq;
650
651  uint32_t EnabledAvfsModules;
652
653  uint32_t MmHubPadding[7];
654} AvfsFuseOverride_t;
655
656typedef struct {
657
658  uint8_t   Gfx_ActiveHystLimit;
659  uint8_t   Gfx_IdleHystLimit;
660  uint8_t   Gfx_FPS;
661  uint8_t   Gfx_MinActiveFreqType;
662  uint8_t   Gfx_BoosterFreqType;
663  uint8_t   Gfx_UseRlcBusy;
664  uint16_t  Gfx_MinActiveFreq;
665  uint16_t  Gfx_BoosterFreq;
666  uint16_t  Gfx_PD_Data_time_constant;
667  uint32_t  Gfx_PD_Data_limit_a;
668  uint32_t  Gfx_PD_Data_limit_b;
669  uint32_t  Gfx_PD_Data_limit_c;
670  uint32_t  Gfx_PD_Data_error_coeff;
671  uint32_t  Gfx_PD_Data_error_rate_coeff;
672
673  uint8_t   Soc_ActiveHystLimit;
674  uint8_t   Soc_IdleHystLimit;
675  uint8_t   Soc_FPS;
676  uint8_t   Soc_MinActiveFreqType;
677  uint8_t   Soc_BoosterFreqType;
678  uint8_t   Soc_UseRlcBusy;
679  uint16_t  Soc_MinActiveFreq;
680  uint16_t  Soc_BoosterFreq;
681  uint16_t  Soc_PD_Data_time_constant;
682  uint32_t  Soc_PD_Data_limit_a;
683  uint32_t  Soc_PD_Data_limit_b;
684  uint32_t  Soc_PD_Data_limit_c;
685  uint32_t  Soc_PD_Data_error_coeff;
686  uint32_t  Soc_PD_Data_error_rate_coeff;
687
688  uint8_t   Mem_ActiveHystLimit;
689  uint8_t   Mem_IdleHystLimit;
690  uint8_t   Mem_FPS;
691  uint8_t   Mem_MinActiveFreqType;
692  uint8_t   Mem_BoosterFreqType;
693  uint8_t   Mem_UseRlcBusy;
694  uint16_t  Mem_MinActiveFreq;
695  uint16_t  Mem_BoosterFreq;
696  uint16_t  Mem_PD_Data_time_constant;
697  uint32_t  Mem_PD_Data_limit_a;
698  uint32_t  Mem_PD_Data_limit_b;
699  uint32_t  Mem_PD_Data_limit_c;
700  uint32_t  Mem_PD_Data_error_coeff;
701  uint32_t  Mem_PD_Data_error_rate_coeff;
702
703} DpmActivityMonitorCoeffInt_t;
704
705
706
707
708#define TABLE_PPTABLE                 0
709#define TABLE_WATERMARKS              1
710#define TABLE_AVFS                    2
711#define TABLE_AVFS_PSM_DEBUG          3
712#define TABLE_AVFS_FUSE_OVERRIDE      4
713#define TABLE_PMSTATUSLOG             5
714#define TABLE_SMU_METRICS             6
715#define TABLE_DRIVER_SMU_CONFIG       7
716#define TABLE_ACTIVITY_MONITOR_COEFF  8
717#define TABLE_OVERDRIVE               9
718#define TABLE_COUNT                  10
719
720
721#define UCLK_SWITCH_SLOW 0
722#define UCLK_SWITCH_FAST 1
723
724
725#define SQ_Enable_MASK 0x1
726#define SQ_IR_MASK 0x2
727#define SQ_PCC_MASK 0x4
728#define SQ_EDC_MASK 0x8
729
730#define TCP_Enable_MASK 0x100
731#define TCP_IR_MASK 0x200
732#define TCP_PCC_MASK 0x400
733#define TCP_EDC_MASK 0x800
734
735#define TD_Enable_MASK 0x10000
736#define TD_IR_MASK 0x20000
737#define TD_PCC_MASK 0x40000
738#define TD_EDC_MASK 0x80000
739
740#define DB_Enable_MASK 0x1000000
741#define DB_IR_MASK 0x2000000
742#define DB_PCC_MASK 0x4000000
743#define DB_EDC_MASK 0x8000000
744
745#define SQ_Enable_SHIFT 0
746#define SQ_IR_SHIFT 1
747#define SQ_PCC_SHIFT 2
748#define SQ_EDC_SHIFT 3
749
750#define TCP_Enable_SHIFT 8
751#define TCP_IR_SHIFT 9
752#define TCP_PCC_SHIFT 10
753#define TCP_EDC_SHIFT 11
754
755#define TD_Enable_SHIFT 16
756#define TD_IR_SHIFT 17
757#define TD_PCC_SHIFT 18
758#define TD_EDC_SHIFT 19
759
760#define DB_Enable_SHIFT 24
761#define DB_IR_SHIFT 25
762#define DB_PCC_SHIFT 26
763#define DB_EDC_SHIFT 27
764
765#define REMOVE_FMAX_MARGIN_BIT     0x0
766#define REMOVE_DCTOL_MARGIN_BIT    0x1
767#define REMOVE_PLATFORM_MARGIN_BIT 0x2
768
769#endif
770