1/* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _sdma3_4_2_2_OFFSET_HEADER 22#define _sdma3_4_2_2_OFFSET_HEADER 23 24 25 26// addressBlock: sdma3_sdma3dec 27// base address: 0x79000 28#define mmSDMA3_UCODE_ADDR 0x0000 29#define mmSDMA3_UCODE_ADDR_BASE_IDX 1 30#define mmSDMA3_UCODE_DATA 0x0001 31#define mmSDMA3_UCODE_DATA_BASE_IDX 1 32#define mmSDMA3_VM_CNTL 0x0004 33#define mmSDMA3_VM_CNTL_BASE_IDX 1 34#define mmSDMA3_VM_CTX_LO 0x0005 35#define mmSDMA3_VM_CTX_LO_BASE_IDX 1 36#define mmSDMA3_VM_CTX_HI 0x0006 37#define mmSDMA3_VM_CTX_HI_BASE_IDX 1 38#define mmSDMA3_ACTIVE_FCN_ID 0x0007 39#define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1 40#define mmSDMA3_VM_CTX_CNTL 0x0008 41#define mmSDMA3_VM_CTX_CNTL_BASE_IDX 1 42#define mmSDMA3_VIRT_RESET_REQ 0x0009 43#define mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1 44#define mmSDMA3_VF_ENABLE 0x000a 45#define mmSDMA3_VF_ENABLE_BASE_IDX 1 46#define mmSDMA3_CONTEXT_REG_TYPE0 0x000b 47#define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1 48#define mmSDMA3_CONTEXT_REG_TYPE1 0x000c 49#define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX 1 50#define mmSDMA3_CONTEXT_REG_TYPE2 0x000d 51#define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX 1 52#define mmSDMA3_CONTEXT_REG_TYPE3 0x000e 53#define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX 1 54#define mmSDMA3_PUB_REG_TYPE0 0x000f 55#define mmSDMA3_PUB_REG_TYPE0_BASE_IDX 1 56#define mmSDMA3_PUB_REG_TYPE1 0x0010 57#define mmSDMA3_PUB_REG_TYPE1_BASE_IDX 1 58#define mmSDMA3_PUB_REG_TYPE2 0x0011 59#define mmSDMA3_PUB_REG_TYPE2_BASE_IDX 1 60#define mmSDMA3_PUB_REG_TYPE3 0x0012 61#define mmSDMA3_PUB_REG_TYPE3_BASE_IDX 1 62#define mmSDMA3_MMHUB_CNTL 0x0013 63#define mmSDMA3_MMHUB_CNTL_BASE_IDX 1 64#define mmSDMA3_CONTEXT_GROUP_BOUNDARY 0x0019 65#define mmSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 66#define mmSDMA3_POWER_CNTL 0x001a 67#define mmSDMA3_POWER_CNTL_BASE_IDX 1 68#define mmSDMA3_CLK_CTRL 0x001b 69#define mmSDMA3_CLK_CTRL_BASE_IDX 1 70#define mmSDMA3_CNTL 0x001c 71#define mmSDMA3_CNTL_BASE_IDX 1 72#define mmSDMA3_CHICKEN_BITS 0x001d 73#define mmSDMA3_CHICKEN_BITS_BASE_IDX 1 74#define mmSDMA3_GB_ADDR_CONFIG 0x001e 75#define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX 1 76#define mmSDMA3_GB_ADDR_CONFIG_READ 0x001f 77#define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 1 78#define mmSDMA3_RB_RPTR_FETCH_HI 0x0020 79#define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 1 80#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 82#define mmSDMA3_RB_RPTR_FETCH 0x0022 83#define mmSDMA3_RB_RPTR_FETCH_BASE_IDX 1 84#define mmSDMA3_IB_OFFSET_FETCH 0x0023 85#define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX 1 86#define mmSDMA3_PROGRAM 0x0024 87#define mmSDMA3_PROGRAM_BASE_IDX 1 88#define mmSDMA3_STATUS_REG 0x0025 89#define mmSDMA3_STATUS_REG_BASE_IDX 1 90#define mmSDMA3_STATUS1_REG 0x0026 91#define mmSDMA3_STATUS1_REG_BASE_IDX 1 92#define mmSDMA3_RD_BURST_CNTL 0x0027 93#define mmSDMA3_RD_BURST_CNTL_BASE_IDX 1 94#define mmSDMA3_HBM_PAGE_CONFIG 0x0028 95#define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX 1 96#define mmSDMA3_UCODE_CHECKSUM 0x0029 97#define mmSDMA3_UCODE_CHECKSUM_BASE_IDX 1 98#define mmSDMA3_F32_CNTL 0x002a 99#define mmSDMA3_F32_CNTL_BASE_IDX 1 100#define mmSDMA3_FREEZE 0x002b 101#define mmSDMA3_FREEZE_BASE_IDX 1 102#define mmSDMA3_PHASE0_QUANTUM 0x002c 103#define mmSDMA3_PHASE0_QUANTUM_BASE_IDX 1 104#define mmSDMA3_PHASE1_QUANTUM 0x002d 105#define mmSDMA3_PHASE1_QUANTUM_BASE_IDX 1 106#define mmSDMA3_EDC_CONFIG 0x0032 107#define mmSDMA3_EDC_CONFIG_BASE_IDX 1 108#define mmSDMA3_BA_THRESHOLD 0x0033 109#define mmSDMA3_BA_THRESHOLD_BASE_IDX 1 110#define mmSDMA3_ID 0x0034 111#define mmSDMA3_ID_BASE_IDX 1 112#define mmSDMA3_VERSION 0x0035 113#define mmSDMA3_VERSION_BASE_IDX 1 114#define mmSDMA3_EDC_COUNTER 0x0036 115#define mmSDMA3_EDC_COUNTER_BASE_IDX 1 116#define mmSDMA3_EDC_COUNTER_CLEAR 0x0037 117#define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX 1 118#define mmSDMA3_STATUS2_REG 0x0038 119#define mmSDMA3_STATUS2_REG_BASE_IDX 1 120#define mmSDMA3_ATOMIC_CNTL 0x0039 121#define mmSDMA3_ATOMIC_CNTL_BASE_IDX 1 122#define mmSDMA3_ATOMIC_PREOP_LO 0x003a 123#define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX 1 124#define mmSDMA3_ATOMIC_PREOP_HI 0x003b 125#define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX 1 126#define mmSDMA3_UTCL1_CNTL 0x003c 127#define mmSDMA3_UTCL1_CNTL_BASE_IDX 1 128#define mmSDMA3_UTCL1_WATERMK 0x003d 129#define mmSDMA3_UTCL1_WATERMK_BASE_IDX 1 130#define mmSDMA3_UTCL1_RD_STATUS 0x003e 131#define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX 1 132#define mmSDMA3_UTCL1_WR_STATUS 0x003f 133#define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX 1 134#define mmSDMA3_UTCL1_INV0 0x0040 135#define mmSDMA3_UTCL1_INV0_BASE_IDX 1 136#define mmSDMA3_UTCL1_INV1 0x0041 137#define mmSDMA3_UTCL1_INV1_BASE_IDX 1 138#define mmSDMA3_UTCL1_INV2 0x0042 139#define mmSDMA3_UTCL1_INV2_BASE_IDX 1 140#define mmSDMA3_UTCL1_RD_XNACK0 0x0043 141#define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX 1 142#define mmSDMA3_UTCL1_RD_XNACK1 0x0044 143#define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX 1 144#define mmSDMA3_UTCL1_WR_XNACK0 0x0045 145#define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX 1 146#define mmSDMA3_UTCL1_WR_XNACK1 0x0046 147#define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX 1 148#define mmSDMA3_UTCL1_TIMEOUT 0x0047 149#define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX 1 150#define mmSDMA3_UTCL1_PAGE 0x0048 151#define mmSDMA3_UTCL1_PAGE_BASE_IDX 1 152#define mmSDMA3_POWER_CNTL_IDLE 0x0049 153#define mmSDMA3_POWER_CNTL_IDLE_BASE_IDX 1 154#define mmSDMA3_RELAX_ORDERING_LUT 0x004a 155#define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX 1 156#define mmSDMA3_CHICKEN_BITS_2 0x004b 157#define mmSDMA3_CHICKEN_BITS_2_BASE_IDX 1 158#define mmSDMA3_STATUS3_REG 0x004c 159#define mmSDMA3_STATUS3_REG_BASE_IDX 1 160#define mmSDMA3_PHYSICAL_ADDR_LO 0x004d 161#define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 1 162#define mmSDMA3_PHYSICAL_ADDR_HI 0x004e 163#define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 1 164#define mmSDMA3_PHASE2_QUANTUM 0x004f 165#define mmSDMA3_PHASE2_QUANTUM_BASE_IDX 1 166#define mmSDMA3_ERROR_LOG 0x0050 167#define mmSDMA3_ERROR_LOG_BASE_IDX 1 168#define mmSDMA3_PUB_DUMMY_REG0 0x0051 169#define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX 1 170#define mmSDMA3_PUB_DUMMY_REG1 0x0052 171#define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX 1 172#define mmSDMA3_PUB_DUMMY_REG2 0x0053 173#define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX 1 174#define mmSDMA3_PUB_DUMMY_REG3 0x0054 175#define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX 1 176#define mmSDMA3_F32_COUNTER 0x0055 177#define mmSDMA3_F32_COUNTER_BASE_IDX 1 178#define mmSDMA3_UNBREAKABLE 0x0056 179#define mmSDMA3_UNBREAKABLE_BASE_IDX 1 180#define mmSDMA3_PERFMON_CNTL 0x0057 181#define mmSDMA3_PERFMON_CNTL_BASE_IDX 1 182#define mmSDMA3_PERFCOUNTER0_RESULT 0x0058 183#define mmSDMA3_PERFCOUNTER0_RESULT_BASE_IDX 1 184#define mmSDMA3_PERFCOUNTER1_RESULT 0x0059 185#define mmSDMA3_PERFCOUNTER1_RESULT_BASE_IDX 1 186#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 187#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 188#define mmSDMA3_CRD_CNTL 0x005b 189#define mmSDMA3_CRD_CNTL_BASE_IDX 1 190#define mmSDMA3_GPU_IOV_VIOLATION_LOG 0x005d 191#define mmSDMA3_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 192#define mmSDMA3_ULV_CNTL 0x005e 193#define mmSDMA3_ULV_CNTL_BASE_IDX 1 194#define mmSDMA3_EA_DBIT_ADDR_DATA 0x0060 195#define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 1 196#define mmSDMA3_EA_DBIT_ADDR_INDEX 0x0061 197#define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 1 198#define mmSDMA3_GPU_IOV_VIOLATION_LOG2 0x0062 199#define mmSDMA3_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 200#define mmSDMA3_GFX_RB_CNTL 0x0080 201#define mmSDMA3_GFX_RB_CNTL_BASE_IDX 1 202#define mmSDMA3_GFX_RB_BASE 0x0081 203#define mmSDMA3_GFX_RB_BASE_BASE_IDX 1 204#define mmSDMA3_GFX_RB_BASE_HI 0x0082 205#define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX 1 206#define mmSDMA3_GFX_RB_RPTR 0x0083 207#define mmSDMA3_GFX_RB_RPTR_BASE_IDX 1 208#define mmSDMA3_GFX_RB_RPTR_HI 0x0084 209#define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX 1 210#define mmSDMA3_GFX_RB_WPTR 0x0085 211#define mmSDMA3_GFX_RB_WPTR_BASE_IDX 1 212#define mmSDMA3_GFX_RB_WPTR_HI 0x0086 213#define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX 1 214#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0x0087 215#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 216#define mmSDMA3_GFX_RB_RPTR_ADDR_HI 0x0088 217#define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 218#define mmSDMA3_GFX_RB_RPTR_ADDR_LO 0x0089 219#define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 220#define mmSDMA3_GFX_IB_CNTL 0x008a 221#define mmSDMA3_GFX_IB_CNTL_BASE_IDX 1 222#define mmSDMA3_GFX_IB_RPTR 0x008b 223#define mmSDMA3_GFX_IB_RPTR_BASE_IDX 1 224#define mmSDMA3_GFX_IB_OFFSET 0x008c 225#define mmSDMA3_GFX_IB_OFFSET_BASE_IDX 1 226#define mmSDMA3_GFX_IB_BASE_LO 0x008d 227#define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX 1 228#define mmSDMA3_GFX_IB_BASE_HI 0x008e 229#define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX 1 230#define mmSDMA3_GFX_IB_SIZE 0x008f 231#define mmSDMA3_GFX_IB_SIZE_BASE_IDX 1 232#define mmSDMA3_GFX_SKIP_CNTL 0x0090 233#define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX 1 234#define mmSDMA3_GFX_CONTEXT_STATUS 0x0091 235#define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 1 236#define mmSDMA3_GFX_DOORBELL 0x0092 237#define mmSDMA3_GFX_DOORBELL_BASE_IDX 1 238#define mmSDMA3_GFX_CONTEXT_CNTL 0x0093 239#define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 1 240#define mmSDMA3_GFX_STATUS 0x00a8 241#define mmSDMA3_GFX_STATUS_BASE_IDX 1 242#define mmSDMA3_GFX_DOORBELL_LOG 0x00a9 243#define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX 1 244#define mmSDMA3_GFX_WATERMARK 0x00aa 245#define mmSDMA3_GFX_WATERMARK_BASE_IDX 1 246#define mmSDMA3_GFX_DOORBELL_OFFSET 0x00ab 247#define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 1 248#define mmSDMA3_GFX_CSA_ADDR_LO 0x00ac 249#define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 1 250#define mmSDMA3_GFX_CSA_ADDR_HI 0x00ad 251#define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 1 252#define mmSDMA3_GFX_IB_SUB_REMAIN 0x00af 253#define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 1 254#define mmSDMA3_GFX_PREEMPT 0x00b0 255#define mmSDMA3_GFX_PREEMPT_BASE_IDX 1 256#define mmSDMA3_GFX_DUMMY_REG 0x00b1 257#define mmSDMA3_GFX_DUMMY_REG_BASE_IDX 1 258#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 259#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 260#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 261#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 262#define mmSDMA3_GFX_RB_AQL_CNTL 0x00b4 263#define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 1 264#define mmSDMA3_GFX_MINOR_PTR_UPDATE 0x00b5 265#define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 266#define mmSDMA3_GFX_MIDCMD_DATA0 0x00c0 267#define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 1 268#define mmSDMA3_GFX_MIDCMD_DATA1 0x00c1 269#define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 1 270#define mmSDMA3_GFX_MIDCMD_DATA2 0x00c2 271#define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 1 272#define mmSDMA3_GFX_MIDCMD_DATA3 0x00c3 273#define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 1 274#define mmSDMA3_GFX_MIDCMD_DATA4 0x00c4 275#define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 1 276#define mmSDMA3_GFX_MIDCMD_DATA5 0x00c5 277#define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 1 278#define mmSDMA3_GFX_MIDCMD_DATA6 0x00c6 279#define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 1 280#define mmSDMA3_GFX_MIDCMD_DATA7 0x00c7 281#define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 1 282#define mmSDMA3_GFX_MIDCMD_DATA8 0x00c8 283#define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 1 284#define mmSDMA3_GFX_MIDCMD_CNTL 0x00c9 285#define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 1 286#define mmSDMA3_PAGE_RB_CNTL 0x00d8 287#define mmSDMA3_PAGE_RB_CNTL_BASE_IDX 1 288#define mmSDMA3_PAGE_RB_BASE 0x00d9 289#define mmSDMA3_PAGE_RB_BASE_BASE_IDX 1 290#define mmSDMA3_PAGE_RB_BASE_HI 0x00da 291#define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX 1 292#define mmSDMA3_PAGE_RB_RPTR 0x00db 293#define mmSDMA3_PAGE_RB_RPTR_BASE_IDX 1 294#define mmSDMA3_PAGE_RB_RPTR_HI 0x00dc 295#define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 1 296#define mmSDMA3_PAGE_RB_WPTR 0x00dd 297#define mmSDMA3_PAGE_RB_WPTR_BASE_IDX 1 298#define mmSDMA3_PAGE_RB_WPTR_HI 0x00de 299#define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 1 300#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x00df 301#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 302#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0x00e0 303#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 304#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0x00e1 305#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 306#define mmSDMA3_PAGE_IB_CNTL 0x00e2 307#define mmSDMA3_PAGE_IB_CNTL_BASE_IDX 1 308#define mmSDMA3_PAGE_IB_RPTR 0x00e3 309#define mmSDMA3_PAGE_IB_RPTR_BASE_IDX 1 310#define mmSDMA3_PAGE_IB_OFFSET 0x00e4 311#define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX 1 312#define mmSDMA3_PAGE_IB_BASE_LO 0x00e5 313#define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX 1 314#define mmSDMA3_PAGE_IB_BASE_HI 0x00e6 315#define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX 1 316#define mmSDMA3_PAGE_IB_SIZE 0x00e7 317#define mmSDMA3_PAGE_IB_SIZE_BASE_IDX 1 318#define mmSDMA3_PAGE_SKIP_CNTL 0x00e8 319#define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX 1 320#define mmSDMA3_PAGE_CONTEXT_STATUS 0x00e9 321#define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 1 322#define mmSDMA3_PAGE_DOORBELL 0x00ea 323#define mmSDMA3_PAGE_DOORBELL_BASE_IDX 1 324#define mmSDMA3_PAGE_STATUS 0x0100 325#define mmSDMA3_PAGE_STATUS_BASE_IDX 1 326#define mmSDMA3_PAGE_DOORBELL_LOG 0x0101 327#define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 1 328#define mmSDMA3_PAGE_WATERMARK 0x0102 329#define mmSDMA3_PAGE_WATERMARK_BASE_IDX 1 330#define mmSDMA3_PAGE_DOORBELL_OFFSET 0x0103 331#define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 1 332#define mmSDMA3_PAGE_CSA_ADDR_LO 0x0104 333#define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 1 334#define mmSDMA3_PAGE_CSA_ADDR_HI 0x0105 335#define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 1 336#define mmSDMA3_PAGE_IB_SUB_REMAIN 0x0107 337#define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 1 338#define mmSDMA3_PAGE_PREEMPT 0x0108 339#define mmSDMA3_PAGE_PREEMPT_BASE_IDX 1 340#define mmSDMA3_PAGE_DUMMY_REG 0x0109 341#define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX 1 342#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a 343#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 344#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b 345#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 346#define mmSDMA3_PAGE_RB_AQL_CNTL 0x010c 347#define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 1 348#define mmSDMA3_PAGE_MINOR_PTR_UPDATE 0x010d 349#define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 350#define mmSDMA3_PAGE_MIDCMD_DATA0 0x0118 351#define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 1 352#define mmSDMA3_PAGE_MIDCMD_DATA1 0x0119 353#define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 1 354#define mmSDMA3_PAGE_MIDCMD_DATA2 0x011a 355#define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 1 356#define mmSDMA3_PAGE_MIDCMD_DATA3 0x011b 357#define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 1 358#define mmSDMA3_PAGE_MIDCMD_DATA4 0x011c 359#define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 1 360#define mmSDMA3_PAGE_MIDCMD_DATA5 0x011d 361#define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 1 362#define mmSDMA3_PAGE_MIDCMD_DATA6 0x011e 363#define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 1 364#define mmSDMA3_PAGE_MIDCMD_DATA7 0x011f 365#define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 1 366#define mmSDMA3_PAGE_MIDCMD_DATA8 0x0120 367#define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 1 368#define mmSDMA3_PAGE_MIDCMD_CNTL 0x0121 369#define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 1 370#define mmSDMA3_RLC0_RB_CNTL 0x0130 371#define mmSDMA3_RLC0_RB_CNTL_BASE_IDX 1 372#define mmSDMA3_RLC0_RB_BASE 0x0131 373#define mmSDMA3_RLC0_RB_BASE_BASE_IDX 1 374#define mmSDMA3_RLC0_RB_BASE_HI 0x0132 375#define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX 1 376#define mmSDMA3_RLC0_RB_RPTR 0x0133 377#define mmSDMA3_RLC0_RB_RPTR_BASE_IDX 1 378#define mmSDMA3_RLC0_RB_RPTR_HI 0x0134 379#define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 1 380#define mmSDMA3_RLC0_RB_WPTR 0x0135 381#define mmSDMA3_RLC0_RB_WPTR_BASE_IDX 1 382#define mmSDMA3_RLC0_RB_WPTR_HI 0x0136 383#define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 1 384#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x0137 385#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 386#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0x0138 387#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 388#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0x0139 389#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 390#define mmSDMA3_RLC0_IB_CNTL 0x013a 391#define mmSDMA3_RLC0_IB_CNTL_BASE_IDX 1 392#define mmSDMA3_RLC0_IB_RPTR 0x013b 393#define mmSDMA3_RLC0_IB_RPTR_BASE_IDX 1 394#define mmSDMA3_RLC0_IB_OFFSET 0x013c 395#define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX 1 396#define mmSDMA3_RLC0_IB_BASE_LO 0x013d 397#define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX 1 398#define mmSDMA3_RLC0_IB_BASE_HI 0x013e 399#define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX 1 400#define mmSDMA3_RLC0_IB_SIZE 0x013f 401#define mmSDMA3_RLC0_IB_SIZE_BASE_IDX 1 402#define mmSDMA3_RLC0_SKIP_CNTL 0x0140 403#define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX 1 404#define mmSDMA3_RLC0_CONTEXT_STATUS 0x0141 405#define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 1 406#define mmSDMA3_RLC0_DOORBELL 0x0142 407#define mmSDMA3_RLC0_DOORBELL_BASE_IDX 1 408#define mmSDMA3_RLC0_STATUS 0x0158 409#define mmSDMA3_RLC0_STATUS_BASE_IDX 1 410#define mmSDMA3_RLC0_DOORBELL_LOG 0x0159 411#define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 1 412#define mmSDMA3_RLC0_WATERMARK 0x015a 413#define mmSDMA3_RLC0_WATERMARK_BASE_IDX 1 414#define mmSDMA3_RLC0_DOORBELL_OFFSET 0x015b 415#define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 1 416#define mmSDMA3_RLC0_CSA_ADDR_LO 0x015c 417#define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 1 418#define mmSDMA3_RLC0_CSA_ADDR_HI 0x015d 419#define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 1 420#define mmSDMA3_RLC0_IB_SUB_REMAIN 0x015f 421#define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 1 422#define mmSDMA3_RLC0_PREEMPT 0x0160 423#define mmSDMA3_RLC0_PREEMPT_BASE_IDX 1 424#define mmSDMA3_RLC0_DUMMY_REG 0x0161 425#define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX 1 426#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 427#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 428#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 429#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 430#define mmSDMA3_RLC0_RB_AQL_CNTL 0x0164 431#define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 1 432#define mmSDMA3_RLC0_MINOR_PTR_UPDATE 0x0165 433#define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 434#define mmSDMA3_RLC0_MIDCMD_DATA0 0x0170 435#define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 1 436#define mmSDMA3_RLC0_MIDCMD_DATA1 0x0171 437#define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 1 438#define mmSDMA3_RLC0_MIDCMD_DATA2 0x0172 439#define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 1 440#define mmSDMA3_RLC0_MIDCMD_DATA3 0x0173 441#define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 1 442#define mmSDMA3_RLC0_MIDCMD_DATA4 0x0174 443#define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 1 444#define mmSDMA3_RLC0_MIDCMD_DATA5 0x0175 445#define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 1 446#define mmSDMA3_RLC0_MIDCMD_DATA6 0x0176 447#define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 1 448#define mmSDMA3_RLC0_MIDCMD_DATA7 0x0177 449#define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 1 450#define mmSDMA3_RLC0_MIDCMD_DATA8 0x0178 451#define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 1 452#define mmSDMA3_RLC0_MIDCMD_CNTL 0x0179 453#define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 1 454#define mmSDMA3_RLC1_RB_CNTL 0x0188 455#define mmSDMA3_RLC1_RB_CNTL_BASE_IDX 1 456#define mmSDMA3_RLC1_RB_BASE 0x0189 457#define mmSDMA3_RLC1_RB_BASE_BASE_IDX 1 458#define mmSDMA3_RLC1_RB_BASE_HI 0x018a 459#define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX 1 460#define mmSDMA3_RLC1_RB_RPTR 0x018b 461#define mmSDMA3_RLC1_RB_RPTR_BASE_IDX 1 462#define mmSDMA3_RLC1_RB_RPTR_HI 0x018c 463#define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 1 464#define mmSDMA3_RLC1_RB_WPTR 0x018d 465#define mmSDMA3_RLC1_RB_WPTR_BASE_IDX 1 466#define mmSDMA3_RLC1_RB_WPTR_HI 0x018e 467#define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 1 468#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x018f 469#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 470#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0x0190 471#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 472#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0x0191 473#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 474#define mmSDMA3_RLC1_IB_CNTL 0x0192 475#define mmSDMA3_RLC1_IB_CNTL_BASE_IDX 1 476#define mmSDMA3_RLC1_IB_RPTR 0x0193 477#define mmSDMA3_RLC1_IB_RPTR_BASE_IDX 1 478#define mmSDMA3_RLC1_IB_OFFSET 0x0194 479#define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX 1 480#define mmSDMA3_RLC1_IB_BASE_LO 0x0195 481#define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX 1 482#define mmSDMA3_RLC1_IB_BASE_HI 0x0196 483#define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX 1 484#define mmSDMA3_RLC1_IB_SIZE 0x0197 485#define mmSDMA3_RLC1_IB_SIZE_BASE_IDX 1 486#define mmSDMA3_RLC1_SKIP_CNTL 0x0198 487#define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX 1 488#define mmSDMA3_RLC1_CONTEXT_STATUS 0x0199 489#define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 1 490#define mmSDMA3_RLC1_DOORBELL 0x019a 491#define mmSDMA3_RLC1_DOORBELL_BASE_IDX 1 492#define mmSDMA3_RLC1_STATUS 0x01b0 493#define mmSDMA3_RLC1_STATUS_BASE_IDX 1 494#define mmSDMA3_RLC1_DOORBELL_LOG 0x01b1 495#define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 1 496#define mmSDMA3_RLC1_WATERMARK 0x01b2 497#define mmSDMA3_RLC1_WATERMARK_BASE_IDX 1 498#define mmSDMA3_RLC1_DOORBELL_OFFSET 0x01b3 499#define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 1 500#define mmSDMA3_RLC1_CSA_ADDR_LO 0x01b4 501#define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 1 502#define mmSDMA3_RLC1_CSA_ADDR_HI 0x01b5 503#define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 1 504#define mmSDMA3_RLC1_IB_SUB_REMAIN 0x01b7 505#define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 1 506#define mmSDMA3_RLC1_PREEMPT 0x01b8 507#define mmSDMA3_RLC1_PREEMPT_BASE_IDX 1 508#define mmSDMA3_RLC1_DUMMY_REG 0x01b9 509#define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX 1 510#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba 511#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 512#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb 513#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 514#define mmSDMA3_RLC1_RB_AQL_CNTL 0x01bc 515#define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 1 516#define mmSDMA3_RLC1_MINOR_PTR_UPDATE 0x01bd 517#define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 518#define mmSDMA3_RLC1_MIDCMD_DATA0 0x01c8 519#define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 1 520#define mmSDMA3_RLC1_MIDCMD_DATA1 0x01c9 521#define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 1 522#define mmSDMA3_RLC1_MIDCMD_DATA2 0x01ca 523#define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 1 524#define mmSDMA3_RLC1_MIDCMD_DATA3 0x01cb 525#define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 1 526#define mmSDMA3_RLC1_MIDCMD_DATA4 0x01cc 527#define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 1 528#define mmSDMA3_RLC1_MIDCMD_DATA5 0x01cd 529#define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 1 530#define mmSDMA3_RLC1_MIDCMD_DATA6 0x01ce 531#define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 1 532#define mmSDMA3_RLC1_MIDCMD_DATA7 0x01cf 533#define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 1 534#define mmSDMA3_RLC1_MIDCMD_DATA8 0x01d0 535#define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 1 536#define mmSDMA3_RLC1_MIDCMD_CNTL 0x01d1 537#define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 1 538#define mmSDMA3_RLC2_RB_CNTL 0x01e0 539#define mmSDMA3_RLC2_RB_CNTL_BASE_IDX 1 540#define mmSDMA3_RLC2_RB_BASE 0x01e1 541#define mmSDMA3_RLC2_RB_BASE_BASE_IDX 1 542#define mmSDMA3_RLC2_RB_BASE_HI 0x01e2 543#define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX 1 544#define mmSDMA3_RLC2_RB_RPTR 0x01e3 545#define mmSDMA3_RLC2_RB_RPTR_BASE_IDX 1 546#define mmSDMA3_RLC2_RB_RPTR_HI 0x01e4 547#define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 1 548#define mmSDMA3_RLC2_RB_WPTR 0x01e5 549#define mmSDMA3_RLC2_RB_WPTR_BASE_IDX 1 550#define mmSDMA3_RLC2_RB_WPTR_HI 0x01e6 551#define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 1 552#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x01e7 553#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 554#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0x01e8 555#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 556#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0x01e9 557#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 558#define mmSDMA3_RLC2_IB_CNTL 0x01ea 559#define mmSDMA3_RLC2_IB_CNTL_BASE_IDX 1 560#define mmSDMA3_RLC2_IB_RPTR 0x01eb 561#define mmSDMA3_RLC2_IB_RPTR_BASE_IDX 1 562#define mmSDMA3_RLC2_IB_OFFSET 0x01ec 563#define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX 1 564#define mmSDMA3_RLC2_IB_BASE_LO 0x01ed 565#define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX 1 566#define mmSDMA3_RLC2_IB_BASE_HI 0x01ee 567#define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX 1 568#define mmSDMA3_RLC2_IB_SIZE 0x01ef 569#define mmSDMA3_RLC2_IB_SIZE_BASE_IDX 1 570#define mmSDMA3_RLC2_SKIP_CNTL 0x01f0 571#define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX 1 572#define mmSDMA3_RLC2_CONTEXT_STATUS 0x01f1 573#define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 1 574#define mmSDMA3_RLC2_DOORBELL 0x01f2 575#define mmSDMA3_RLC2_DOORBELL_BASE_IDX 1 576#define mmSDMA3_RLC2_STATUS 0x0208 577#define mmSDMA3_RLC2_STATUS_BASE_IDX 1 578#define mmSDMA3_RLC2_DOORBELL_LOG 0x0209 579#define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 1 580#define mmSDMA3_RLC2_WATERMARK 0x020a 581#define mmSDMA3_RLC2_WATERMARK_BASE_IDX 1 582#define mmSDMA3_RLC2_DOORBELL_OFFSET 0x020b 583#define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 1 584#define mmSDMA3_RLC2_CSA_ADDR_LO 0x020c 585#define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 1 586#define mmSDMA3_RLC2_CSA_ADDR_HI 0x020d 587#define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 1 588#define mmSDMA3_RLC2_IB_SUB_REMAIN 0x020f 589#define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 1 590#define mmSDMA3_RLC2_PREEMPT 0x0210 591#define mmSDMA3_RLC2_PREEMPT_BASE_IDX 1 592#define mmSDMA3_RLC2_DUMMY_REG 0x0211 593#define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX 1 594#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 595#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 596#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 597#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 598#define mmSDMA3_RLC2_RB_AQL_CNTL 0x0214 599#define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 1 600#define mmSDMA3_RLC2_MINOR_PTR_UPDATE 0x0215 601#define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 602#define mmSDMA3_RLC2_MIDCMD_DATA0 0x0220 603#define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 1 604#define mmSDMA3_RLC2_MIDCMD_DATA1 0x0221 605#define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 1 606#define mmSDMA3_RLC2_MIDCMD_DATA2 0x0222 607#define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 1 608#define mmSDMA3_RLC2_MIDCMD_DATA3 0x0223 609#define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 1 610#define mmSDMA3_RLC2_MIDCMD_DATA4 0x0224 611#define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 1 612#define mmSDMA3_RLC2_MIDCMD_DATA5 0x0225 613#define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 1 614#define mmSDMA3_RLC2_MIDCMD_DATA6 0x0226 615#define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 1 616#define mmSDMA3_RLC2_MIDCMD_DATA7 0x0227 617#define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 1 618#define mmSDMA3_RLC2_MIDCMD_DATA8 0x0228 619#define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 1 620#define mmSDMA3_RLC2_MIDCMD_CNTL 0x0229 621#define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 1 622#define mmSDMA3_RLC3_RB_CNTL 0x0238 623#define mmSDMA3_RLC3_RB_CNTL_BASE_IDX 1 624#define mmSDMA3_RLC3_RB_BASE 0x0239 625#define mmSDMA3_RLC3_RB_BASE_BASE_IDX 1 626#define mmSDMA3_RLC3_RB_BASE_HI 0x023a 627#define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX 1 628#define mmSDMA3_RLC3_RB_RPTR 0x023b 629#define mmSDMA3_RLC3_RB_RPTR_BASE_IDX 1 630#define mmSDMA3_RLC3_RB_RPTR_HI 0x023c 631#define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 1 632#define mmSDMA3_RLC3_RB_WPTR 0x023d 633#define mmSDMA3_RLC3_RB_WPTR_BASE_IDX 1 634#define mmSDMA3_RLC3_RB_WPTR_HI 0x023e 635#define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 1 636#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x023f 637#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 638#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0x0240 639#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 640#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0x0241 641#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 642#define mmSDMA3_RLC3_IB_CNTL 0x0242 643#define mmSDMA3_RLC3_IB_CNTL_BASE_IDX 1 644#define mmSDMA3_RLC3_IB_RPTR 0x0243 645#define mmSDMA3_RLC3_IB_RPTR_BASE_IDX 1 646#define mmSDMA3_RLC3_IB_OFFSET 0x0244 647#define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX 1 648#define mmSDMA3_RLC3_IB_BASE_LO 0x0245 649#define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX 1 650#define mmSDMA3_RLC3_IB_BASE_HI 0x0246 651#define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX 1 652#define mmSDMA3_RLC3_IB_SIZE 0x0247 653#define mmSDMA3_RLC3_IB_SIZE_BASE_IDX 1 654#define mmSDMA3_RLC3_SKIP_CNTL 0x0248 655#define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX 1 656#define mmSDMA3_RLC3_CONTEXT_STATUS 0x0249 657#define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 1 658#define mmSDMA3_RLC3_DOORBELL 0x024a 659#define mmSDMA3_RLC3_DOORBELL_BASE_IDX 1 660#define mmSDMA3_RLC3_STATUS 0x0260 661#define mmSDMA3_RLC3_STATUS_BASE_IDX 1 662#define mmSDMA3_RLC3_DOORBELL_LOG 0x0261 663#define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 1 664#define mmSDMA3_RLC3_WATERMARK 0x0262 665#define mmSDMA3_RLC3_WATERMARK_BASE_IDX 1 666#define mmSDMA3_RLC3_DOORBELL_OFFSET 0x0263 667#define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 1 668#define mmSDMA3_RLC3_CSA_ADDR_LO 0x0264 669#define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 1 670#define mmSDMA3_RLC3_CSA_ADDR_HI 0x0265 671#define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 1 672#define mmSDMA3_RLC3_IB_SUB_REMAIN 0x0267 673#define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 1 674#define mmSDMA3_RLC3_PREEMPT 0x0268 675#define mmSDMA3_RLC3_PREEMPT_BASE_IDX 1 676#define mmSDMA3_RLC3_DUMMY_REG 0x0269 677#define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX 1 678#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a 679#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 680#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b 681#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 682#define mmSDMA3_RLC3_RB_AQL_CNTL 0x026c 683#define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 1 684#define mmSDMA3_RLC3_MINOR_PTR_UPDATE 0x026d 685#define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 686#define mmSDMA3_RLC3_MIDCMD_DATA0 0x0278 687#define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 1 688#define mmSDMA3_RLC3_MIDCMD_DATA1 0x0279 689#define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 1 690#define mmSDMA3_RLC3_MIDCMD_DATA2 0x027a 691#define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 1 692#define mmSDMA3_RLC3_MIDCMD_DATA3 0x027b 693#define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 1 694#define mmSDMA3_RLC3_MIDCMD_DATA4 0x027c 695#define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 1 696#define mmSDMA3_RLC3_MIDCMD_DATA5 0x027d 697#define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 1 698#define mmSDMA3_RLC3_MIDCMD_DATA6 0x027e 699#define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 1 700#define mmSDMA3_RLC3_MIDCMD_DATA7 0x027f 701#define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 1 702#define mmSDMA3_RLC3_MIDCMD_DATA8 0x0280 703#define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 1 704#define mmSDMA3_RLC3_MIDCMD_CNTL 0x0281 705#define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 1 706#define mmSDMA3_RLC4_RB_CNTL 0x0290 707#define mmSDMA3_RLC4_RB_CNTL_BASE_IDX 1 708#define mmSDMA3_RLC4_RB_BASE 0x0291 709#define mmSDMA3_RLC4_RB_BASE_BASE_IDX 1 710#define mmSDMA3_RLC4_RB_BASE_HI 0x0292 711#define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX 1 712#define mmSDMA3_RLC4_RB_RPTR 0x0293 713#define mmSDMA3_RLC4_RB_RPTR_BASE_IDX 1 714#define mmSDMA3_RLC4_RB_RPTR_HI 0x0294 715#define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 1 716#define mmSDMA3_RLC4_RB_WPTR 0x0295 717#define mmSDMA3_RLC4_RB_WPTR_BASE_IDX 1 718#define mmSDMA3_RLC4_RB_WPTR_HI 0x0296 719#define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 1 720#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x0297 721#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 722#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0x0298 723#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 724#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0x0299 725#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 726#define mmSDMA3_RLC4_IB_CNTL 0x029a 727#define mmSDMA3_RLC4_IB_CNTL_BASE_IDX 1 728#define mmSDMA3_RLC4_IB_RPTR 0x029b 729#define mmSDMA3_RLC4_IB_RPTR_BASE_IDX 1 730#define mmSDMA3_RLC4_IB_OFFSET 0x029c 731#define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX 1 732#define mmSDMA3_RLC4_IB_BASE_LO 0x029d 733#define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX 1 734#define mmSDMA3_RLC4_IB_BASE_HI 0x029e 735#define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX 1 736#define mmSDMA3_RLC4_IB_SIZE 0x029f 737#define mmSDMA3_RLC4_IB_SIZE_BASE_IDX 1 738#define mmSDMA3_RLC4_SKIP_CNTL 0x02a0 739#define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX 1 740#define mmSDMA3_RLC4_CONTEXT_STATUS 0x02a1 741#define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 1 742#define mmSDMA3_RLC4_DOORBELL 0x02a2 743#define mmSDMA3_RLC4_DOORBELL_BASE_IDX 1 744#define mmSDMA3_RLC4_STATUS 0x02b8 745#define mmSDMA3_RLC4_STATUS_BASE_IDX 1 746#define mmSDMA3_RLC4_DOORBELL_LOG 0x02b9 747#define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 1 748#define mmSDMA3_RLC4_WATERMARK 0x02ba 749#define mmSDMA3_RLC4_WATERMARK_BASE_IDX 1 750#define mmSDMA3_RLC4_DOORBELL_OFFSET 0x02bb 751#define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 1 752#define mmSDMA3_RLC4_CSA_ADDR_LO 0x02bc 753#define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 1 754#define mmSDMA3_RLC4_CSA_ADDR_HI 0x02bd 755#define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 1 756#define mmSDMA3_RLC4_IB_SUB_REMAIN 0x02bf 757#define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 1 758#define mmSDMA3_RLC4_PREEMPT 0x02c0 759#define mmSDMA3_RLC4_PREEMPT_BASE_IDX 1 760#define mmSDMA3_RLC4_DUMMY_REG 0x02c1 761#define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX 1 762#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 763#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 764#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 765#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 766#define mmSDMA3_RLC4_RB_AQL_CNTL 0x02c4 767#define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 1 768#define mmSDMA3_RLC4_MINOR_PTR_UPDATE 0x02c5 769#define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 770#define mmSDMA3_RLC4_MIDCMD_DATA0 0x02d0 771#define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 1 772#define mmSDMA3_RLC4_MIDCMD_DATA1 0x02d1 773#define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 1 774#define mmSDMA3_RLC4_MIDCMD_DATA2 0x02d2 775#define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 1 776#define mmSDMA3_RLC4_MIDCMD_DATA3 0x02d3 777#define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 1 778#define mmSDMA3_RLC4_MIDCMD_DATA4 0x02d4 779#define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 1 780#define mmSDMA3_RLC4_MIDCMD_DATA5 0x02d5 781#define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 1 782#define mmSDMA3_RLC4_MIDCMD_DATA6 0x02d6 783#define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 1 784#define mmSDMA3_RLC4_MIDCMD_DATA7 0x02d7 785#define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 1 786#define mmSDMA3_RLC4_MIDCMD_DATA8 0x02d8 787#define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 1 788#define mmSDMA3_RLC4_MIDCMD_CNTL 0x02d9 789#define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 1 790#define mmSDMA3_RLC5_RB_CNTL 0x02e8 791#define mmSDMA3_RLC5_RB_CNTL_BASE_IDX 1 792#define mmSDMA3_RLC5_RB_BASE 0x02e9 793#define mmSDMA3_RLC5_RB_BASE_BASE_IDX 1 794#define mmSDMA3_RLC5_RB_BASE_HI 0x02ea 795#define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX 1 796#define mmSDMA3_RLC5_RB_RPTR 0x02eb 797#define mmSDMA3_RLC5_RB_RPTR_BASE_IDX 1 798#define mmSDMA3_RLC5_RB_RPTR_HI 0x02ec 799#define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 1 800#define mmSDMA3_RLC5_RB_WPTR 0x02ed 801#define mmSDMA3_RLC5_RB_WPTR_BASE_IDX 1 802#define mmSDMA3_RLC5_RB_WPTR_HI 0x02ee 803#define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 1 804#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x02ef 805#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 806#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0x02f0 807#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 808#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0x02f1 809#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 810#define mmSDMA3_RLC5_IB_CNTL 0x02f2 811#define mmSDMA3_RLC5_IB_CNTL_BASE_IDX 1 812#define mmSDMA3_RLC5_IB_RPTR 0x02f3 813#define mmSDMA3_RLC5_IB_RPTR_BASE_IDX 1 814#define mmSDMA3_RLC5_IB_OFFSET 0x02f4 815#define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX 1 816#define mmSDMA3_RLC5_IB_BASE_LO 0x02f5 817#define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX 1 818#define mmSDMA3_RLC5_IB_BASE_HI 0x02f6 819#define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX 1 820#define mmSDMA3_RLC5_IB_SIZE 0x02f7 821#define mmSDMA3_RLC5_IB_SIZE_BASE_IDX 1 822#define mmSDMA3_RLC5_SKIP_CNTL 0x02f8 823#define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX 1 824#define mmSDMA3_RLC5_CONTEXT_STATUS 0x02f9 825#define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 1 826#define mmSDMA3_RLC5_DOORBELL 0x02fa 827#define mmSDMA3_RLC5_DOORBELL_BASE_IDX 1 828#define mmSDMA3_RLC5_STATUS 0x0310 829#define mmSDMA3_RLC5_STATUS_BASE_IDX 1 830#define mmSDMA3_RLC5_DOORBELL_LOG 0x0311 831#define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 1 832#define mmSDMA3_RLC5_WATERMARK 0x0312 833#define mmSDMA3_RLC5_WATERMARK_BASE_IDX 1 834#define mmSDMA3_RLC5_DOORBELL_OFFSET 0x0313 835#define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 1 836#define mmSDMA3_RLC5_CSA_ADDR_LO 0x0314 837#define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 1 838#define mmSDMA3_RLC5_CSA_ADDR_HI 0x0315 839#define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 1 840#define mmSDMA3_RLC5_IB_SUB_REMAIN 0x0317 841#define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 1 842#define mmSDMA3_RLC5_PREEMPT 0x0318 843#define mmSDMA3_RLC5_PREEMPT_BASE_IDX 1 844#define mmSDMA3_RLC5_DUMMY_REG 0x0319 845#define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX 1 846#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a 847#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 848#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b 849#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 850#define mmSDMA3_RLC5_RB_AQL_CNTL 0x031c 851#define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 1 852#define mmSDMA3_RLC5_MINOR_PTR_UPDATE 0x031d 853#define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 854#define mmSDMA3_RLC5_MIDCMD_DATA0 0x0328 855#define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 1 856#define mmSDMA3_RLC5_MIDCMD_DATA1 0x0329 857#define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 1 858#define mmSDMA3_RLC5_MIDCMD_DATA2 0x032a 859#define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 1 860#define mmSDMA3_RLC5_MIDCMD_DATA3 0x032b 861#define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 1 862#define mmSDMA3_RLC5_MIDCMD_DATA4 0x032c 863#define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 1 864#define mmSDMA3_RLC5_MIDCMD_DATA5 0x032d 865#define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 1 866#define mmSDMA3_RLC5_MIDCMD_DATA6 0x032e 867#define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 1 868#define mmSDMA3_RLC5_MIDCMD_DATA7 0x032f 869#define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 1 870#define mmSDMA3_RLC5_MIDCMD_DATA8 0x0330 871#define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 1 872#define mmSDMA3_RLC5_MIDCMD_CNTL 0x0331 873#define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 1 874#define mmSDMA3_RLC6_RB_CNTL 0x0340 875#define mmSDMA3_RLC6_RB_CNTL_BASE_IDX 1 876#define mmSDMA3_RLC6_RB_BASE 0x0341 877#define mmSDMA3_RLC6_RB_BASE_BASE_IDX 1 878#define mmSDMA3_RLC6_RB_BASE_HI 0x0342 879#define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX 1 880#define mmSDMA3_RLC6_RB_RPTR 0x0343 881#define mmSDMA3_RLC6_RB_RPTR_BASE_IDX 1 882#define mmSDMA3_RLC6_RB_RPTR_HI 0x0344 883#define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 1 884#define mmSDMA3_RLC6_RB_WPTR 0x0345 885#define mmSDMA3_RLC6_RB_WPTR_BASE_IDX 1 886#define mmSDMA3_RLC6_RB_WPTR_HI 0x0346 887#define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 1 888#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x0347 889#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 890#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0x0348 891#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 892#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0x0349 893#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 894#define mmSDMA3_RLC6_IB_CNTL 0x034a 895#define mmSDMA3_RLC6_IB_CNTL_BASE_IDX 1 896#define mmSDMA3_RLC6_IB_RPTR 0x034b 897#define mmSDMA3_RLC6_IB_RPTR_BASE_IDX 1 898#define mmSDMA3_RLC6_IB_OFFSET 0x034c 899#define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX 1 900#define mmSDMA3_RLC6_IB_BASE_LO 0x034d 901#define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX 1 902#define mmSDMA3_RLC6_IB_BASE_HI 0x034e 903#define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX 1 904#define mmSDMA3_RLC6_IB_SIZE 0x034f 905#define mmSDMA3_RLC6_IB_SIZE_BASE_IDX 1 906#define mmSDMA3_RLC6_SKIP_CNTL 0x0350 907#define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX 1 908#define mmSDMA3_RLC6_CONTEXT_STATUS 0x0351 909#define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 1 910#define mmSDMA3_RLC6_DOORBELL 0x0352 911#define mmSDMA3_RLC6_DOORBELL_BASE_IDX 1 912#define mmSDMA3_RLC6_STATUS 0x0368 913#define mmSDMA3_RLC6_STATUS_BASE_IDX 1 914#define mmSDMA3_RLC6_DOORBELL_LOG 0x0369 915#define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 1 916#define mmSDMA3_RLC6_WATERMARK 0x036a 917#define mmSDMA3_RLC6_WATERMARK_BASE_IDX 1 918#define mmSDMA3_RLC6_DOORBELL_OFFSET 0x036b 919#define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 1 920#define mmSDMA3_RLC6_CSA_ADDR_LO 0x036c 921#define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 1 922#define mmSDMA3_RLC6_CSA_ADDR_HI 0x036d 923#define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 1 924#define mmSDMA3_RLC6_IB_SUB_REMAIN 0x036f 925#define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 1 926#define mmSDMA3_RLC6_PREEMPT 0x0370 927#define mmSDMA3_RLC6_PREEMPT_BASE_IDX 1 928#define mmSDMA3_RLC6_DUMMY_REG 0x0371 929#define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX 1 930#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 931#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 932#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 933#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 934#define mmSDMA3_RLC6_RB_AQL_CNTL 0x0374 935#define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 1 936#define mmSDMA3_RLC6_MINOR_PTR_UPDATE 0x0375 937#define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 938#define mmSDMA3_RLC6_MIDCMD_DATA0 0x0380 939#define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 1 940#define mmSDMA3_RLC6_MIDCMD_DATA1 0x0381 941#define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 1 942#define mmSDMA3_RLC6_MIDCMD_DATA2 0x0382 943#define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 1 944#define mmSDMA3_RLC6_MIDCMD_DATA3 0x0383 945#define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 1 946#define mmSDMA3_RLC6_MIDCMD_DATA4 0x0384 947#define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 1 948#define mmSDMA3_RLC6_MIDCMD_DATA5 0x0385 949#define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 1 950#define mmSDMA3_RLC6_MIDCMD_DATA6 0x0386 951#define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 1 952#define mmSDMA3_RLC6_MIDCMD_DATA7 0x0387 953#define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 1 954#define mmSDMA3_RLC6_MIDCMD_DATA8 0x0388 955#define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 1 956#define mmSDMA3_RLC6_MIDCMD_CNTL 0x0389 957#define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 1 958#define mmSDMA3_RLC7_RB_CNTL 0x0398 959#define mmSDMA3_RLC7_RB_CNTL_BASE_IDX 1 960#define mmSDMA3_RLC7_RB_BASE 0x0399 961#define mmSDMA3_RLC7_RB_BASE_BASE_IDX 1 962#define mmSDMA3_RLC7_RB_BASE_HI 0x039a 963#define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX 1 964#define mmSDMA3_RLC7_RB_RPTR 0x039b 965#define mmSDMA3_RLC7_RB_RPTR_BASE_IDX 1 966#define mmSDMA3_RLC7_RB_RPTR_HI 0x039c 967#define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 1 968#define mmSDMA3_RLC7_RB_WPTR 0x039d 969#define mmSDMA3_RLC7_RB_WPTR_BASE_IDX 1 970#define mmSDMA3_RLC7_RB_WPTR_HI 0x039e 971#define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 1 972#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x039f 973#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 974#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0x03a0 975#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 976#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0x03a1 977#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 978#define mmSDMA3_RLC7_IB_CNTL 0x03a2 979#define mmSDMA3_RLC7_IB_CNTL_BASE_IDX 1 980#define mmSDMA3_RLC7_IB_RPTR 0x03a3 981#define mmSDMA3_RLC7_IB_RPTR_BASE_IDX 1 982#define mmSDMA3_RLC7_IB_OFFSET 0x03a4 983#define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX 1 984#define mmSDMA3_RLC7_IB_BASE_LO 0x03a5 985#define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX 1 986#define mmSDMA3_RLC7_IB_BASE_HI 0x03a6 987#define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX 1 988#define mmSDMA3_RLC7_IB_SIZE 0x03a7 989#define mmSDMA3_RLC7_IB_SIZE_BASE_IDX 1 990#define mmSDMA3_RLC7_SKIP_CNTL 0x03a8 991#define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX 1 992#define mmSDMA3_RLC7_CONTEXT_STATUS 0x03a9 993#define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 1 994#define mmSDMA3_RLC7_DOORBELL 0x03aa 995#define mmSDMA3_RLC7_DOORBELL_BASE_IDX 1 996#define mmSDMA3_RLC7_STATUS 0x03c0 997#define mmSDMA3_RLC7_STATUS_BASE_IDX 1 998#define mmSDMA3_RLC7_DOORBELL_LOG 0x03c1 999#define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 1 1000#define mmSDMA3_RLC7_WATERMARK 0x03c2 1001#define mmSDMA3_RLC7_WATERMARK_BASE_IDX 1 1002#define mmSDMA3_RLC7_DOORBELL_OFFSET 0x03c3 1003#define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 1 1004#define mmSDMA3_RLC7_CSA_ADDR_LO 0x03c4 1005#define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 1 1006#define mmSDMA3_RLC7_CSA_ADDR_HI 0x03c5 1007#define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 1 1008#define mmSDMA3_RLC7_IB_SUB_REMAIN 0x03c7 1009#define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 1 1010#define mmSDMA3_RLC7_PREEMPT 0x03c8 1011#define mmSDMA3_RLC7_PREEMPT_BASE_IDX 1 1012#define mmSDMA3_RLC7_DUMMY_REG 0x03c9 1013#define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX 1 1014#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca 1015#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 1016#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb 1017#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 1018#define mmSDMA3_RLC7_RB_AQL_CNTL 0x03cc 1019#define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 1 1020#define mmSDMA3_RLC7_MINOR_PTR_UPDATE 0x03cd 1021#define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 1022#define mmSDMA3_RLC7_MIDCMD_DATA0 0x03d8 1023#define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 1 1024#define mmSDMA3_RLC7_MIDCMD_DATA1 0x03d9 1025#define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 1 1026#define mmSDMA3_RLC7_MIDCMD_DATA2 0x03da 1027#define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 1 1028#define mmSDMA3_RLC7_MIDCMD_DATA3 0x03db 1029#define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 1 1030#define mmSDMA3_RLC7_MIDCMD_DATA4 0x03dc 1031#define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 1 1032#define mmSDMA3_RLC7_MIDCMD_DATA5 0x03dd 1033#define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 1 1034#define mmSDMA3_RLC7_MIDCMD_DATA6 0x03de 1035#define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 1 1036#define mmSDMA3_RLC7_MIDCMD_DATA7 0x03df 1037#define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 1 1038#define mmSDMA3_RLC7_MIDCMD_DATA8 0x03e0 1039#define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 1 1040#define mmSDMA3_RLC7_MIDCMD_CNTL 0x03e1 1041#define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 1 1042 1043#endif 1044