1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _osssys_4_2_0_SH_MASK_HEADER 24#define _osssys_4_2_0_SH_MASK_HEADER 25 26 27// addressBlock: osssys_osssysdec 28//IH_VMID_0_LUT 29#define IH_VMID_0_LUT__PASID__SHIFT 0x0 30#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL 31//IH_VMID_1_LUT 32#define IH_VMID_1_LUT__PASID__SHIFT 0x0 33#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL 34//IH_VMID_2_LUT 35#define IH_VMID_2_LUT__PASID__SHIFT 0x0 36#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL 37//IH_VMID_3_LUT 38#define IH_VMID_3_LUT__PASID__SHIFT 0x0 39#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL 40//IH_VMID_4_LUT 41#define IH_VMID_4_LUT__PASID__SHIFT 0x0 42#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL 43//IH_VMID_5_LUT 44#define IH_VMID_5_LUT__PASID__SHIFT 0x0 45#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL 46//IH_VMID_6_LUT 47#define IH_VMID_6_LUT__PASID__SHIFT 0x0 48#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL 49//IH_VMID_7_LUT 50#define IH_VMID_7_LUT__PASID__SHIFT 0x0 51#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL 52//IH_VMID_8_LUT 53#define IH_VMID_8_LUT__PASID__SHIFT 0x0 54#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL 55//IH_VMID_9_LUT 56#define IH_VMID_9_LUT__PASID__SHIFT 0x0 57#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL 58//IH_VMID_10_LUT 59#define IH_VMID_10_LUT__PASID__SHIFT 0x0 60#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL 61//IH_VMID_11_LUT 62#define IH_VMID_11_LUT__PASID__SHIFT 0x0 63#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL 64//IH_VMID_12_LUT 65#define IH_VMID_12_LUT__PASID__SHIFT 0x0 66#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL 67//IH_VMID_13_LUT 68#define IH_VMID_13_LUT__PASID__SHIFT 0x0 69#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL 70//IH_VMID_14_LUT 71#define IH_VMID_14_LUT__PASID__SHIFT 0x0 72#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL 73//IH_VMID_15_LUT 74#define IH_VMID_15_LUT__PASID__SHIFT 0x0 75#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL 76//IH_VMID_0_LUT_MM 77#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 78#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL 79//IH_VMID_1_LUT_MM 80#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 81#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL 82//IH_VMID_2_LUT_MM 83#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 84#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL 85//IH_VMID_3_LUT_MM 86#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 87#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL 88//IH_VMID_4_LUT_MM 89#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 90#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL 91//IH_VMID_5_LUT_MM 92#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 93#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL 94//IH_VMID_6_LUT_MM 95#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 96#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL 97//IH_VMID_7_LUT_MM 98#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 99#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL 100//IH_VMID_8_LUT_MM 101#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 102#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL 103//IH_VMID_9_LUT_MM 104#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 105#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL 106//IH_VMID_10_LUT_MM 107#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 108#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL 109//IH_VMID_11_LUT_MM 110#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 111#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL 112//IH_VMID_12_LUT_MM 113#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 114#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL 115//IH_VMID_13_LUT_MM 116#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 117#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL 118//IH_VMID_14_LUT_MM 119#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 120#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL 121//IH_VMID_15_LUT_MM 122#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 123#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL 124//IH_COOKIE_0 125#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 126#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 127#define IH_COOKIE_0__RING_ID__SHIFT 0x10 128#define IH_COOKIE_0__VM_ID__SHIFT 0x18 129#define IH_COOKIE_0__RESERVED__SHIFT 0x1c 130#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f 131#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL 132#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L 133#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L 134#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L 135#define IH_COOKIE_0__RESERVED_MASK 0x70000000L 136#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L 137//IH_COOKIE_1 138#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 139#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL 140//IH_COOKIE_2 141#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 142#define IH_COOKIE_2__RESERVED__SHIFT 0x10 143#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f 144#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL 145#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L 146#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L 147//IH_COOKIE_3 148#define IH_COOKIE_3__PAS_ID__SHIFT 0x0 149#define IH_COOKIE_3__RESERVED__SHIFT 0x10 150#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f 151#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL 152#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L 153#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L 154//IH_COOKIE_4 155#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 156#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL 157//IH_COOKIE_5 158#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 159#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL 160//IH_COOKIE_6 161#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 162#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL 163//IH_COOKIE_7 164#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 165#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL 166//IH_REGISTER_LAST_PART0 167#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 168#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 169//SEM_REQ_INPUT_0 170#define SEM_REQ_INPUT_0__DATA__SHIFT 0x0 171#define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL 172//SEM_REQ_INPUT_1 173#define SEM_REQ_INPUT_1__DATA__SHIFT 0x0 174#define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL 175//SEM_REQ_INPUT_2 176#define SEM_REQ_INPUT_2__DATA__SHIFT 0x0 177#define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL 178//SEM_REQ_INPUT_3 179#define SEM_REQ_INPUT_3__DATA__SHIFT 0x0 180#define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL 181//SEM_REGISTER_LAST_PART0 182#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 183#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 184//IH_RB_CNTL 185#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 186#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 187#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 188#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 189#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 190#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa 191#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb 192#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc 193#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 194#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 195#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 196#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 197#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 198#define IH_RB_CNTL__MC_RO__SHIFT 0x16 199#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 200#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c 201#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 202#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L 203#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL 204#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L 205#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L 206#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 207#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L 208#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L 209#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 210#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 211#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L 212#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L 213#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L 214#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L 215#define IH_RB_CNTL__MC_RO_MASK 0x00400000L 216#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L 217#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L 218#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 219//IH_RB_BASE 220#define IH_RB_BASE__ADDR__SHIFT 0x0 221#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL 222//IH_RB_BASE_HI 223#define IH_RB_BASE_HI__ADDR__SHIFT 0x0 224#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL 225//IH_RB_RPTR 226#define IH_RB_RPTR__OFFSET__SHIFT 0x2 227#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL 228//IH_RB_WPTR 229#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 230#define IH_RB_WPTR__OFFSET__SHIFT 0x2 231#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 232#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 233#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L 234#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL 235#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L 236#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L 237//IH_RB_WPTR_ADDR_HI 238#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 239#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL 240//IH_RB_WPTR_ADDR_LO 241#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 242#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 243//IH_DOORBELL_RPTR 244#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 245#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c 246#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL 247#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L 248//IH_RB_CNTL_RING1 249#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 250#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 251#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7 252#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 253#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa 254#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb 255#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc 256#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 257#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 258#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 259#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 260#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 261#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c 262#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 263#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L 264#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL 265#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L 266#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 267#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L 268#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L 269#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 270#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 271#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L 272#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L 273#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L 274#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L 275#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L 276#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 277//IH_RB_BASE_RING1 278#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 279#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL 280//IH_RB_BASE_HI_RING1 281#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 282#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL 283//IH_RB_RPTR_RING1 284#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 285#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL 286//IH_RB_WPTR_RING1 287#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 288#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 289#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 290#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 291#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L 292#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL 293#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L 294#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L 295//IH_DOORBELL_RPTR_RING1 296#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 297#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c 298#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL 299#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L 300//IH_RB_CNTL_RING2 301#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0 302#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1 303#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7 304#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 305#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa 306#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT 0xb 307#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc 308#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 309#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12 310#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14 311#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16 312#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18 313#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c 314#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 315#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L 316#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL 317#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L 318#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 319#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L 320#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK 0x00000800L 321#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 322#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 323#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L 324#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L 325#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L 326#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L 327#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L 328#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 329//IH_RB_BASE_RING2 330#define IH_RB_BASE_RING2__ADDR__SHIFT 0x0 331#define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL 332//IH_RB_BASE_HI_RING2 333#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0 334#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL 335//IH_RB_RPTR_RING2 336#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2 337#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL 338//IH_RB_WPTR_RING2 339#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0 340#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2 341#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12 342#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13 343#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L 344#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL 345#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L 346#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L 347//IH_DOORBELL_RPTR_RING2 348#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0 349#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c 350#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL 351#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L 352//IH_RETRY_INT_CAM_CNTL 353#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0 354#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8 355#define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10 356#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_ENABLE__SHIFT 0x11 357#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14 358#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL 359#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L 360#define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L 361#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_ENABLE_MASK 0x00020000L 362#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L 363//IH_VERSION 364#define IH_VERSION__MINVER__SHIFT 0x0 365#define IH_VERSION__MAJVER__SHIFT 0x8 366#define IH_VERSION__REV__SHIFT 0x10 367#define IH_VERSION__MINVER_MASK 0x0000007FL 368#define IH_VERSION__MAJVER_MASK 0x00007F00L 369#define IH_VERSION__REV_MASK 0x003F0000L 370//IH_CNTL 371#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 372#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 373#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 374#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 375#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL 376#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L 377#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L 378#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L 379//IH_CNTL2 380#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 381#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 382#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL 383#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L 384//IH_STATUS 385#define IH_STATUS__IDLE__SHIFT 0x0 386#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 387#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 388#define IH_STATUS__RB_FULL__SHIFT 0x3 389#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 390#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 391#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 392#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 393#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 394#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 395#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 396#define IH_STATUS__SWITCH_READY__SHIFT 0xb 397#define IH_STATUS__RB1_FULL__SHIFT 0xc 398#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd 399#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe 400#define IH_STATUS__RB2_FULL__SHIFT 0xf 401#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10 402#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11 403#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 404#define IH_STATUS__IDLE_MASK 0x00000001L 405#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L 406#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L 407#define IH_STATUS__RB_FULL_MASK 0x00000008L 408#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L 409#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L 410#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L 411#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L 412#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L 413#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L 414#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L 415#define IH_STATUS__SWITCH_READY_MASK 0x00000800L 416#define IH_STATUS__RB1_FULL_MASK 0x00001000L 417#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L 418#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L 419#define IH_STATUS__RB2_FULL_MASK 0x00008000L 420#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L 421#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L 422#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L 423//IH_PERFMON_CNTL 424#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 425#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 426#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 427#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 428#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 429#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 430#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L 431#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L 432#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007FCL 433#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L 434#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L 435#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07FC0000L 436//IH_PERFCOUNTER0_RESULT 437#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 438#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 439//IH_PERFCOUNTER1_RESULT 440#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 441#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 442//IH_DSM_MATCH_VALUE_BIT_31_0 443#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 444#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL 445//IH_DSM_MATCH_VALUE_BIT_63_32 446#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 447#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL 448//IH_DSM_MATCH_VALUE_BIT_95_64 449#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 450#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL 451//IH_DSM_MATCH_FIELD_CONTROL 452#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 453#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 454#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 455#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 456#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 457#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 458#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 459#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L 460#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L 461#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L 462#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L 463#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L 464#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L 465#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L 466//IH_DSM_MATCH_DATA_CONTROL 467#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 468#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL 469//IH_DSM_MATCH_FCN_ID 470#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0 471#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1 472#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L 473#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001EL 474//IH_LIMIT_INT_RATE_CNTL 475#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 476#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 477#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 478#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 479#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 480#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L 481#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL 482#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L 483#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L 484#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L 485//IH_VF_RB_STATUS 486#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 487#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 488#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 489#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 490//IH_VF_RB_STATUS2 491#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 492#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 493#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 494#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xFFFF0000L 495//IH_VF_RB1_STATUS 496#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 497#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 498#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 499#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 500//IH_VF_RB1_STATUS2 501#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 502#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 503//IH_VF_RB2_STATUS 504#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 505#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 506#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 507#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 508//IH_VF_RB2_STATUS2 509#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0 510#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 511//IH_INT_FLOOD_CNTL 512#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 513#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 514#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 515#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L 516#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L 517#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L 518//IH_RB0_INT_FLOOD_STATUS 519#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 520#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 521#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 522#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 523//IH_RB1_INT_FLOOD_STATUS 524#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 525#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 526#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 527#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 528//IH_RB2_INT_FLOOD_STATUS 529#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 530#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 531#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 532#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 533//IH_INT_FLOOD_STATUS 534#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 535#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 536#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 537#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 538#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c 539#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e 540#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL 541#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L 542#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L 543#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L 544#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L 545#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L 546//IH_STORM_CLIENT_LIST_CNTL 547#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 548#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 549#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 550#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 551#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 552#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 553#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 554#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 555#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 556#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa 557#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb 558#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc 559#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd 560#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe 561#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf 562#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 563#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 564#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 565#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 566#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 567#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 568#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 569#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 570#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 571#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 572#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a 573#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b 574#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c 575#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d 576#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e 577#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f 578#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L 579#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L 580#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L 581#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L 582#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L 583#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L 584#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L 585#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L 586#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L 587#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L 588#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L 589#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L 590#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L 591#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L 592#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L 593#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L 594#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L 595#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L 596#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L 597#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L 598#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L 599#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L 600#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L 601#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L 602#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L 603#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L 604#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L 605#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L 606#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L 607#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L 608#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L 609//IH_CLK_CTRL 610#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 611#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 612#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b 613#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c 614#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 615#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e 616#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 617#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L 618#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 619#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L 620#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L 621#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 622#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L 623#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 624//IH_INT_FLAGS 625#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 626#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 627#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 628#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 629#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 630#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 631#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 632#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 633#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 634#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 635#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa 636#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb 637#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc 638#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd 639#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe 640#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf 641#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 642#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 643#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 644#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 645#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 646#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 647#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 648#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 649#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 650#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 651#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a 652#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b 653#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c 654#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d 655#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e 656#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f 657#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L 658#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L 659#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L 660#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L 661#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L 662#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L 663#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L 664#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L 665#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L 666#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L 667#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L 668#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L 669#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L 670#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L 671#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L 672#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L 673#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L 674#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L 675#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L 676#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L 677#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L 678#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L 679#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L 680#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L 681#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L 682#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L 683#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L 684#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L 685#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L 686#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L 687#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L 688#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L 689//IH_LAST_INT_INFO0 690#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 691#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 692#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 693#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 694#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f 695#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL 696#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L 697#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L 698#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L 699#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L 700//IH_LAST_INT_INFO1 701#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 702#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL 703//IH_LAST_INT_INFO2 704#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 705#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 706#define IH_LAST_INT_INFO2__VF__SHIFT 0x14 707#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL 708#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L 709#define IH_LAST_INT_INFO2__VF_MASK 0x00100000L 710//IH_SCRATCH 711#define IH_SCRATCH__DATA__SHIFT 0x0 712#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL 713//IH_CLIENT_CREDIT_ERROR 714#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 715#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 716#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 717#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 718#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 719#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 720#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 721#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 722#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 723#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 724#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa 725#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb 726#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc 727#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd 728#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe 729#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf 730#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 731#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 732#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 733#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 734#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 735#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 736#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 737#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 738#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 739#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 740#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a 741#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b 742#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c 743#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d 744#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e 745#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f 746#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L 747#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L 748#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L 749#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L 750#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L 751#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L 752#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L 753#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L 754#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L 755#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L 756#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L 757#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L 758#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L 759#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L 760#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L 761#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L 762#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L 763#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L 764#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L 765#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L 766#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L 767#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L 768#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L 769#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L 770#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L 771#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L 772#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L 773#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L 774#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L 775#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L 776#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L 777#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L 778//IH_GPU_IOV_VIOLATION_LOG 779#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 780#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 781#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 782#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 783#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 784#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 785#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 786#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 787#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 788#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 789#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 790#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 791#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L 792#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 793//IH_COOKIE_REC_VIOLATION_LOG 794#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 795#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x10 796#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 797#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 798#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00FF0000L 799#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 800//IH_CREDIT_STATUS 801#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 802#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 803#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 804#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 805#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 806#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 807#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 808#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 809#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 810#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa 811#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb 812#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc 813#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd 814#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe 815#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf 816#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 817#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 818#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 819#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 820#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 821#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 822#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 823#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 824#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 825#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 826#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a 827#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b 828#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c 829#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d 830#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e 831#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f 832#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L 833#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L 834#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L 835#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L 836#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L 837#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L 838#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L 839#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L 840#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L 841#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L 842#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L 843#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L 844#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L 845#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L 846#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L 847#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L 848#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L 849#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L 850#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L 851#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L 852#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L 853#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L 854#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L 855#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L 856#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L 857#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L 858#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L 859#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L 860#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L 861#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L 862#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L 863//IH_MMHUB_ERROR 864#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 865#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 866#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 867#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 868#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 869#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 870#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L 871#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L 872#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L 873#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L 874#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L 875#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L 876//IH_MEM_POWER_CTRL 877#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 878#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 879#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 880#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 881#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 882#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 883#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe 884#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L 885#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L 886#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L 887#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L 888#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 889#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 890#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L 891//IH_REGISTER_LAST_PART2 892#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 893#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 894//SEM_CLK_CTRL 895#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0 896#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 897#define SEM_CLK_CTRL__RESERVED__SHIFT 0xc 898#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 899#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 900#define SEM_CLK_CTRL__MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 901#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 902#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 903#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 904#define SEM_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e 905#define SEM_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 906#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 907#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 908#define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L 909#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 910#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 911#define SEM_CLK_CTRL__MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 912#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 913#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 914#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 915#define SEM_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L 916#define SEM_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 917//SEM_UTC_CREDIT 918#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0 919#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8 920#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL 921#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L 922//SEM_UTC_CONFIG 923#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0 924#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3 925#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4 926#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5 927#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L 928#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L 929#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L 930#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L 931//SEM_UTCL2_TRAN_EN_LUT 932#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0 933#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1 934#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2 935#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3 936#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4 937#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5 938#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6 939#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7 940#define SEM_UTCL2_TRAN_EN_LUT__UVD1_UTCL2_EN__SHIFT 0x8 941#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x9 942#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f 943#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L 944#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L 945#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L 946#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L 947#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L 948#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L 949#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L 950#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L 951#define SEM_UTCL2_TRAN_EN_LUT__UVD1_UTCL2_EN_MASK 0x00000100L 952#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFE00L 953#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L 954//SEM_MCIF_CONFIG 955#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 956#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 957#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 958#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L 959#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL 960#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L 961//SEM_PERFMON_CNTL 962#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 963#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 964#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 965#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 966#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 967#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 968#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 969#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 970#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 971#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 972#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 973#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 974//SEM_PERFCOUNTER0_RESULT 975#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 976#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 977//SEM_PERFCOUNTER1_RESULT 978#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 979#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 980//SEM_STATUS 981#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 982#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 983#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 984#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 985#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 986#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 987#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 988#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 989#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 990#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 991#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 992#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 993#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 994#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 995#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 996#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf 997#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10 998#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11 999#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12 1000#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13 1001#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14 1002#define SEM_STATUS__MIF_IDLE__SHIFT 0x15 1003#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16 1004#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17 1005#define SEM_STATUS__UVD1_MAILBOX_PENDING__SHIFT 0x18 1006#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f 1007#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L 1008#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L 1009#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L 1010#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L 1011#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L 1012#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L 1013#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L 1014#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L 1015#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L 1016#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L 1017#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L 1018#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L 1019#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L 1020#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L 1021#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L 1022#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L 1023#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L 1024#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L 1025#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L 1026#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L 1027#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L 1028#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L 1029#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L 1030#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L 1031#define SEM_STATUS__UVD1_MAILBOX_PENDING_MASK 0x01000000L 1032#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L 1033//SEM_MAILBOX_CLIENTCONFIG 1034#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 1035#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 1036#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 1037#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 1038#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 1039#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 1040#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 1041#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 1042#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L 1043#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L 1044#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L 1045#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L 1046#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L 1047#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L 1048#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L 1049#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L 1050//SEM_MAILBOX 1051#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 1052#define SEM_MAILBOX__RESERVED__SHIFT 0x10 1053#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL 1054#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L 1055//SEM_MAILBOX_CONTROL 1056#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0 1057#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10 1058#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL 1059#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L 1060//SEM_CHICKEN_BITS 1061#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 1062#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 1063#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 1064#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 1065#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 1066#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 1067#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 1068#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa 1069#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc 1070#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe 1071#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf 1072#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10 1073#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12 1074#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13 1075#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L 1076#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L 1077#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L 1078#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L 1079#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L 1080#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L 1081#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L 1082#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L 1083#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L 1084#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L 1085#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L 1086#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L 1087#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L 1088#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L 1089//SEM_MAILBOX_CLIENTCONFIG_EXTRA 1090#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 1091#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__UVD1_CLIENT0__SHIFT 0x4 1092#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL 1093#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__UVD1_CLIENT0_MASK 0x000000F0L 1094//SEM_GPU_IOV_VIOLATION_LOG 1095#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1096#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1097#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1098#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 1099#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1100#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 1101#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1102#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1103#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1104#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1105#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 1106#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1107#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L 1108#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1109//SEM_OUTSTANDING_THRESHOLD 1110#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0 1111#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL 1112//SEM_MEM_POWER_CTRL 1113#define SEM_MEM_POWER_CTRL__MEM_POWER_CTRL_EN__SHIFT 0x0 1114#define SEM_MEM_POWER_CTRL__MEM_POWER_LS_EN__SHIFT 0x1 1115#define SEM_MEM_POWER_CTRL__MEM_POWER_DS_EN__SHIFT 0x2 1116#define SEM_MEM_POWER_CTRL__MEM_POWER_SD_EN__SHIFT 0x3 1117#define SEM_MEM_POWER_CTRL__MEM_IDLE_HYSTERESIS__SHIFT 0x4 1118#define SEM_MEM_POWER_CTRL__MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 1119#define SEM_MEM_POWER_CTRL__MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe 1120#define SEM_MEM_POWER_CTRL__MEM_POWER_CTRL_EN_MASK 0x00000001L 1121#define SEM_MEM_POWER_CTRL__MEM_POWER_LS_EN_MASK 0x00000002L 1122#define SEM_MEM_POWER_CTRL__MEM_POWER_DS_EN_MASK 0x00000004L 1123#define SEM_MEM_POWER_CTRL__MEM_POWER_SD_EN_MASK 0x00000008L 1124#define SEM_MEM_POWER_CTRL__MEM_IDLE_HYSTERESIS_MASK 0x00000070L 1125#define SEM_MEM_POWER_CTRL__MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 1126#define SEM_MEM_POWER_CTRL__MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L 1127//SEM_REGISTER_LAST_PART2 1128#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 1129#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 1130//IH_ACTIVE_FCN_ID 1131#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 1132#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 1133#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 1134#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL 1135#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 1136#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 1137//IH_VIRT_RESET_REQ 1138#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 1139#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f 1140#define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 1141#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L 1142//IH_CLIENT_CFG 1143#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 1144#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL 1145//IH_CLIENT_CFG_INDEX 1146#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 1147#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL 1148//IH_CLIENT_CFG_DATA 1149#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0 1150#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 1151#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14 1152#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 1153#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 1154#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0003FFFFL 1155#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L 1156#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L 1157#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L 1158#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L 1159//IH_CID_REMAP_INDEX 1160#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 1161#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 1162//IH_CID_REMAP_DATA 1163#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 1164#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 1165#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 1166#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 1167#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L 1168#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L 1169//IH_CHICKEN 1170#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 1171#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 1172#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 1173#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 1174#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L 1175#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L 1176//IH_MMHUB_CNTL 1177#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 1178#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 1179#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc 1180#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL 1181#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L 1182#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L 1183//IH_INT_DROP_CNTL 1184#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 1185#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 1186#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 1187#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 1188#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 1189#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 1190#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 1191#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 1192#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 1193#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L 1194#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L 1195#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L 1196#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L 1197#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L 1198#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L 1199#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L 1200#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L 1201#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L 1202//IH_INT_DROP_MATCH_VALUE0 1203#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 1204#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 1205#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 1206#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 1207#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 1208#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL 1209#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L 1210#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x000F0000L 1211#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L 1212#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L 1213//IH_INT_DROP_MATCH_VALUE1 1214#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 1215#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL 1216//IH_INT_DROP_MATCH_MASK0 1217#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 1218#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 1219#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 1220#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 1221#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 1222#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL 1223#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L 1224#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x000F0000L 1225#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L 1226#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L 1227//IH_INT_DROP_MATCH_MASK1 1228#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 1229#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL 1230//IH_REGISTER_LAST_PART1 1231#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1232#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1233//SEM_ACTIVE_FCN_ID 1234#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1235#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1236#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 1237#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L 1238//SEM_VIRT_RESET_REQ 1239#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 1240#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f 1241#define SEM_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 1242#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L 1243//SEM_RESP_SDMA0 1244#define SEM_RESP_SDMA0__ADDR__SHIFT 0x2 1245#define SEM_RESP_SDMA0__ADDR_MASK 0x000FFFFCL 1246//SEM_RESP_SDMA1 1247#define SEM_RESP_SDMA1__ADDR__SHIFT 0x2 1248#define SEM_RESP_SDMA1__ADDR_MASK 0x000FFFFCL 1249//SEM_RESP_UVD 1250#define SEM_RESP_UVD__ADDR__SHIFT 0x2 1251#define SEM_RESP_UVD__ADDR_MASK 0x000FFFFCL 1252//SEM_RESP_VCE_0 1253#define SEM_RESP_VCE_0__ADDR__SHIFT 0x2 1254#define SEM_RESP_VCE_0__ADDR_MASK 0x000FFFFCL 1255//SEM_RESP_ACP 1256#define SEM_RESP_ACP__ADDR__SHIFT 0x2 1257#define SEM_RESP_ACP__ADDR_MASK 0x000FFFFCL 1258//SEM_RESP_ISP 1259#define SEM_RESP_ISP__ADDR__SHIFT 0x2 1260#define SEM_RESP_ISP__ADDR_MASK 0x000FFFFCL 1261//SEM_RESP_VCE_1 1262#define SEM_RESP_VCE_1__ADDR__SHIFT 0x2 1263#define SEM_RESP_VCE_1__ADDR_MASK 0x000FFFFCL 1264//SEM_RESP_VP8 1265#define SEM_RESP_VP8__ADDR__SHIFT 0x2 1266#define SEM_RESP_VP8__ADDR_MASK 0x000FFFFCL 1267//SEM_RESP_GC 1268#define SEM_RESP_GC__ADDR__SHIFT 0x2 1269#define SEM_RESP_GC__ADDR_MASK 0x000FFFFCL 1270//SEM_RESP_UVD_1 1271#define SEM_RESP_UVD_1__ADDR__SHIFT 0x2 1272#define SEM_RESP_UVD_1__ADDR_MASK 0x000FFFFCL 1273//SEM_CID_REMAP_INDEX 1274#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0 1275#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 1276//SEM_CID_REMAP_DATA 1277#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 1278#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 1279#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 1280#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 1281#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L 1282#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L 1283//SEM_ATOMIC_OP_LUT 1284#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0 1285#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7 1286#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe 1287#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15 1288#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL 1289#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L 1290#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L 1291#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L 1292//SEM_EDC_CONFIG 1293#define SEM_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 1294#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 1295#define SEM_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L 1296#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 1297//SEM_CHICKEN_BITS2 1298#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 1299#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1 1300#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 1301#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L 1302//SEM_MMHUB_CNTL 1303#define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 1304#define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8 1305#define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 1306#define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L 1307//SEM_REGISTER_LAST_PART1 1308#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1309#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1310 1311#endif 1312