1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _mp_13_0_6_SH_MASK_HEADER 24#define _mp_13_0_6_SH_MASK_HEADER 25 26 27// addressBlock: aid_mp_SmuMp0_SmnDec 28//MP0_SMN_C2PMSG_32 29#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 30#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 31//MP0_SMN_C2PMSG_33 32#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 33#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 34//MP0_SMN_C2PMSG_34 35#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 36#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 37//MP0_SMN_C2PMSG_35 38#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 39#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 40//MP0_SMN_C2PMSG_36 41#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 42#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 43//MP0_SMN_C2PMSG_37 44#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 45#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 46//MP0_SMN_C2PMSG_38 47#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 48#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 49//MP0_SMN_C2PMSG_39 50#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 51#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 52//MP0_SMN_C2PMSG_40 53#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 54#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 55//MP0_SMN_C2PMSG_41 56#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 57#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 58//MP0_SMN_C2PMSG_42 59#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 60#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 61//MP0_SMN_C2PMSG_43 62#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 63#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 64//MP0_SMN_C2PMSG_44 65#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 66#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 67//MP0_SMN_C2PMSG_45 68#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 69#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 70//MP0_SMN_C2PMSG_46 71#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 72#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 73//MP0_SMN_C2PMSG_47 74#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 75#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 76//MP0_SMN_C2PMSG_48 77#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 78#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 79//MP0_SMN_C2PMSG_49 80#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 81#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 82//MP0_SMN_C2PMSG_50 83#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 84#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 85//MP0_SMN_C2PMSG_51 86#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 87#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 88//MP0_SMN_C2PMSG_52 89#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 90#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 91//MP0_SMN_C2PMSG_53 92#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 93#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 94//MP0_SMN_C2PMSG_54 95#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 96#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 97//MP0_SMN_C2PMSG_55 98#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 99#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 100//MP0_SMN_C2PMSG_56 101#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 102#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 103//MP0_SMN_C2PMSG_57 104#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 105#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 106//MP0_SMN_C2PMSG_58 107#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 108#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 109//MP0_SMN_C2PMSG_59 110#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 111#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 112//MP0_SMN_C2PMSG_60 113#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 114#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 115//MP0_SMN_C2PMSG_61 116#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 117#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 118//MP0_SMN_C2PMSG_62 119#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 120#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 121//MP0_SMN_C2PMSG_63 122#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 123#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 124//MP0_SMN_C2PMSG_64 125#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 126#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 127//MP0_SMN_C2PMSG_65 128#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 129#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 130//MP0_SMN_C2PMSG_66 131#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 132#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 133//MP0_SMN_C2PMSG_67 134#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 135#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 136//MP0_SMN_C2PMSG_68 137#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 138#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 139//MP0_SMN_C2PMSG_69 140#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 141#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 142//MP0_SMN_C2PMSG_70 143#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 144#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 145//MP0_SMN_C2PMSG_71 146#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 147#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 148//MP0_SMN_C2PMSG_72 149#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 150#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 151//MP0_SMN_C2PMSG_73 152#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 153#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 154//MP0_SMN_C2PMSG_74 155#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 156#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 157//MP0_SMN_C2PMSG_75 158#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 159#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 160//MP0_SMN_C2PMSG_76 161#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 162#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 163//MP0_SMN_C2PMSG_77 164#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 165#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 166//MP0_SMN_C2PMSG_78 167#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 168#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 169//MP0_SMN_C2PMSG_79 170#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 171#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 172//MP0_SMN_C2PMSG_80 173#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 174#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 175//MP0_SMN_C2PMSG_81 176#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 177#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 178//MP0_SMN_C2PMSG_82 179#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 180#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 181//MP0_SMN_C2PMSG_83 182#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 183#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 184//MP0_SMN_C2PMSG_84 185#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 186#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 187//MP0_SMN_C2PMSG_85 188#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 189#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 190//MP0_SMN_C2PMSG_86 191#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 192#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 193//MP0_SMN_C2PMSG_87 194#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 195#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 196//MP0_SMN_C2PMSG_88 197#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 198#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 199//MP0_SMN_C2PMSG_89 200#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 201#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 202//MP0_SMN_C2PMSG_90 203#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 204#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 205//MP0_SMN_C2PMSG_91 206#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 207#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 208//MP0_SMN_C2PMSG_92 209#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 210#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 211//MP0_SMN_C2PMSG_93 212#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 213#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 214//MP0_SMN_C2PMSG_94 215#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 216#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 217//MP0_SMN_C2PMSG_95 218#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 219#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 220//MP0_SMN_C2PMSG_96 221#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 222#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 223//MP0_SMN_C2PMSG_97 224#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 225#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 226//MP0_SMN_C2PMSG_98 227#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 228#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 229//MP0_SMN_C2PMSG_99 230#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 231#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 232//MP0_SMN_C2PMSG_100 233#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 234#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 235//MP0_SMN_C2PMSG_101 236#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 237#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 238//MP0_SMN_C2PMSG_102 239#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 240#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 241//MP0_SMN_C2PMSG_103 242#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 243#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 244//MP0_SMN_IH_CREDIT 245#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 246#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 247#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 248#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 249//MP0_SMN_IH_SW_INT 250#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 251#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 252#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL 253#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L 254//MP0_SMN_IH_SW_INT_CTRL 255#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 256#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 257#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 258#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 259 260 261// addressBlock: aid_mp_SmuMp1_SmnDec 262//MP1_SMN_C2PMSG_32 263#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 264#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 265//MP1_SMN_C2PMSG_33 266#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 267#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 268//MP1_SMN_C2PMSG_34 269#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 270#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 271//MP1_SMN_C2PMSG_35 272#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 273#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 274//MP1_SMN_C2PMSG_36 275#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 276#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 277//MP1_SMN_C2PMSG_37 278#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 279#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 280//MP1_SMN_C2PMSG_38 281#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 282#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 283//MP1_SMN_C2PMSG_39 284#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 285#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 286//MP1_SMN_C2PMSG_40 287#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 288#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 289//MP1_SMN_C2PMSG_41 290#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 291#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 292//MP1_SMN_C2PMSG_42 293#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 294#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 295//MP1_SMN_C2PMSG_43 296#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 297#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 298//MP1_SMN_C2PMSG_44 299#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 300#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 301//MP1_SMN_C2PMSG_45 302#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 303#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 304//MP1_SMN_C2PMSG_46 305#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 306#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 307//MP1_SMN_C2PMSG_47 308#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 309#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 310//MP1_SMN_C2PMSG_48 311#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 312#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 313//MP1_SMN_C2PMSG_49 314#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 315#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 316//MP1_SMN_C2PMSG_50 317#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 318#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 319//MP1_SMN_C2PMSG_51 320#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 321#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 322//MP1_SMN_C2PMSG_52 323#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 324#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 325//MP1_SMN_C2PMSG_53 326#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 327#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 328//MP1_SMN_C2PMSG_54 329#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 330#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 331//MP1_SMN_C2PMSG_55 332#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 333#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 334//MP1_SMN_C2PMSG_56 335#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 336#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 337//MP1_SMN_C2PMSG_57 338#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 339#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 340//MP1_SMN_C2PMSG_58 341#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 342#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 343//MP1_SMN_C2PMSG_59 344#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 345#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 346//MP1_SMN_C2PMSG_60 347#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 348#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 349//MP1_SMN_C2PMSG_61 350#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 351#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 352//MP1_SMN_C2PMSG_62 353#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 354#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 355//MP1_SMN_C2PMSG_63 356#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 357#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 358//MP1_SMN_C2PMSG_64 359#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 360#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 361//MP1_SMN_C2PMSG_65 362#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 363#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 364//MP1_SMN_C2PMSG_66 365#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 366#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 367//MP1_SMN_C2PMSG_67 368#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 369#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 370//MP1_SMN_C2PMSG_68 371#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 372#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 373//MP1_SMN_C2PMSG_69 374#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 375#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 376//MP1_SMN_C2PMSG_70 377#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 378#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 379//MP1_SMN_C2PMSG_71 380#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 381#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 382//MP1_SMN_C2PMSG_72 383#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 384#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 385//MP1_SMN_C2PMSG_73 386#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 387#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 388//MP1_SMN_C2PMSG_74 389#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 390#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 391//MP1_SMN_C2PMSG_75 392#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 393#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 394//MP1_SMN_C2PMSG_76 395#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 396#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 397//MP1_SMN_C2PMSG_77 398#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 399#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 400//MP1_SMN_C2PMSG_78 401#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 402#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 403//MP1_SMN_C2PMSG_79 404#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 405#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 406//MP1_SMN_C2PMSG_80 407#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 408#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 409//MP1_SMN_C2PMSG_81 410#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 411#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 412//MP1_SMN_C2PMSG_82 413#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 414#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 415//MP1_SMN_C2PMSG_83 416#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 417#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 418//MP1_SMN_C2PMSG_84 419#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 420#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 421//MP1_SMN_C2PMSG_85 422#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 423#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 424//MP1_SMN_C2PMSG_86 425#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 426#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 427//MP1_SMN_C2PMSG_87 428#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 429#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 430//MP1_SMN_C2PMSG_88 431#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 432#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 433//MP1_SMN_C2PMSG_89 434#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 435#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 436//MP1_SMN_C2PMSG_90 437#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 438#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 439//MP1_SMN_C2PMSG_91 440#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 441#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 442//MP1_SMN_C2PMSG_92 443#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 444#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 445//MP1_SMN_C2PMSG_93 446#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 447#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 448//MP1_SMN_C2PMSG_94 449#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 450#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 451//MP1_SMN_C2PMSG_95 452#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 453#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 454//MP1_SMN_C2PMSG_96 455#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 456#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 457//MP1_SMN_C2PMSG_97 458#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 459#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 460//MP1_SMN_C2PMSG_98 461#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 462#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 463//MP1_SMN_C2PMSG_99 464#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 465#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 466//MP1_SMN_C2PMSG_100 467#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 468#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 469//MP1_SMN_C2PMSG_101 470#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 471#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 472//MP1_SMN_C2PMSG_102 473#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 474#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 475//MP1_SMN_C2PMSG_103 476#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 477#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 478//MP1_SMN_C2PMSG_104 479#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 480#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 481//MP1_SMN_C2PMSG_105 482#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 483#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 484//MP1_SMN_C2PMSG_106 485#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 486#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 487//MP1_SMN_C2PMSG_107 488#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 489#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 490//MP1_SMN_C2PMSG_108 491#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 492#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 493//MP1_SMN_C2PMSG_109 494#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 495#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 496//MP1_SMN_C2PMSG_110 497#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 498#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 499//MP1_SMN_C2PMSG_111 500#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 501#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 502//MP1_SMN_C2PMSG_112 503#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 504#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 505//MP1_SMN_C2PMSG_113 506#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 507#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 508//MP1_SMN_C2PMSG_114 509#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 510#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 511//MP1_SMN_C2PMSG_115 512#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 513#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 514//MP1_SMN_C2PMSG_116 515#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 516#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 517//MP1_SMN_C2PMSG_117 518#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 519#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 520//MP1_SMN_C2PMSG_118 521#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 522#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 523//MP1_SMN_C2PMSG_119 524#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 525#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 526//MP1_SMN_C2PMSG_120 527#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 528#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 529//MP1_SMN_C2PMSG_121 530#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 531#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 532//MP1_SMN_C2PMSG_122 533#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 534#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 535//MP1_SMN_C2PMSG_123 536#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 537#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 538//MP1_SMN_C2PMSG_124 539#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 540#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 541//MP1_SMN_C2PMSG_125 542#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 543#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 544//MP1_SMN_C2PMSG_126 545#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 546#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 547//MP1_SMN_C2PMSG_127 548#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 549#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 550//MP1_SMN_IH_CREDIT 551#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 552#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 553#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 554#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 555//MP1_SMN_IH_SW_INT 556#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 557#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 558#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 559#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 560//MP1_SMN_IH_SW_INT_CTRL 561#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 562#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 563#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 564#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 565//MP1_SMN_FPS_CNT 566#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 567#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 568//MP1_SMN_PUB_CTRL 569#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT 0x0 570#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK 0x00000001L 571//MP1_SMN_EXT_SCRATCH0 572#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 573#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 574//MP1_SMN_EXT_SCRATCH1 575#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 576#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 577//MP1_SMN_EXT_SCRATCH2 578#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 579#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 580//MP1_SMN_EXT_SCRATCH3 581#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 582#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 583//MP1_SMN_EXT_SCRATCH4 584#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 585#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 586//MP1_SMN_EXT_SCRATCH5 587#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 588#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 589//MP1_SMN_EXT_SCRATCH6 590#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 591#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 592//MP1_SMN_EXT_SCRATCH7 593#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 594#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 595//MP1_SMN_EXT_SCRATCH8 596#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 597#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL 598//MP1_SMN_EXT_SCRATCH10 599#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 600#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL 601//MP1_SMN_EXT_SCRATCH11 602#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 603#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL 604//MP1_SMN_EXT_SCRATCH12 605#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 606#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL 607//MP1_SMN_EXT_SCRATCH13 608#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 609#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL 610//MP1_SMN_EXT_SCRATCH14 611#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 612#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL 613//MP1_SMN_EXT_SCRATCH15 614#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 615#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL 616//MP1_SMN_EXT_SCRATCH16 617#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 618#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL 619//MP1_SMN_EXT_SCRATCH17 620#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 621#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL 622//MP1_SMN_EXT_SCRATCH18 623#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 624#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL 625//MP1_SMN_EXT_SCRATCH19 626#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 627#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL 628//MP1_SMN_EXT_SCRATCH20 629#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 630#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL 631//MP1_SMN_EXT_SCRATCH21 632#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 633#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL 634//MP1_SMN_EXT_SCRATCH22 635#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 636#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL 637//MP1_SMN_EXT_SCRATCH23 638#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 639#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL 640//MP1_SMN_EXT_SCRATCH24 641#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 642#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL 643//MP1_SMN_EXT_SCRATCH25 644#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 645#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL 646//MP1_SMN_EXT_SCRATCH26 647#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 648#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL 649//MP1_SMN_EXT_SCRATCH27 650#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 651#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL 652//MP1_SMN_EXT_SCRATCH28 653#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 654#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL 655//MP1_SMN_EXT_SCRATCH29 656#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 657#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL 658//MP1_SMN_EXT_SCRATCH30 659#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 660#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL 661//MP1_SMN_EXT_SCRATCH31 662#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 663#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL 664 665 666// addressBlock: aid_mp_SmuMp1Pub_CruDec 667//MP1_FIRMWARE_FLAGS 668#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 669#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 670#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 671#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 672 673//MCMP1_IPIDT0 674#define MCMP1_IPIDT0__InstanceIdLo__SHIFT 0x0 675#define MCMP1_IPIDT0__HardwareID__SHIFT 0x20 676#define MCMP1_IPIDT0__InstanceIdHi__SHIFT 0x2c 677#define MCMP1_IPIDT0__McaType__SHIFT 0x30 678 679#define MCMP1_IPIDT0__InstanceIdLo_MASK 0x00000000FFFFFFFFL 680#define MCMP1_IPIDT0__HardwareID_MASK 0x00000FFF00000000L 681#define MCMP1_IPIDT0__InstanceIdHi_MASK 0x0000F00000000000L 682#define MCMP1_IPIDT0__McaType_MASK 0xFFFF000000000000L 683 684//MCMP1_STATUST0 685#define MCMP1_STATUST0__ErrorCode__SHIFT 0x0 686#define MCMP1_STATUST0__ErrorCodeExt__SHIFT 0x10 687#define MCMP1_STATUST0__PCC__SHIFT 0x39 688#define MCMP1_STATUST0__UC__SHIFT 0x3d 689#define MCMP1_STATUST0__Val__SHIFT 0x3f 690 691#define MCMP1_STATUST0__ErrorCode_MASK 0x000000000000FFFFL 692#define MCMP1_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L 693#define MCMP1_STATUST0__PCC_MASK 0x0200000000000000L 694#define MCMP1_STATUST0__UC_MASK 0x2000000000000000L 695#define MCMP1_STATUST0__Val_MASK 0x8000000000000000L 696 697//MCMP1_MISC0T0 698#define MCMP1_MISC0T0__ErrCnt__SHIFT 0x20 699 700#define MCMP1_MISC0T0__ErrCnt_MASK 0x00000FFF00000000L 701 702#endif 703