1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dce110/dce110_hwseq.h"
27#include "dcn10/dcn10_hwseq.h"
28#include "dcn20/dcn20_hwseq.h"
29#include "dcn21/dcn21_hwseq.h"
30#include "dcn30/dcn30_hwseq.h"
31#include "dcn301/dcn301_hwseq.h"
32#include "dcn31/dcn31_hwseq.h"
33#include "dcn32/dcn32_hwseq.h"
34#include "dcn35/dcn35_hwseq.h"
35
36#include "dcn351_init.h"
37
38static const struct hw_sequencer_funcs dcn351_funcs = {
39	.program_gamut_remap = dcn30_program_gamut_remap,
40	.init_hw = dcn35_init_hw,
41	.power_down_on_boot = dcn35_power_down_on_boot,
42	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
43	.apply_ctx_for_surface = NULL,
44	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
45	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
46	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
47	.update_plane_addr = dcn20_update_plane_addr,
48	.update_dchub = dcn10_update_dchub,
49	.update_pending_status = dcn10_update_pending_status,
50	.program_output_csc = dcn20_program_output_csc,
51	.enable_accelerated_mode = dce110_enable_accelerated_mode,
52	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
53	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
54	.update_info_frame = dcn31_update_info_frame,
55	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
56	.enable_stream = dcn20_enable_stream,
57	.disable_stream = dce110_disable_stream,
58	.unblank_stream = dcn32_unblank_stream,
59	.blank_stream = dce110_blank_stream,
60	.enable_audio_stream = dce110_enable_audio_stream,
61	.disable_audio_stream = dce110_disable_audio_stream,
62	.disable_plane = dcn35_disable_plane,
63	.disable_pixel_data = dcn20_disable_pixel_data,
64	.pipe_control_lock = dcn20_pipe_control_lock,
65	.interdependent_update_lock = dcn10_lock_all_pipes,
66	.cursor_lock = dcn10_cursor_lock,
67	.prepare_bandwidth = dcn35_prepare_bandwidth,
68	.optimize_bandwidth = dcn35_optimize_bandwidth,
69	.update_bandwidth = dcn20_update_bandwidth,
70	.set_drr = dcn35_set_drr,
71	.get_position = dcn10_get_position,
72	.set_static_screen_control = dcn35_set_static_screen_control,
73	.setup_stereo = dcn10_setup_stereo,
74	.set_avmute = dcn30_set_avmute,
75	.log_hw_state = dcn10_log_hw_state,
76	.get_hw_state = dcn10_get_hw_state,
77	.clear_status_bits = dcn10_clear_status_bits,
78	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
79	.edp_backlight_control = dce110_edp_backlight_control,
80	.edp_power_control = dce110_edp_power_control,
81	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
82	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
83	.set_cursor_position = dcn10_set_cursor_position,
84	.set_cursor_attribute = dcn10_set_cursor_attribute,
85	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
86	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
87	.set_clock = dcn10_set_clock,
88	.get_clock = dcn10_get_clock,
89	.program_triplebuffer = dcn20_program_triple_buffer,
90	.enable_writeback = dcn30_enable_writeback,
91	.disable_writeback = dcn30_disable_writeback,
92	.update_writeback = dcn30_update_writeback,
93	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
94	.dmdata_status_done = dcn20_dmdata_status_done,
95	.program_dmdata_engine = dcn30_program_dmdata_engine,
96	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
97	.init_sys_ctx = dcn31_init_sys_ctx,
98	.init_vm_ctx = dcn20_init_vm_ctx,
99	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
100	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
101	.calc_vupdate_position = dcn10_calc_vupdate_position,
102	.power_down = dce110_power_down,
103	.set_backlight_level = dcn21_set_backlight_level,
104	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
105	.set_pipe = dcn21_set_pipe,
106	.enable_lvds_link_output = dce110_enable_lvds_link_output,
107	.enable_tmds_link_output = dce110_enable_tmds_link_output,
108	.enable_dp_link_output = dce110_enable_dp_link_output,
109	.disable_link_output = dcn32_disable_link_output,
110	.z10_restore = dcn35_z10_restore,
111	.z10_save_init = dcn31_z10_save_init,
112	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
113	.optimize_pwr_state = dcn21_optimize_pwr_state,
114	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
115	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
116	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
117	.update_dsc_pg = dcn32_update_dsc_pg,
118	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
119	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
120	.hw_block_power_up = dcn35_hw_block_power_up,
121	.hw_block_power_down = dcn35_hw_block_power_down,
122	.root_clock_control = dcn35_root_clock_control,
123	.set_idle_state = dcn35_set_idle_state,
124	.get_idle_state = dcn35_get_idle_state
125};
126
127static const struct hwseq_private_funcs dcn351_private_funcs = {
128	.init_pipes = dcn35_init_pipes,
129	.update_plane_addr = dcn20_update_plane_addr,
130	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
131	.update_mpcc = dcn20_update_mpcc,
132	.set_input_transfer_func = dcn32_set_input_transfer_func,
133	.set_output_transfer_func = dcn32_set_output_transfer_func,
134	.power_down = dce110_power_down,
135	.enable_display_power_gating = dcn10_dummy_display_power_gating,
136	.blank_pixel_data = dcn20_blank_pixel_data,
137	.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
138	.enable_stream_timing = dcn20_enable_stream_timing,
139	.edp_backlight_control = dce110_edp_backlight_control,
140	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
141	.did_underflow_occur = dcn10_did_underflow_occur,
142	.init_blank = dcn20_init_blank,
143	.disable_vga = NULL,
144	.bios_golden_init = dcn10_bios_golden_init,
145	.plane_atomic_disable = dcn35_plane_atomic_disable,
146	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/
147	//.hubp_pg_control = dcn35_hubp_pg_control,
148	.enable_power_gating_plane = dcn35_enable_power_gating_plane,
149	.dpp_root_clock_control = dcn35_dpp_root_clock_control,
150	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
151	.update_odm = dcn35_update_odm,
152	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
153	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
154	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
155	.dccg_init = dcn20_dccg_init,
156	.set_mcm_luts = dcn32_set_mcm_luts,
157	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
158	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
159	.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
160	.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
161	.dsc_pg_control = dcn35_dsc_pg_control,
162	.dsc_pg_status = dcn32_dsc_pg_status,
163	.enable_plane = dcn35_enable_plane,
164};
165
166void dcn351_hw_sequencer_construct(struct dc *dc)
167{
168	dc->hwss = dcn351_funcs;
169	dc->hwseq->funcs = dcn351_private_funcs;
170
171}
172