1/*
2 * Copyright 2016-2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dce110/dce110_hwseq.h"
27#include "dcn10/dcn10_hwseq.h"
28#include "dcn20/dcn20_hwseq.h"
29#include "dcn21/dcn21_hwseq.h"
30#include "dcn30/dcn30_hwseq.h"
31
32#include "dcn30_init.h"
33
34static const struct hw_sequencer_funcs dcn30_funcs = {
35	.program_gamut_remap = dcn30_program_gamut_remap,
36	.init_hw = dcn30_init_hw,
37	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
38	.apply_ctx_for_surface = NULL,
39	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
40	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
41	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
42	.update_plane_addr = dcn20_update_plane_addr,
43	.update_dchub = dcn10_update_dchub,
44	.update_pending_status = dcn10_update_pending_status,
45	.program_output_csc = dcn20_program_output_csc,
46	.enable_accelerated_mode = dce110_enable_accelerated_mode,
47	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
48	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
49	.update_info_frame = dcn30_update_info_frame,
50	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
51	.enable_stream = dcn20_enable_stream,
52	.disable_stream = dce110_disable_stream,
53	.unblank_stream = dcn20_unblank_stream,
54	.blank_stream = dce110_blank_stream,
55	.enable_audio_stream = dce110_enable_audio_stream,
56	.disable_audio_stream = dce110_disable_audio_stream,
57	.disable_plane = dcn20_disable_plane,
58	.disable_pixel_data = dcn20_disable_pixel_data,
59	.pipe_control_lock = dcn20_pipe_control_lock,
60	.interdependent_update_lock = dcn10_lock_all_pipes,
61	.cursor_lock = dcn10_cursor_lock,
62	.prepare_bandwidth = dcn30_prepare_bandwidth,
63	.optimize_bandwidth = dcn20_optimize_bandwidth,
64	.update_bandwidth = dcn20_update_bandwidth,
65	.set_drr = dcn10_set_drr,
66	.get_position = dcn10_get_position,
67	.set_static_screen_control = dcn10_set_static_screen_control,
68	.setup_stereo = dcn10_setup_stereo,
69	.set_avmute = dcn30_set_avmute,
70	.log_hw_state = dcn10_log_hw_state,
71	.get_hw_state = dcn10_get_hw_state,
72	.clear_status_bits = dcn10_clear_status_bits,
73	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
74	.edp_backlight_control = dce110_edp_backlight_control,
75	.edp_power_control = dce110_edp_power_control,
76	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
77	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
78	.set_cursor_position = dcn10_set_cursor_position,
79	.set_cursor_attribute = dcn10_set_cursor_attribute,
80	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
81	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
82	.set_clock = dcn10_set_clock,
83	.get_clock = dcn10_get_clock,
84	.program_triplebuffer = dcn20_program_triple_buffer,
85	.enable_writeback = dcn30_enable_writeback,
86	.disable_writeback = dcn30_disable_writeback,
87	.update_writeback = dcn30_update_writeback,
88	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
89	.dmdata_status_done = dcn20_dmdata_status_done,
90	.program_dmdata_engine = dcn30_program_dmdata_engine,
91	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
92	.init_sys_ctx = dcn20_init_sys_ctx,
93	.init_vm_ctx = dcn20_init_vm_ctx,
94	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
95	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
96	.calc_vupdate_position = dcn10_calc_vupdate_position,
97	.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
98	.does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall,
99	.set_backlight_level = dcn21_set_backlight_level,
100	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
101	.hardware_release = dcn30_hardware_release,
102	.set_pipe = dcn21_set_pipe,
103	.enable_lvds_link_output = dce110_enable_lvds_link_output,
104	.enable_tmds_link_output = dce110_enable_tmds_link_output,
105	.enable_dp_link_output = dce110_enable_dp_link_output,
106	.disable_link_output = dce110_disable_link_output,
107	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
108	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
109	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
110	.is_abm_supported = dcn21_is_abm_supported
111};
112
113static const struct hwseq_private_funcs dcn30_private_funcs = {
114	.init_pipes = dcn10_init_pipes,
115	.update_plane_addr = dcn20_update_plane_addr,
116	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
117	.update_mpcc = dcn20_update_mpcc,
118	.set_input_transfer_func = dcn30_set_input_transfer_func,
119	.set_output_transfer_func = dcn30_set_output_transfer_func,
120	.power_down = dce110_power_down,
121	.enable_display_power_gating = dcn10_dummy_display_power_gating,
122	.blank_pixel_data = dcn20_blank_pixel_data,
123	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
124	.enable_stream_timing = dcn20_enable_stream_timing,
125	.edp_backlight_control = dce110_edp_backlight_control,
126	.disable_stream_gating = dcn20_disable_stream_gating,
127	.enable_stream_gating = dcn20_enable_stream_gating,
128	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
129	.did_underflow_occur = dcn10_did_underflow_occur,
130	.init_blank = dcn20_init_blank,
131	.disable_vga = dcn20_disable_vga,
132	.bios_golden_init = dcn10_bios_golden_init,
133	.plane_atomic_disable = dcn20_plane_atomic_disable,
134	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
135	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
136	.dpp_pg_control = dcn20_dpp_pg_control,
137	.hubp_pg_control = dcn20_hubp_pg_control,
138	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
139	.update_odm = dcn20_update_odm,
140	.dsc_pg_control = dcn20_dsc_pg_control,
141	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
142	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
143	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
144	.dccg_init = dcn20_dccg_init,
145	.set_blend_lut = dcn30_set_blend_lut,
146	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
147};
148
149void dcn30_hw_sequencer_construct(struct dc *dc)
150{
151	dc->hwss = dcn30_funcs;
152	dc->hwseq->funcs = dcn30_private_funcs;
153
154}
155