1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "core_types.h"
28#include "dcn35/dcn35_dpp.h"
29#include "reg_helper.h"
30
31#define REG(reg) dpp->tf_regs->reg
32
33#define CTX dpp->base.ctx
34
35#undef FN
36#define FN(reg_name, field_name)                                       \
37	((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \
38	((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name
39
40void dpp35_dppclk_control(
41		struct dpp *dpp_base,
42		bool dppclk_div,
43		bool enable)
44{
45	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
46
47	if (enable) {
48		if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
49			REG_UPDATE_2(DPP_CONTROL,
50				DPPCLK_RATE_CONTROL, dppclk_div,
51				DPP_CLOCK_ENABLE, 1);
52		else
53			REG_UPDATE_2(DPP_CONTROL,
54					DPP_CLOCK_ENABLE, 1,
55					DISPCLK_R_GATE_DISABLE, 1);
56	} else
57		REG_UPDATE_2(DPP_CONTROL,
58				DPP_CLOCK_ENABLE, 0,
59				DISPCLK_R_GATE_DISABLE, 0);
60}
61
62static struct dpp_funcs dcn35_dpp_funcs = {
63	.dpp_program_gamcor_lut		= dpp3_program_gamcor_lut,
64	.dpp_read_state				= dpp30_read_state,
65	.dpp_reset					= dpp_reset,
66	.dpp_set_scaler				= dpp1_dscl_set_scaler_manual_scale,
67	.dpp_get_optimal_number_of_taps	= dpp3_get_optimal_number_of_taps,
68	.dpp_set_gamut_remap		= dpp3_cm_set_gamut_remap,
69	.dpp_set_csc_adjustment		= NULL,
70	.dpp_set_csc_default		= NULL,
71	.dpp_program_regamma_pwl	= NULL,
72	.dpp_set_pre_degam			= dpp3_set_pre_degam,
73	.dpp_program_input_lut		= NULL,
74	.dpp_full_bypass			= dpp1_full_bypass,
75	.dpp_setup					= dpp3_cnv_setup,
76	.dpp_program_degamma_pwl	= NULL,
77	.dpp_program_cm_dealpha		= dpp3_program_cm_dealpha,
78	.dpp_program_cm_bias		= dpp3_program_cm_bias,
79
80	.dpp_program_blnd_lut		= NULL, // BLNDGAM is removed completely in DCN3.2 DPP
81	.dpp_program_shaper_lut		= NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
82	.dpp_program_3dlut			= NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
83
84	.dpp_program_bias_and_scale	= NULL,
85	.dpp_cnv_set_alpha_keyer	= dpp2_cnv_set_alpha_keyer,
86	.set_cursor_attributes		= dpp3_set_cursor_attributes,
87	.set_cursor_position		= dpp1_set_cursor_position,
88	.set_optional_cursor_attributes	= dpp1_cnv_set_optional_cursor_attributes,
89	.dpp_dppclk_control			= dpp35_dppclk_control,
90	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,
91	.dpp_get_gamut_remap		= dpp3_cm_get_gamut_remap,
92};
93
94
95bool dpp35_construct(
96	struct dcn3_dpp *dpp, struct dc_context *ctx,
97	uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
98	const struct dcn35_dpp_shift *tf_shift,
99	const struct dcn35_dpp_mask *tf_mask)
100{
101	bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,
102			      (const struct dcn3_dpp_shift *)(tf_shift),
103			      (const struct dcn3_dpp_mask *)(tf_mask));
104
105	dpp->base.funcs = &dcn35_dpp_funcs;
106	return ret;
107}
108
109void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)
110{
111	REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);
112}
113