1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25#ifndef __DC_FEATURES_H__ 26#define __DC_FEATURES_H__ 27 28// local features 29#define DC__PRESENT 1 30#define DC__PRESENT__1 1 31#define DC__NUM_DPP 4 32 33/** 34 * @DC__VOLTAGE_STATES: 35 * 36 * Define the maximum amount of states supported by the ASIC. Every ASIC has a 37 * specific number of states; this macro defines the maximum number of states. 38 */ 39#define DC__VOLTAGE_STATES 40 40#define DC__NUM_DPP__4 1 41#define DC__NUM_DPP__0_PRESENT 1 42#define DC__NUM_DPP__1_PRESENT 1 43#define DC__NUM_DPP__2_PRESENT 1 44#define DC__NUM_DPP__3_PRESENT 1 45#define DC__NUM_DPP__MAX 8 46#define DC__NUM_DPP__MAX__8 1 47#define DC__PIPE_10BIT 0 48#define DC__PIPE_10BIT__0 1 49#define DC__PIPE_10BIT__MAX 1 50#define DC__PIPE_10BIT__MAX__1 1 51#define DC__NUM_OPP 4 52#define DC__NUM_OPP__4 1 53#define DC__NUM_OPP__0_PRESENT 1 54#define DC__NUM_OPP__1_PRESENT 1 55#define DC__NUM_OPP__2_PRESENT 1 56#define DC__NUM_OPP__3_PRESENT 1 57#define DC__NUM_OPP__MAX 6 58#define DC__NUM_OPP__MAX__6 1 59#define DC__NUM_DSC 0 60#define DC__NUM_DSC__0 1 61#define DC__NUM_DSC__MAX 6 62#define DC__NUM_DSC__MAX__6 1 63#define DC__NUM_ABM 1 64#define DC__NUM_ABM__1 1 65#define DC__NUM_ABM__0_PRESENT 1 66#define DC__NUM_ABM__MAX 2 67#define DC__NUM_ABM__MAX__2 1 68#define DC__ODM_PRESENT 0 69#define DC__ODM_PRESENT__0 1 70#define DC__NUM_OTG 4 71#define DC__NUM_OTG__4 1 72#define DC__NUM_OTG__0_PRESENT 1 73#define DC__NUM_OTG__1_PRESENT 1 74#define DC__NUM_OTG__2_PRESENT 1 75#define DC__NUM_OTG__3_PRESENT 1 76#define DC__NUM_OTG__MAX 6 77#define DC__NUM_OTG__MAX__6 1 78#define DC__NUM_DWB 2 79#define DC__NUM_DWB__2 1 80#define DC__NUM_DWB__0_PRESENT 1 81#define DC__NUM_DWB__1_PRESENT 1 82#define DC__NUM_DWB__MAX 2 83#define DC__NUM_DWB__MAX__2 1 84#define DC__NUM_DIG 4 85#define DC__NUM_DIG__4 1 86#define DC__NUM_DIG__0_PRESENT 1 87#define DC__NUM_DIG__1_PRESENT 1 88#define DC__NUM_DIG__2_PRESENT 1 89#define DC__NUM_DIG__3_PRESENT 1 90#define DC__NUM_DIG__MAX 6 91#define DC__NUM_DIG__MAX__6 1 92#define DC__NUM_AUX 4 93#define DC__NUM_AUX__4 1 94#define DC__NUM_AUX__0_PRESENT 1 95#define DC__NUM_AUX__1_PRESENT 1 96#define DC__NUM_AUX__2_PRESENT 1 97#define DC__NUM_AUX__3_PRESENT 1 98#define DC__NUM_AUX__MAX 6 99#define DC__NUM_AUX__MAX__6 1 100#define DC__NUM_AUDIO_STREAMS 4 101#define DC__NUM_AUDIO_STREAMS__4 1 102#define DC__NUM_AUDIO_STREAMS__0_PRESENT 1 103#define DC__NUM_AUDIO_STREAMS__1_PRESENT 1 104#define DC__NUM_AUDIO_STREAMS__2_PRESENT 1 105#define DC__NUM_AUDIO_STREAMS__3_PRESENT 1 106#define DC__NUM_AUDIO_STREAMS__MAX 8 107#define DC__NUM_AUDIO_STREAMS__MAX__8 1 108#define DC__NUM_AUDIO_ENDPOINTS 6 109#define DC__NUM_AUDIO_ENDPOINTS__6 1 110#define DC__NUM_AUDIO_ENDPOINTS__0_PRESENT 1 111#define DC__NUM_AUDIO_ENDPOINTS__1_PRESENT 1 112#define DC__NUM_AUDIO_ENDPOINTS__2_PRESENT 1 113#define DC__NUM_AUDIO_ENDPOINTS__3_PRESENT 1 114#define DC__NUM_AUDIO_ENDPOINTS__4_PRESENT 1 115#define DC__NUM_AUDIO_ENDPOINTS__5_PRESENT 1 116#define DC__NUM_AUDIO_ENDPOINTS__MAX 8 117#define DC__NUM_AUDIO_ENDPOINTS__MAX__8 1 118#define DC__NUM_AUDIO_INPUT_STREAMS 0 119#define DC__NUM_AUDIO_INPUT_STREAMS__0 1 120#define DC__NUM_AUDIO_INPUT_STREAMS__MAX 8 121#define DC__NUM_AUDIO_INPUT_STREAMS__MAX__8 1 122#define DC__NUM_AUDIO_INPUT_ENDPOINTS 0 123#define DC__NUM_AUDIO_INPUT_ENDPOINTS__0 1 124#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX 8 125#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8 1 126#define DC__NUM_CURSOR 1 127#define DC__NUM_CURSOR__1 1 128#define DC__NUM_CURSOR__0_PRESENT 1 129#define DC__NUM_CURSOR__MAX 2 130#define DC__NUM_CURSOR__MAX__2 1 131#define DC__DIGITAL_BYPASS_PRESENT 0 132#define DC__DIGITAL_BYPASS_PRESENT__0 1 133#define DC__HCID_HWMAJVER 1 134#define DC__HCID_HWMAJVER__1 1 135#define DC__HCID_HWMINVER 0 136#define DC__HCID_HWMINVER__0 1 137#define DC__HCID_HWREV 0 138#define DC__HCID_HWREV__0 1 139#define DC__ROMSTRAP_PRESENT 0 140#define DC__ROMSTRAP_PRESENT__0 1 141#define DC__NUM_RBBMIF_DECODES 30 142#define DC__NUM_RBBMIF_DECODES__30 1 143#define DC__NUM_DBG_REGS 36 144#define DC__NUM_DBG_REGS__36 1 145#define DC__NUM_PIPES_UNDERLAY 0 146#define DC__NUM_PIPES_UNDERLAY__0 1 147#define DC__NUM_PIPES_UNDERLAY__MAX 2 148#define DC__NUM_PIPES_UNDERLAY__MAX__2 1 149#define DC__NUM_VCE_ENGINE 1 150#define DC__NUM_VCE_ENGINE__1 1 151#define DC__NUM_VCE_ENGINE__0_PRESENT 1 152#define DC__NUM_VCE_ENGINE__MAX 2 153#define DC__NUM_VCE_ENGINE__MAX__2 1 154#define DC__OTG_EXTERNAL_SYNC_PRESENT 0 155#define DC__OTG_EXTERNAL_SYNC_PRESENT__0 1 156#define DC__OTG_CRC_PRESENT 1 157#define DC__OTG_CRC_PRESENT__1 1 158#define DC__VIP_PRESENT 0 159#define DC__VIP_PRESENT__0 1 160#define DC__DTMTEST_PRESENT 0 161#define DC__DTMTEST_PRESENT__0 1 162#define DC__POWER_GATE_PRESENT 1 163#define DC__POWER_GATE_PRESENT__1 1 164#define DC__MEM_PG 1 165#define DC__MEM_PG__1 1 166#define DC__FMT_SRC_SEL_PRESENT 0 167#define DC__FMT_SRC_SEL_PRESENT__0 1 168#define DC__DIG_FEATURES__HDMI_PRESENT 1 169#define DC__DIG_FEATURES__HDMI_PRESENT__1 1 170#define DC__DIG_FEATURES__DP_PRESENT 1 171#define DC__DIG_FEATURES__DP_PRESENT__1 1 172#define DC__DIG_FEATURES__DP_MST_PRESENT 1 173#define DC__DIG_FEATURES__DP_MST_PRESENT__1 1 174#define DC__DIG_LP_FEATURES__HDMI_PRESENT 0 175#define DC__DIG_LP_FEATURES__HDMI_PRESENT__0 1 176#define DC__DIG_LP_FEATURES__DP_PRESENT 1 177#define DC__DIG_LP_FEATURES__DP_PRESENT__1 1 178#define DC__DIG_LP_FEATURES__DP_MST_PRESENT 0 179#define DC__DIG_LP_FEATURES__DP_MST_PRESENT__0 1 180#define DC__DIG_RESYNC_FIFO_SIZE 14 181#define DC__DIG_RESYNC_FIFO_SIZE__14 1 182#define DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT 1 183#define DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT 1 184#define DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT 1 185#define DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT 1 186#define DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT 1 187#define DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT 1 188#define DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT 1 189#define DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT 1 190#define DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT 1 191#define DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT 1 192#define DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT 1 193#define DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT 1 194#define DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT 1 195#define DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT 1 196#define DC__DIG_RESYNC_FIFO_SIZE__MAX 16 197#define DC__DIG_RESYNC_FIFO_SIZE__MAX__16 1 198#define DC__DAC_RESYNC_FIFO_SIZE 12 199#define DC__DAC_RESYNC_FIFO_SIZE__12 1 200#define DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT 1 201#define DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT 1 202#define DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT 1 203#define DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT 1 204#define DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT 1 205#define DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT 1 206#define DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT 1 207#define DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT 1 208#define DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT 1 209#define DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT 1 210#define DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT 1 211#define DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT 1 212#define DC__DAC_RESYNC_FIFO_SIZE__MAX 16 213#define DC__DAC_RESYNC_FIFO_SIZE__MAX__16 1 214#define DC__DVO_RESYNC_FIFO_SIZE 12 215#define DC__DVO_RESYNC_FIFO_SIZE__12 1 216#define DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT 1 217#define DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT 1 218#define DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT 1 219#define DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT 1 220#define DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT 1 221#define DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT 1 222#define DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT 1 223#define DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT 1 224#define DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT 1 225#define DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT 1 226#define DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT 1 227#define DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT 1 228#define DC__DVO_RESYNC_FIFO_SIZE__MAX 16 229#define DC__DVO_RESYNC_FIFO_SIZE__MAX__16 1 230#define DC__MEM_CDC_PRESENT 1 231#define DC__MEM_CDC_PRESENT__1 1 232#define DC__NUM_HPD 4 233#define DC__NUM_HPD__4 1 234#define DC__NUM_HPD__0_PRESENT 1 235#define DC__NUM_HPD__1_PRESENT 1 236#define DC__NUM_HPD__2_PRESENT 1 237#define DC__NUM_HPD__3_PRESENT 1 238#define DC__NUM_HPD__MAX 6 239#define DC__NUM_HPD__MAX__6 1 240#define DC__NUM_DDC_PAIRS 4 241#define DC__NUM_DDC_PAIRS__4 1 242#define DC__NUM_DDC_PAIRS__0_PRESENT 1 243#define DC__NUM_DDC_PAIRS__1_PRESENT 1 244#define DC__NUM_DDC_PAIRS__2_PRESENT 1 245#define DC__NUM_DDC_PAIRS__3_PRESENT 1 246#define DC__NUM_DDC_PAIRS__MAX 6 247#define DC__NUM_DDC_PAIRS__MAX__6 1 248#define DC__NUM_AUDIO_PLL 0 249#define DC__NUM_AUDIO_PLL__0 1 250#define DC__NUM_AUDIO_PLL__MAX 2 251#define DC__NUM_AUDIO_PLL__MAX__2 1 252#define DC__NUM_PIXEL_PLL 1 253#define DC__NUM_PIXEL_PLL__1 1 254#define DC__NUM_PIXEL_PLL__0_PRESENT 1 255#define DC__NUM_PIXEL_PLL__MAX 4 256#define DC__NUM_PIXEL_PLL__MAX__4 1 257#define DC__NUM_CASCADED_PLL 0 258#define DC__NUM_CASCADED_PLL__0 1 259#define DC__NUM_CASCADED_PLL__MAX 3 260#define DC__NUM_CASCADED_PLL__MAX__3 1 261#define DC__PIXCLK_FROM_PHYPLL 1 262#define DC__PIXCLK_FROM_PHYPLL__1 1 263#define DC__NB_STUTTER_MODE_PRESENT 0 264#define DC__NB_STUTTER_MODE_PRESENT__0 1 265#define DC__I2S0_AND_SPDIF0_PRESENT 0 266#define DC__I2S0_AND_SPDIF0_PRESENT__0 1 267#define DC__I2S1_PRESENT 0 268#define DC__I2S1_PRESENT__0 1 269#define DC__SPDIF1_PRESENT 0 270#define DC__SPDIF1_PRESENT__0 1 271#define DC__DSI_PRESENT 0 272#define DC__DSI_PRESENT__0 1 273#define DC__DACA_PRESENT 0 274#define DC__DACA_PRESENT__0 1 275#define DC__DACB_PRESENT 0 276#define DC__DACB_PRESENT__0 1 277#define DC__NUM_PIPES 4 278#define DC__NUM_PIPES__4 1 279#define DC__NUM_PIPES__0_PRESENT 1 280#define DC__NUM_PIPES__1_PRESENT 1 281#define DC__NUM_PIPES__2_PRESENT 1 282#define DC__NUM_PIPES__3_PRESENT 1 283#define DC__NUM_PIPES__MAX 6 284#define DC__NUM_PIPES__MAX__6 1 285#define DC__NUM_DIG_LP 0 286#define DC__NUM_DIG_LP__0 1 287#define DC__NUM_DIG_LP__MAX 2 288#define DC__NUM_DIG_LP__MAX__2 1 289#define DC__DPDEBUG_PRESENT 0 290#define DC__DPDEBUG_PRESENT__0 1 291#define DC__DISPLAY_WB_PRESENT 1 292#define DC__DISPLAY_WB_PRESENT__1 1 293#define DC__NUM_CWB 0 294#define DC__NUM_CWB__0 1 295#define DC__NUM_CWB__MAX 2 296#define DC__NUM_CWB__MAX__2 1 297#define DC__MVP_PRESENT 0 298#define DC__MVP_PRESENT__0 1 299#define DC__DVO_PRESENT 0 300#define DC__DVO_PRESENT__0 1 301#define DC__ABM_PRESENT 0 302#define DC__ABM_PRESENT__0 1 303#define DC__BPHYC_PLL_PRESENT 0 304#define DC__BPHYC_PLL_PRESENT__0 1 305#define DC__BPHYC_UNIPHY_PRESENT 0 306#define DC__BPHYC_UNIPHY_PRESENT__0 1 307#define DC__PHY_BROADCAST_PRESENT 0 308#define DC__PHY_BROADCAST_PRESENT__0 1 309#define DC__NUM_OF_DCRX_SD 0 310#define DC__NUM_OF_DCRX_SD__0 1 311#define DC__DVO_17BIT_MAPPING 0 312#define DC__DVO_17BIT_MAPPING__0 1 313#define DC__AVSYNC_PRESENT 0 314#define DC__AVSYNC_PRESENT__0 1 315#define DC__NUM_OF_DCRX_PORTS 0 316#define DC__NUM_OF_DCRX_PORTS__0 1 317#define DC__NUM_OF_DCRX_PORTS__MAX 1 318#define DC__NUM_OF_DCRX_PORTS__MAX__1 1 319#define DC__NUM_PHY 4 320#define DC__NUM_PHY__4 1 321#define DC__NUM_PHY__0_PRESENT 1 322#define DC__NUM_PHY__1_PRESENT 1 323#define DC__NUM_PHY__2_PRESENT 1 324#define DC__NUM_PHY__3_PRESENT 1 325#define DC__NUM_PHY__MAX 7 326#define DC__NUM_PHY__MAX__7 1 327#define DC__NUM_PHY_LP 0 328#define DC__NUM_PHY_LP__0 1 329#define DC__NUM_PHY_LP__MAX 2 330#define DC__NUM_PHY_LP__MAX__2 1 331#define DC__SYNC_CELL vid_sync_gf14lpp 332#define DC__SYNC_CELL__VID_SYNC_GF14LPP 1 333#define DC__USE_NEW_VSS 1 334#define DC__USE_NEW_VSS__1 1 335#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES 6 336#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6 1 337#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES 6 338#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6 1 339#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES 6 340#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6 1 341#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES 6 342#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6 1 343#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES 6 344#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6 1 345#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES 6 346#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6 1 347#define DC__SYNC_CELL_REFCLK_NUM_LATCHES 6 348#define DC__SYNC_CELL_REFCLK_NUM_LATCHES__6 1 349#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES 6 350#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6 1 351#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES 6 352#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6 1 353#define DC__SYNC_CELL_SCLK_NUM_LATCHES 6 354#define DC__SYNC_CELL_SCLK_NUM_LATCHES__6 1 355#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES 6 356#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6 1 357#define DC__SYNC_CELL_AMCLK_NUM_LATCHES 6 358#define DC__SYNC_CELL_AMCLK_NUM_LATCHES__6 1 359#define DC__SYNC_CELL_DSICLK_NUM_LATCHES 6 360#define DC__SYNC_CELL_DSICLK_NUM_LATCHES__6 1 361#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES 6 362#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6 1 363#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES 6 364#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6 1 365#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES 6 366#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6 1 367#define UNIPHYA_PRESENT 1 368#define UNIPHYA_PRESENT__1 1 369#define DC__UNIPHYA_PRESENT 1 370#define DC__UNIPHYA_PRESENT__1 1 371#define UNIPHYB_PRESENT 1 372#define UNIPHYB_PRESENT__1 1 373#define DC__UNIPHYB_PRESENT 1 374#define DC__UNIPHYB_PRESENT__1 1 375#define UNIPHYC_PRESENT 1 376#define UNIPHYC_PRESENT__1 1 377#define DC__UNIPHYC_PRESENT 1 378#define DC__UNIPHYC_PRESENT__1 1 379#define UNIPHYD_PRESENT 1 380#define UNIPHYD_PRESENT__1 1 381#define DC__UNIPHYD_PRESENT 1 382#define DC__UNIPHYD_PRESENT__1 1 383#define UNIPHYE_PRESENT 0 384#define UNIPHYE_PRESENT__0 1 385#define DC__UNIPHYE_PRESENT 0 386#define DC__UNIPHYE_PRESENT__0 1 387#define UNIPHYF_PRESENT 0 388#define UNIPHYF_PRESENT__0 1 389#define DC__UNIPHYF_PRESENT 0 390#define DC__UNIPHYF_PRESENT__0 1 391#define UNIPHYG_PRESENT 0 392#define UNIPHYG_PRESENT__0 1 393#define DC__UNIPHYG_PRESENT 0 394#define DC__UNIPHYG_PRESENT__0 1 395#define DC__TMDS_LINK tmds_link_dual 396#define DC__TMDS_LINK__TMDS_LINK_DUAL 1 397#define DC__WBSCL_PIXBW 8 398#define DC__WBSCL_PIXBW__8 1 399#define DC__DWB_CSC_PRESENT 0 400#define DC__DWB_CSC_PRESENT__0 1 401#define DC__DWB_LUMA_SCL_PRESENT 0 402#define DC__DWB_LUMA_SCL_PRESENT__0 1 403#define DC__DENTIST_INTERFACE_PRESENT 1 404#define DC__DENTIST_INTERFACE_PRESENT__1 1 405#define DC__GENERICA_PRESENT 1 406#define DC__GENERICA_PRESENT__1 1 407#define DC__GENERICB_PRESENT 1 408#define DC__GENERICB_PRESENT__1 1 409#define DC__GENERICC_PRESENT 0 410#define DC__GENERICC_PRESENT__0 1 411#define DC__GENERICD_PRESENT 0 412#define DC__GENERICD_PRESENT__0 1 413#define DC__GENERICE_PRESENT 0 414#define DC__GENERICE_PRESENT__0 1 415#define DC__GENERICF_PRESENT 0 416#define DC__GENERICF_PRESENT__0 1 417#define DC__GENERICG_PRESENT 0 418#define DC__GENERICG_PRESENT__0 1 419#define DC__UNIPHY_VOLTAGE_MODE 1 420#define DC__UNIPHY_VOLTAGE_MODE__1 1 421#define DC__BLON_TYPE dedicated 422#define DC__BLON_TYPE__DEDICATED 1 423#define DC__UNIPHY_STAGGER_CH_PRESENT 1 424#define DC__UNIPHY_STAGGER_CH_PRESENT__1 1 425#define DC__XDMA_PRESENT 0 426#define DC__XDMA_PRESENT__0 1 427#define XDMA__PRESENT 0 428#define XDMA__PRESENT__0 1 429#define DC__DP_MEM_PG 0 430#define DC__DP_MEM_PG__0 1 431#define DP__MEM_PG 0 432#define DP__MEM_PG__0 1 433#define DC__AFMT_MEM_PG 0 434#define DC__AFMT_MEM_PG__0 1 435#define AFMT__MEM_PG 0 436#define AFMT__MEM_PG__0 1 437#define DC__HDMI_MEM_PG 0 438#define DC__HDMI_MEM_PG__0 1 439#define HDMI__MEM_PG 0 440#define HDMI__MEM_PG__0 1 441#define DC__I2C_MEM_PG 0 442#define DC__I2C_MEM_PG__0 1 443#define I2C__MEM_PG 0 444#define I2C__MEM_PG__0 1 445#define DC__DSCL_MEM_PG 0 446#define DC__DSCL_MEM_PG__0 1 447#define DSCL__MEM_PG 0 448#define DSCL__MEM_PG__0 1 449#define DC__CM_MEM_PG 0 450#define DC__CM_MEM_PG__0 1 451#define CM__MEM_PG 0 452#define CM__MEM_PG__0 1 453#define DC__OBUF_MEM_PG 0 454#define DC__OBUF_MEM_PG__0 1 455#define OBUF__MEM_PG 0 456#define OBUF__MEM_PG__0 1 457#define DC__WBIF_MEM_PG 1 458#define DC__WBIF_MEM_PG__1 1 459#define WBIF__MEM_PG 1 460#define WBIF__MEM_PG__1 1 461#define DC__VGA_MEM_PG 0 462#define DC__VGA_MEM_PG__0 1 463#define VGA__MEM_PG 0 464#define VGA__MEM_PG__0 1 465#define DC__FMT_MEM_PG 0 466#define DC__FMT_MEM_PG__0 1 467#define FMT__MEM_PG 0 468#define FMT__MEM_PG__0 1 469#define DC__ODM_MEM_PG 0 470#define DC__ODM_MEM_PG__0 1 471#define ODM__MEM_PG 0 472#define ODM__MEM_PG__0 1 473#define DC__DSI_MEM_PG 0 474#define DC__DSI_MEM_PG__0 1 475#define DSI__MEM_PG 0 476#define DSI__MEM_PG__0 1 477#define DC__AZ_MEM_PG 1 478#define DC__AZ_MEM_PG__1 1 479#define AZ__MEM_PG 1 480#define AZ__MEM_PG__1 1 481#define DC__WBSCL_MEM1P1024X64QS_MEM_PG 1 482#define DC__WBSCL_MEM1P1024X64QS_MEM_PG__1 1 483#define WBSCL_MEM1P1024X64QS__MEM_PG 1 484#define WBSCL_MEM1P1024X64QS__MEM_PG__1 1 485#define DC__WBSCL_MEM1P528X64QS_MEM_PG 1 486#define DC__WBSCL_MEM1P528X64QS_MEM_PG__1 1 487#define WBSCL_MEM1P528X64QS__MEM_PG 1 488#define WBSCL_MEM1P528X64QS__MEM_PG__1 1 489#define DC__DMCU_MEM1P1024X32BQS_MEM_PG 1 490#define DC__DMCU_MEM1P1024X32BQS_MEM_PG__1 1 491#define DMCU_MEM1P1024X32BQS__MEM_PG 1 492#define DMCU_MEM1P1024X32BQS__MEM_PG__1 1 493#define DC__HUBBUB_SDP_TAG_INT_MEM_PG 0 494#define DC__HUBBUB_SDP_TAG_INT_MEM_PG__0 1 495#define HUBBUB_SDP_TAG_INT__MEM_PG 0 496#define HUBBUB_SDP_TAG_INT__MEM_PG__0 1 497#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG 0 498#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0 1 499#define HUBBUB_SDP_TAG_EXT__MEM_PG 0 500#define HUBBUB_SDP_TAG_EXT__MEM_PG__0 1 501#define DC__HUBBUB_RET_ZERO_MEM_PG 0 502#define DC__HUBBUB_RET_ZERO_MEM_PG__0 1 503#define HUBBUB_RET_ZERO__MEM_PG 0 504#define HUBBUB_RET_ZERO__MEM_PG__0 1 505#define DC__HUBBUB_RET_ROB_MEM_PG 0 506#define DC__HUBBUB_RET_ROB_MEM_PG__0 1 507#define HUBBUB_RET_ROB__MEM_PG 0 508#define HUBBUB_RET_ROB__MEM_PG__0 1 509#define DC__HUBPRET_CUR_ROB_MEM_PG 0 510#define DC__HUBPRET_CUR_ROB_MEM_PG__0 1 511#define HUBPRET_CUR_ROB__MEM_PG 0 512#define HUBPRET_CUR_ROB__MEM_PG__0 1 513#define DC__HUBPRET_CUR_CDC_MEM_PG 0 514#define DC__HUBPRET_CUR_CDC_MEM_PG__0 1 515#define HUBPRET_CUR_CDC__MEM_PG 0 516#define HUBPRET_CUR_CDC__MEM_PG__0 1 517#define DC__HUBPREQ_MPTE_MEM_PG 0 518#define DC__HUBPREQ_MPTE_MEM_PG__0 1 519#define HUBPREQ_MPTE__MEM_PG 0 520#define HUBPREQ_MPTE__MEM_PG__0 1 521#define DC__HUBPREQ_META_MEM_PG 0 522#define DC__HUBPREQ_META_MEM_PG__0 1 523#define HUBPREQ_META__MEM_PG 0 524#define HUBPREQ_META__MEM_PG__0 1 525#define DC__HUBPREQ_DPTE_MEM_PG 0 526#define DC__HUBPREQ_DPTE_MEM_PG__0 1 527#define HUBPREQ_DPTE__MEM_PG 0 528#define HUBPREQ_DPTE__MEM_PG__0 1 529#define DC__HUBPRET_DET_MEM_PG 0 530#define DC__HUBPRET_DET_MEM_PG__0 1 531#define HUBPRET_DET__MEM_PG 0 532#define HUBPRET_DET__MEM_PG__0 1 533#define DC__HUBPRET_PIX_CDC_MEM_PG 0 534#define DC__HUBPRET_PIX_CDC_MEM_PG__0 1 535#define HUBPRET_PIX_CDC__MEM_PG 0 536#define HUBPRET_PIX_CDC__MEM_PG__0 1 537#define DC__TOP_BLKS__DCCG 1 538#define DC__TOP_BLKS__DCHUBBUB 1 539#define DC__TOP_BLKS__DCHUBP 1 540#define DC__TOP_BLKS__HDA 1 541#define DC__TOP_BLKS__DIO 1 542#define DC__TOP_BLKS__DCIO 1 543#define DC__TOP_BLKS__DMU 1 544#define DC__TOP_BLKS__DPP 1 545#define DC__TOP_BLKS__MPC 1 546#define DC__TOP_BLKS__OPP 1 547#define DC__TOP_BLKS__OPTC 1 548#define DC__TOP_BLKS__MMHUBBUB 1 549#define DC__TOP_BLKS__WB 1 550#define DC__TOP_BLKS__MAX 13 551#define DC__TOP_BLKS__MAX__13 1 552#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS 9 553#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9 1 554#define DC__DPP_MPC_SF_PIXEL_CREDITS 9 555#define DC__DPP_MPC_SF_PIXEL_CREDITS__9 1 556#define DC__MPC_OPP_SF_PIXEL_CREDITS 8 557#define DC__MPC_OPP_SF_PIXEL_CREDITS__8 1 558#define DC__OPP_OPTC_SF_PIXEL_CREDITS 8 559#define DC__OPP_OPTC_SF_PIXEL_CREDITS__8 1 560#define DC__SFR_SFT_ROUND_TRIP_DELAY 5 561#define DC__SFR_SFT_ROUND_TRIP_DELAY__5 1 562#define DC__REPEATER_PROJECT_MAX 8 563#define DC__REPEATER_PROJECT_MAX__8 1 564#define DC__SURFACE_422_CAPABLE 0 565#define DC__SURFACE_422_CAPABLE__0 1 566#endif 567