1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26#ifndef DALSMC_H
27#define DALSMC_H
28
29#define DALSMC_VERSION 0x1
30
31// SMU Response Codes:
32#define DALSMC_Result_OK                   0x1
33#define DALSMC_Result_Failed               0xFF
34#define DALSMC_Result_UnknownCmd           0xFE
35#define DALSMC_Result_CmdRejectedPrereq    0xFD
36#define DALSMC_Result_CmdRejectedBusy      0xFC
37
38// Message Definitions:
39#define DALSMC_MSG_TestMessage                    0x1
40#define DALSMC_MSG_GetSmuVersion                  0x2
41#define DALSMC_MSG_GetDriverIfVersion             0x3
42#define DALSMC_MSG_GetMsgHeaderVersion            0x4
43#define DALSMC_MSG_SetDalDramAddrHigh             0x5
44#define DALSMC_MSG_SetDalDramAddrLow              0x6
45#define DALSMC_MSG_TransferTableSmu2Dram          0x7
46#define DALSMC_MSG_TransferTableDram2Smu          0x8
47#define DALSMC_MSG_SetHardMinByFreq               0x9
48#define DALSMC_MSG_SetHardMaxByFreq               0xA
49#define DALSMC_MSG_GetDpmFreqByIndex              0xB
50#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC
51#define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD
52#define DALSMC_MSG_NumOfDisplays                  0xE
53#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF
54#define DALSMC_MSG_BacoAudioD3PME                 0x10
55#define DALSMC_MSG_SetFclkSwitchAllow             0x11
56#define DALSMC_MSG_SetCabForUclkPstate            0x12
57#define DALSMC_MSG_SetWorstCaseUclkLatency        0x13
58#define DALSMC_MSG_SetAlwaysWaitDmcubResp         0x14
59#define DALSMC_MSG_ReturnHardMinStatus            0x15
60#define DALSMC_Message_Count                      0x16
61
62#define CHECK_HARD_MIN_CLK_DISPCLK                0x1
63#define CHECK_HARD_MIN_CLK_DPPCLK                 0x2
64#define CHECK_HARD_MIN_CLK_DPREFCLK               0x4
65#define CHECK_HARD_MIN_CLK_DCFCLK                 0x8
66#define CHECK_HARD_MIN_CLK_DTBCLK                 0x10
67#define CHECK_HARD_MIN_CLK_UCLK                   0x20
68
69typedef enum {
70	FCLK_SWITCH_DISALLOW,
71	FCLK_SWITCH_ALLOW,
72} FclkSwitchAllow_e;
73
74#endif
75