1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "gfxhub_v1_1.h"
25
26#include "gc/gc_9_2_1_offset.h"
27#include "gc/gc_9_2_1_sh_mask.h"
28
29#include "soc15_common.h"
30
31#define mmMC_VM_XGMI_LFB_CNTL_ALDE			0x0978
32#define mmMC_VM_XGMI_LFB_CNTL_ALDE_BASE_IDX		0
33#define mmMC_VM_XGMI_LFB_SIZE_ALDE			0x0979
34#define mmMC_VM_XGMI_LFB_SIZE_ALDE_BASE_IDX		0
35//MC_VM_XGMI_LFB_CNTL
36#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION__SHIFT	0x0
37#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION__SHIFT	0x4
38#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION_MASK	0x0000000FL
39#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION_MASK	0x000000F0L
40//MC_VM_XGMI_LFB_SIZE
41#define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE__SHIFT	0x0
42#define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE_MASK	0x0001FFFFL
43
44int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
45{
46	u32 max_num_physical_nodes;
47	u32 max_physical_node_id;
48	u32 xgmi_lfb_cntl;
49	u32 max_region;
50	u64 seg_size;
51
52	if (adev->asic_type == CHIP_ALDEBARAN) {
53		xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE);
54		seg_size = REG_GET_FIELD(
55			RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),
56			MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
57		max_region =
58			REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION);
59	} else {
60		xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
61		seg_size = REG_GET_FIELD(
62			RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
63			MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
64		max_region =
65			REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
66	}
67
68
69
70	switch (adev->asic_type) {
71	case CHIP_VEGA20:
72		max_num_physical_nodes   = 4;
73		max_physical_node_id     = 3;
74		break;
75	case CHIP_ARCTURUS:
76		max_num_physical_nodes   = 8;
77		max_physical_node_id     = 7;
78		break;
79	case CHIP_ALDEBARAN:
80		max_num_physical_nodes   = 16;
81		max_physical_node_id     = 15;
82		break;
83	default:
84		return -EINVAL;
85	}
86
87	/* PF_MAX_REGION=0 means xgmi is disabled */
88	if (max_region || adev->gmc.xgmi.connected_to_cpu) {
89		adev->gmc.xgmi.num_physical_nodes = max_region + 1;
90
91		if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
92			return -EINVAL;
93
94		if (adev->asic_type == CHIP_ALDEBARAN) {
95			adev->gmc.xgmi.physical_node_id =
96				REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
97						PF_LFB_REGION);
98		} else {
99			adev->gmc.xgmi.physical_node_id =
100				REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
101						PF_LFB_REGION);
102		}
103
104		if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
105			return -EINVAL;
106
107		adev->gmc.xgmi.node_segment_size = seg_size;
108	}
109
110	return 0;
111}
112